[llvm] 3e4e5db - [AMDGPU] shl_add_ptr.ll - regenerate test checks
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 9 09:50:17 PDT 2025
Author: Simon Pilgrim
Date: 2025-07-09T17:50:07+01:00
New Revision: 3e4e5dbc2599e08fb2cadc3829869b18a7c17667
URL: https://github.com/llvm/llvm-project/commit/3e4e5dbc2599e08fb2cadc3829869b18a7c17667
DIFF: https://github.com/llvm/llvm-project/commit/3e4e5dbc2599e08fb2cadc3829869b18a7c17667.diff
LOG: [AMDGPU] shl_add_ptr.ll - regenerate test checks
Added:
Modified:
llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll b/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
index fe838872169c6..47cc01445896c 100644
--- a/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
@@ -1,12 +1,12 @@
-; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
; Test that doing a shift of a pointer with a constant add will be
; folded into the constant offset addressing mode even if the add has
; multiple uses. This is relevant to accessing 2 separate, adjacent
; LDS globals.
-
declare i32 @llvm.amdgcn.workitem.id.x() #1
@lds0 = addrspace(3) global [512 x float] poison, align 4
@@ -14,12 +14,46 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 8
-
-; GCN-LABEL: {{^}}load_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @load_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: load_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_read_b32 v1, v1 offset:8
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: load_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: ds_read_b32 v1, v1 offset:8
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
@@ -31,15 +65,46 @@ define amdgpu_kernel void @load_shl_base_lds_0(ptr addrspace(1) %out, ptr addrsp
; Make sure once the first use is folded into the addressing mode, the
; remaining add use goes through the normal shl + add constant fold.
-
-; GCN-LABEL: {{^}}load_shl_base_lds_1:
-; GCN: v_lshlrev_b32_e32 [[OFS:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_read_b32 [[RESULT:v[0-9]+]], [[OFS]] offset:8
-; GCN: v_add_{{[iu]}}32_e32 [[ADDUSE:v[0-9]+]], vcc, 8, v{{[0-9]+}}
-; GCN-DAG: buffer_store_dword [[RESULT]]
-; GCN-DAG: buffer_store_dword [[ADDUSE]]
-; GCN: s_endpgm
define amdgpu_kernel void @load_shl_base_lds_1(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: load_shl_base_lds_1:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_read_b32 v1, v0 offset:8
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 8, v0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: load_shl_base_lds_1:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: ds_read_b32 v1, v0 offset:8
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 8, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
@@ -52,10 +117,38 @@ define amdgpu_kernel void @load_shl_base_lds_1(ptr addrspace(1) %out, ptr addrsp
@maxlds = addrspace(3) global [65536 x i8] poison, align 4
-; GCN-LABEL: {{^}}load_shl_base_lds_max_offset
-; GCN: ds_read_u8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535
-; GCN: s_endpgm
define amdgpu_kernel void @load_shl_base_lds_max_offset(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: load_shl_base_lds_max_offset:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; CI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_read_u8 v1, v0 offset:65535
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s6, s2
+; CI-NEXT: s_mov_b32 s7, s3
+; CI-NEXT: v_add_i32_e32 v0, vcc, 0xffff, v0
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; CI-NEXT: buffer_store_byte v1, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: load_shl_base_lds_max_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: ds_read_u8 v1, v0 offset:65535
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_mov_b32 s6, s2
+; VI-NEXT: s_mov_b32 s7, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0xffff, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 65535
%arrayidx0 = getelementptr inbounds [65536 x i8], ptr addrspace(3) @maxlds, i32 0, i32 %idx.0
@@ -67,13 +160,32 @@ define amdgpu_kernel void @load_shl_base_lds_max_offset(ptr addrspace(1) %out, p
; The two globals are placed adjacent in memory, so the same base
; pointer can be used with an offset into the second one.
-
-; GCN-LABEL: {{^}}load_shl_base_lds_2:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: s_mov_b32 m0, -1
-; GCN: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9
-; GCN: s_endpgm
define amdgpu_kernel void @load_shl_base_lds_2(ptr addrspace(1) %out) #0 {
+; CI-LABEL: load_shl_base_lds_2:
+; CI: ; %bb.0:
+; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_read2st64_b32 v[0:1], v0 offset0:1 offset1:9
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_add_f32_e32 v0, v0, v1
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: load_shl_base_lds_2:
+; VI: ; %bb.0:
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: ds_read2st64_b32 v[0:1], v0 offset0:1 offset1:9
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_add_f32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 64
%arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
@@ -85,11 +197,34 @@ define amdgpu_kernel void @load_shl_base_lds_2(ptr addrspace(1) %out) #0 {
ret void
}
-; GCN-LABEL: {{^}}store_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @store_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: store_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xb
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: v_add_i32_e32 v1, vcc, 2, v0
+; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 1.0
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_write_b32 v0, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: store_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2c
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 2, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 1.0
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: ds_write_b32 v0, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x float], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
@@ -114,12 +249,54 @@ define amdgpu_kernel void @store_shl_base_lds_0(ptr addrspace(1) %out, ptr addrs
; ret void
; }
-
-; GCN-LABEL: {{^}}atomic_cmpxchg_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_cmpst_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_cmpxchg_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use, i32 %swap) #0 {
+; CI-LABEL: atomic_cmpxchg_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: s_load_dword s8, s[4:5], 0xd
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 7
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_mov_b32_e32 v3, s8
+; CI-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_cmpxchg_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: s_load_dword s8, s[4:5], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 7
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v3, s8
+; VI-NEXT: ds_cmpst_rtn_b32 v1, v1, v2, v3 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -130,11 +307,50 @@ define amdgpu_kernel void @atomic_cmpxchg_shl_base_lds_0(ptr addrspace(1) %out,
ret void
}
-; GCN-LABEL: {{^}}atomic_swap_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_wrxchg_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_swap_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_swap_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_wrxchg_rtn_b32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_swap_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_wrxchg_rtn_b32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -144,11 +360,50 @@ define amdgpu_kernel void @atomic_swap_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_add_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_add_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_add_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_add_rtn_u32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_add_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_add_rtn_u32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -158,11 +413,50 @@ define amdgpu_kernel void @atomic_add_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_sub_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_sub_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_sub_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_sub_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_sub_rtn_u32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_sub_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_sub_rtn_u32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -172,11 +466,50 @@ define amdgpu_kernel void @atomic_sub_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_and_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_and_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_and_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_and_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_and_rtn_b32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_and_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_and_rtn_b32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -186,11 +519,50 @@ define amdgpu_kernel void @atomic_and_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_or_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_or_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_or_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_or_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_or_rtn_b32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_or_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_or_rtn_b32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -200,11 +572,50 @@ define amdgpu_kernel void @atomic_or_shl_base_lds_0(ptr addrspace(1) %out, ptr a
ret void
}
-; GCN-LABEL: {{^}}atomic_xor_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_xor_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_xor_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_xor_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_xor_rtn_b32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_xor_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_xor_rtn_b32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -224,11 +635,50 @@ define amdgpu_kernel void @atomic_xor_shl_base_lds_0(ptr addrspace(1) %out, ptr
; ret void
; }
-; GCN-LABEL: {{^}}atomic_min_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_min_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_min_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_min_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_min_rtn_i32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_min_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_min_rtn_i32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -238,11 +688,50 @@ define amdgpu_kernel void @atomic_min_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_max_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_max_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_max_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_max_rtn_i32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_max_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_max_rtn_i32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -252,11 +741,50 @@ define amdgpu_kernel void @atomic_max_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_umin_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_min_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_umin_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_umin_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_min_rtn_u32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_umin_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_min_rtn_u32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -266,11 +794,50 @@ define amdgpu_kernel void @atomic_umin_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_umax_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_max_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_umax_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_umax_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 3
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_max_rtn_u32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_umax_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 3
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_max_rtn_u32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -280,11 +847,50 @@ define amdgpu_kernel void @atomic_umax_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_inc_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_inc_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_inc_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 31
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_inc_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 31
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_inc_rtn_u32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -294,11 +900,50 @@ define amdgpu_kernel void @atomic_inc_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0:
-; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
-; GCN: ds_dec_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8
-; GCN: s_endpgm
define amdgpu_kernel void @atomic_dec_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
+; CI-LABEL: atomic_dec_shl_base_lds_0:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; CI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 31
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: ds_dec_rtn_u32 v1, v1, v2 offset:8
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_mov_b32 s7, 0xf000
+; CI-NEXT: s_mov_b32 s6, -1
+; CI-NEXT: s_mov_b32 s4, s0
+; CI-NEXT: s_mov_b32 s5, s1
+; CI-NEXT: s_mov_b32 s0, s2
+; CI-NEXT: s_mov_b32 s1, s3
+; CI-NEXT: s_mov_b32 s2, s6
+; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: v_add_i32_e32 v0, vcc, 2, v0
+; CI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; CI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; CI-NEXT: s_endpgm
+;
+; VI-LABEL: atomic_dec_shl_base_lds_0:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; VI-NEXT: v_mov_b32_e32 v2, 31
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ds_dec_rtn_u32 v1, v1, v2 offset:8
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_mov_b32 s4, s0
+; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_mov_b32 s0, s2
+; VI-NEXT: s_mov_b32 s1, s3
+; VI-NEXT: s_mov_b32 s2, s6
+; VI-NEXT: s_mov_b32 s3, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, 2, v0
+; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds2, i32 0, i32 %idx.0
@@ -308,12 +953,19 @@ define amdgpu_kernel void @atomic_dec_shl_base_lds_0(ptr addrspace(1) %out, ptr
ret void
}
-; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_lds:
-; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0
-; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0
-; GCN: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:32
-; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+}} offset:64
define void @shl_add_ptr_combine_2use_lds(i32 %idx) #0 {
+; GCN-LABEL: shl_add_ptr_combine_2use_lds:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0
+; GCN-NEXT: v_mov_b32_e32 v2, 9
+; GCN-NEXT: s_mov_b32 m0, -1
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GCN-NEXT: ds_write_b32 v1, v2 offset:32
+; GCN-NEXT: v_mov_b32_e32 v1, 10
+; GCN-NEXT: ds_write_b32 v0, v1 offset:64
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
%idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4
@@ -324,13 +976,34 @@ define void @shl_add_ptr_combine_2use_lds(i32 %idx) #0 {
ret void
}
-; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_max_lds_offset:
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0
-; GCN-DAG: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:65528
-; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD1:v[0-9]+]], vcc, 0x1fff0, [[SCALE1]]
-; GCN: ds_write_b32 [[ADD1]], v{{[0-9]+$}}
define void @shl_add_ptr_combine_2use_max_lds_offset(i32 %idx) #0 {
+; CI-LABEL: shl_add_ptr_combine_2use_max_lds_offset:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; CI-NEXT: v_mov_b32_e32 v2, 9
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: v_add_i32_e32 v1, vcc, 0x1fff0, v1
+; CI-NEXT: ds_write_b32 v0, v2 offset:65528
+; CI-NEXT: v_mov_b32_e32 v0, 10
+; CI-NEXT: ds_write_b32 v1, v0
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: shl_add_ptr_combine_2use_max_lds_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; VI-NEXT: v_mov_b32_e32 v2, 9
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x1fff0, v1
+; VI-NEXT: ds_write_b32 v0, v2 offset:65528
+; VI-NEXT: v_mov_b32_e32 v0, 10
+; VI-NEXT: ds_write_b32 v1, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
%idx.add = add nuw i32 %idx, 8191
%shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4
@@ -341,13 +1014,34 @@ define void @shl_add_ptr_combine_2use_max_lds_offset(i32 %idx) #0 {
ret void
}
-; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_both_max_lds_offset:
-; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x1000, v0
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 4, [[ADD]]
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 5, [[ADD]]
-; GCN-DAG: ds_write_b32 [[SCALE0]], v{{[0-9]+$}}
-; GCN: ds_write_b32 [[SCALE1]], v{{[0-9]+$}}
define void @shl_add_ptr_combine_2use_both_max_lds_offset(i32 %idx) #0 {
+; CI-LABEL: shl_add_ptr_combine_2use_both_max_lds_offset:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_add_i32_e32 v0, vcc, 0x1000, v0
+; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; CI-NEXT: v_mov_b32_e32 v2, 9
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; CI-NEXT: ds_write_b32 v1, v2
+; CI-NEXT: v_mov_b32_e32 v1, 10
+; CI-NEXT: ds_write_b32 v0, v1
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: shl_add_ptr_combine_2use_both_max_lds_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x1000, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; VI-NEXT: v_mov_b32_e32 v2, 9
+; VI-NEXT: s_mov_b32 m0, -1
+; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-NEXT: ds_write_b32 v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, 10
+; VI-NEXT: ds_write_b32 v0, v1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
%idx.add = add nuw i32 %idx, 4096
%shl0 = shl i32 %idx.add, 4
%shl1 = shl i32 %idx.add, 5
@@ -358,12 +1052,19 @@ define void @shl_add_ptr_combine_2use_both_max_lds_offset(i32 %idx) #0 {
ret void
}
-; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_private:
-; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 2, v0
-; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 3, v0
-; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], 0 offen offset:16
-; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], 0 offen offset:32
define void @shl_add_ptr_combine_2use_private(i16 zeroext %idx.arg) #0 {
+; GCN-LABEL: shl_add_ptr_combine_2use_private:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0
+; GCN-NEXT: v_mov_b32_e32 v2, 9
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; GCN-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen offset:16
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v1, 10
+; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
+; GCN-NEXT: s_waitcnt vmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
%idx = zext i16 %idx.arg to i32
%idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 2
@@ -375,13 +1076,34 @@ define void @shl_add_ptr_combine_2use_private(i16 zeroext %idx.arg) #0 {
ret void
}
-; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_max_private_offset:
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0
-; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], 0 offen offset:4088
-; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x1ff0, [[SCALE1]]
-; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[0:3], 0 offen{{$}}
define void @shl_add_ptr_combine_2use_max_private_offset(i16 zeroext %idx.arg) #0 {
+; CI-LABEL: shl_add_ptr_combine_2use_max_private_offset:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; CI-NEXT: v_mov_b32_e32 v2, 9
+; CI-NEXT: v_add_i32_e32 v1, vcc, 0x1ff0, v1
+; CI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4088
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_mov_b32_e32 v0, 10
+; CI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: shl_add_ptr_combine_2use_max_private_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; VI-NEXT: v_mov_b32_e32 v2, 9
+; VI-NEXT: v_add_u32_e32 v1, vcc, 0x1ff0, v1
+; VI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4088
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, 10
+; VI-NEXT: buffer_store_dword v0, v1, s[0:3], 0 offen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
%idx = zext i16 %idx.arg to i32
%idx.add = add nuw i32 %idx, 511
%shl0 = shl i32 %idx.add, 3
@@ -392,13 +1114,35 @@ define void @shl_add_ptr_combine_2use_max_private_offset(i16 zeroext %idx.arg) #
store volatile i32 10, ptr addrspace(5) %ptr1
ret void
}
-; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_both_max_private_offset:
-; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x100, v0
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 4, [[ADD]]
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 5, [[ADD]]
-; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], 0 offen{{$}}
-; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], 0 offen{{$}}
+
define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.arg) #0 {
+; CI-LABEL: shl_add_ptr_combine_2use_both_max_private_offset:
+; CI: ; %bb.0:
+; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CI-NEXT: v_add_i32_e32 v0, vcc, 0x100, v0
+; CI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; CI-NEXT: v_mov_b32_e32 v2, 9
+; CI-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; CI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_mov_b32_e32 v1, 10
+; CI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: shl_add_ptr_combine_2use_both_max_private_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_add_u32_e32 v0, vcc, 0x100, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 4, v0
+; VI-NEXT: v_mov_b32_e32 v2, 9
+; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, 10
+; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
%idx = zext i16 %idx.arg to i32
%idx.add = add nuw i32 %idx, 256
%shl0 = shl i32 %idx.add, 4
@@ -410,10 +1154,20 @@ define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.a
ret void
}
-; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_lds:
-; GCN-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8
-; GCN-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
define void @shl_or_ptr_combine_2use_lds(i32 %idx) #0 {
+; GCN-LABEL: shl_or_ptr_combine_2use_lds:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 1, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GCN-NEXT: v_mov_b32_e32 v2, 9
+; GCN-NEXT: s_mov_b32 m0, -1
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v1
+; GCN-NEXT: ds_write_b32 v0, v2 offset:8
+; GCN-NEXT: v_mov_b32_e32 v0, 10
+; GCN-NEXT: ds_write_b32 v1, v0 offset:16
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
%idx.shl = shl i32 %idx, 1
%idx.add = or i32 %idx.shl, 1
%shl0 = shl i32 %idx.add, 3
@@ -424,13 +1178,21 @@ define void @shl_or_ptr_combine_2use_lds(i32 %idx) #0 {
store volatile i32 10, ptr addrspace(3) %ptr1
ret void
}
-; GCN-LABEL: {{^}}shl_or_ptr_not_combine_2use_lds:
-; GCN: v_or_b32_e32 [[OR:v[0-9]+]], 1, v0
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, [[OR]]
-; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, [[OR]]
-; GCN-DAG: ds_write_b32 [[SCALE0]], v{{[0-9]+}}{{$}}
-; GCN-DAG: ds_write_b32 [[SCALE1]], v{{[0-9]+}}{{$}}
+
define void @shl_or_ptr_not_combine_2use_lds(i32 %idx) #0 {
+; GCN-LABEL: shl_or_ptr_not_combine_2use_lds:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_or_b32_e32 v0, 1, v0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v0
+; GCN-NEXT: v_mov_b32_e32 v2, 9
+; GCN-NEXT: s_mov_b32 m0, -1
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GCN-NEXT: ds_write_b32 v1, v2
+; GCN-NEXT: v_mov_b32_e32 v1, 10
+; GCN-NEXT: ds_write_b32 v0, v1
+; GCN-NEXT: s_waitcnt lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
%idx.add = or i32 %idx, 1
%shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4
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