[llvm] [SelectionDAG] isADDLike should also include XORs that have no common bits set. (PR #147639)

[Craig Topper via llvm-commits]

topperc wrote:

Was it not already enough that we turn Xor into Or in DAGCombine. From visitXor:

```
  // fold (a^b) -> (a|b) iff a and b share no bits.                              
  if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&                 
      DAG.haveNoCommonBitsSet(N0, N1))                                           
    return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
```

https://github.com/llvm/llvm-project/pull/147639