[llvm] [SelectionDAG] isADDLike should also include XORs that have no common bits set. (PR #147639)

[via llvm-commits]

https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/147639

A disjoint or is also a disjoint xor, because (x | y) - (x & y) = x ^ y, and a disjoint or by definition has (x & y) as 0.

>From 1bee0f79048753f3022e29f96d3600f0cf6199a4 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Tue, 8 Jul 2025 22:38:29 -0400
Subject: [PATCH] [SelectionDAG] isADDLike should also include XORs that have
 no common bits set

A disjoint or is also a disjoint xor, because (x | y) - (x & y) = x ^ y, and a disjoint or by definition has (x & y) as 0.
---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c1356239ad206..ee9c55e3548a0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5677,7 +5677,8 @@ bool SelectionDAG::isADDLike(SDValue Op, bool NoWrap) const {
     return Op->getFlags().hasDisjoint() ||
            haveNoCommonBitsSet(Op.getOperand(0), Op.getOperand(1));
   if (Opcode == ISD::XOR)
-    return !NoWrap && isMinSignedConstant(Op.getOperand(1));
+    return !NoWrap && isMinSignedConstant(Op.getOperand(1)) || 
+           haveNoCommonBitsSet(Op.getOperand(0), Op.getOperand(1));
   return false;
 }