[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (PR #146675)

[Sam Elliott via llvm-commits]

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@@ -1461,6 +1485,33 @@ def : QCIMVCCIPat <SETLT,  QC_MVLTI>;
 def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
 }
 
+let Predicates = [HasVendorXqcics, IsRV32] in {
+def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
+          (QC_SELECTEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs3, GPRNoX0:$rs2)>;
+
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lenary wrote:

They would likely help, yes.

> Unfortunately, qc.selectiine can't have a rs1=x0 so you can't write a pattern for true and false both being immediates, but no setcc present.

But this is "fine" right, in that selection will end up putting one immediate into a register, and keeping the other as an immediate - rather than failing.

https://github.com/llvm/llvm-project/pull/146675