[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (PR #146675)

[Sam Elliott via llvm-commits]

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@@ -122,6 +136,13 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
 ; RV32-XQCICM-NEXT:    mv a0, a3
 ; RV32-XQCICM-NEXT:    ret
 ;
+; RV32-XQCICS-LABEL: select_i32_eq:
+; RV32-XQCICS:       # %bb.0:
+; RV32-XQCICS-NEXT:    xor a0, a0, a1
+; RV32-XQCICS-NEXT:    seqz a0, a0
+; RV32-XQCICS-NEXT:    qc.selecteqi a0, 0, a3, a2
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lenary wrote:

I think we come back to this in a follow-up.

https://github.com/llvm/llvm-project/pull/146675