[llvm] [RISCV] Use QC.INSBI for OR with immediate when ORI isn't possible (PR #147349)
Sudharsan Veeravalli via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 7 22:00:45 PDT 2025
================
@@ -681,6 +681,43 @@ bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
return false;
}
+bool RISCVDAGToDAGISel::trySignedBitfieldInsertInMask(SDNode *Node) {
+ // Supported only in Xqcibm for now.
+ if (!Subtarget->hasVendorXqcibm())
+ return false;
+
+ auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
+ if (!N1C)
+ return false;
+
+ int32_t C1 = N1C->getSExtValue();
+ if (!(isShiftedMask_32(C1) && !isInt<12>(C1)))
+ return false;
+
+ // If C1 is a shifted mask (but can't be formed as an ORI),
+ // use a bitfield insert of -1.
+ // Transform (or x, C1)
+ // -> (qc.insbi x, width, shift)
+ const unsigned Leading = llvm::countl_zero((uint32_t)C1);
+ const unsigned Trailing = llvm::countr_zero((uint32_t)C1);
+ const unsigned Width = 32 - Leading - Trailing;
+
+ // If Zbs is enabled and it is a single bit set we can use BSETI which
+ // can be compressed to C_BSETI when Xqcibm in enabled.
+ if (Width == 1 && Subtarget->hasStdExtZbs())
+ return false;
+
+ SDLoc DL(Node);
+ MVT VT = Node->getSimpleValueType(0);
+
+ SmallVector<SDValue, 4> Ops = {CurDAG->getSignedTargetConstant(-1, DL, VT),
----------------
svs-quic wrote:
Done.
https://github.com/llvm/llvm-project/pull/147349
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