[llvm] 56cf2cb - HexagonMCCodeEmitter: Set PCRel at fixup creation
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 17:49:00 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T17:48:55-07:00
New Revision: 56cf2cb0eadd6916b3f45b6504905ab8821ee4e8
URL: https://github.com/llvm/llvm-project/commit/56cf2cb0eadd6916b3f45b6504905ab8821ee4e8
DIFF: https://github.com/llvm/llvm-project/commit/56cf2cb0eadd6916b3f45b6504905ab8821ee4e8.diff
LOG: HexagonMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.
Added:
Modified:
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index 1c31257a9e2ac..0dbc05690d479 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -84,14 +84,15 @@ class HexagonAsmBackend : public MCAsmBackend {
}
MCFixupKindInfo getFixupKindInfo(MCFixupKind Kind) const override {
+ // clang-format off
const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
// This table *must* be in same the order of fixup_* kinds in
// HexagonFixupKinds.h.
//
// namei offset bits flags
- { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B22_PCREL", 0, 32, 0 },
+ { "fixup_Hexagon_B15_PCREL", 0, 32, 0 },
+ { "fixup_Hexagon_B7_PCREL", 0, 32, 0 },
{ "fixup_Hexagon_LO16", 0, 32, 0 },
{ "fixup_Hexagon_HI16", 0, 32, 0 },
{ "fixup_Hexagon_32", 0, 32, 0 },
@@ -102,15 +103,15 @@ class HexagonAsmBackend : public MCAsmBackend {
{ "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
{ "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
{ "fixup_Hexagon_HL16", 0, 32, 0 },
- { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B13_PCREL", 0, 32, 0 },
+ { "fixup_Hexagon_B9_PCREL", 0, 32, 0 },
+ { "fixup_Hexagon_B32_PCREL_X", 0, 32, 0 },
{ "fixup_Hexagon_32_6_X", 0, 32, 0 },
- { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_B22_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_B15_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_B13_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_B9_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_B7_PCREL_X", 0, 32, 0 },
{ "fixup_Hexagon_16_X", 0, 32, 0 },
{ "fixup_Hexagon_12_X", 0, 32, 0 },
{ "fixup_Hexagon_11_X", 0, 32, 0 },
@@ -119,12 +120,12 @@ class HexagonAsmBackend : public MCAsmBackend {
{ "fixup_Hexagon_8_X", 0, 32, 0 },
{ "fixup_Hexagon_7_X", 0, 32, 0 },
{ "fixup_Hexagon_6_X", 0, 32, 0 },
- { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_32_PCREL", 0, 32, 0 },
{ "fixup_Hexagon_COPY", 0, 32, 0 },
{ "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
{ "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
{ "fixup_Hexagon_RELATIVE", 0, 32, 0 },
- { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, 0 },
{ "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
{ "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
{ "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
@@ -137,8 +138,8 @@ class HexagonAsmBackend : public MCAsmBackend {
{ "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
{ "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
{ "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
- { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, 0 },
+ { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, 0 },
{ "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
{ "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
{ "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
@@ -159,7 +160,7 @@ class HexagonAsmBackend : public MCAsmBackend {
{ "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
{ "fixup_Hexagon_TPREL_32", 0, 32, 0 },
{ "fixup_Hexagon_TPREL_16", 0, 32, 0 },
- { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Hexagon_6_PCREL_X", 0, 32, 0 },
{ "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
{ "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
{ "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
@@ -183,11 +184,12 @@ class HexagonAsmBackend : public MCAsmBackend {
{ "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
{ "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
{ "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
- { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
+ { "fixup_Hexagon_GD_PLT_B22_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_GD_PLT_B32_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_LD_PLT_B22_PCREL_X", 0, 32, 0 },
+ { "fixup_Hexagon_LD_PLT_B32_PCREL_X", 0, 32, 0 },
};
+ // clang-format on
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 8490e74b4d959..dfe0fa973c9b3 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -337,6 +337,35 @@ static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
#undef P
#undef _
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+ const MCExpr *Value, uint16_t Kind) {
+ bool PCRel = false;
+ switch (Kind) {
+ case Hexagon::fixup_Hexagon_B22_PCREL:
+ case Hexagon::fixup_Hexagon_B15_PCREL:
+ case Hexagon::fixup_Hexagon_B7_PCREL:
+ case Hexagon::fixup_Hexagon_B13_PCREL:
+ case Hexagon::fixup_Hexagon_B9_PCREL:
+ case Hexagon::fixup_Hexagon_B32_PCREL_X:
+ case Hexagon::fixup_Hexagon_B22_PCREL_X:
+ case Hexagon::fixup_Hexagon_B15_PCREL_X:
+ case Hexagon::fixup_Hexagon_B13_PCREL_X:
+ case Hexagon::fixup_Hexagon_B9_PCREL_X:
+ case Hexagon::fixup_Hexagon_B7_PCREL_X:
+ case Hexagon::fixup_Hexagon_32_PCREL:
+ case Hexagon::fixup_Hexagon_PLT_B22_PCREL:
+ case Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL:
+ case Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL:
+ case Hexagon::fixup_Hexagon_6_PCREL_X:
+ case Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X:
+ case Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X:
+ case Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X:
+ case Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X:
+ PCRel = true;
+ }
+ Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
MCInst const &MCI) const {
bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
@@ -698,10 +727,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
}
- MCFixup Fixup =
- MCFixup::create(State.Addend, FixupExpr, MCFixupKind(FixupKind));
- Fixups.push_back(Fixup);
- // All of the information is in the fixup.
+ addFixup(Fixups, State.Addend, FixupExpr, FixupKind);
return 0;
}
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