[llvm] def731a - MipsMCCodeEmitter: Set PCRel at fixup creation
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 4 17:44:08 PDT 2025
Author: Fangrui Song
Date: 2025-07-04T17:44:03-07:00
New Revision: def731a787daa9f5d4146552fb64c17cb248bd69
URL: https://github.com/llvm/llvm-project/commit/def731a787daa9f5d4146552fb64c17cb248bd69
DIFF: https://github.com/llvm/llvm-project/commit/def731a787daa9f5d4146552fb64c17cb248bd69.diff
LOG: MipsMCCodeEmitter: Set PCRel at fixup creation
Avoid reliance on the MCAssembler::evaluateFixup workaround that checks
MCFixupKindInfo::FKF_IsPCRel. Additionally, standardize how fixups are
appended. This helper will facilitate future fixup data structure
optimizations.
Added:
Modified:
llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
index dad4e705a8d45..7b0231c95d6af 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
@@ -418,7 +418,7 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_GPREL16", 0, 16, 0 },
{ "fixup_Mips_LITERAL", 0, 16, 0 },
{ "fixup_Mips_GOT", 0, 16, 0 },
- { "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Mips_PC16", 0, 16, 0 },
{ "fixup_Mips_CALL16", 0, 16, 0 },
{ "fixup_Mips_SHIFT5", 6, 5, 0 },
{ "fixup_Mips_SHIFT6", 6, 5, 0 },
@@ -430,7 +430,7 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_TLSLDM", 0, 16, 0 },
{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
- { "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Mips_Branch_PCRel", 0, 16, 0 },
{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
{ "fixup_MICROMIPS_GPOFF_HI",0, 16, 0 },
{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
@@ -446,23 +446,23 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
- { "fixup_Mips_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PC21_S2", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PC26_S2", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PCHI16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PCLO16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Mips_PC18_S3", 0, 18, 0 },
+ { "fixup_MIPS_PC19_S2", 0, 19, 0 },
+ { "fixup_MIPS_PC21_S2", 0, 21, 0 },
+ { "fixup_MIPS_PC26_S2", 0, 26, 0 },
+ { "fixup_MIPS_PCHI16", 0, 16, 0 },
+ { "fixup_MIPS_PCLO16", 0, 16, 0 },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
- { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC26_S1", 0, 26, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC19_S2", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC18_S3", 0, 18, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC21_S1", 0, 21, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_MICROMIPS_PC7_S1", 0, 7, 0 },
+ { "fixup_MICROMIPS_PC10_S1", 0, 10, 0 },
+ { "fixup_MICROMIPS_PC16_S1", 0, 16, 0 },
+ { "fixup_MICROMIPS_PC26_S1", 0, 26, 0 },
+ { "fixup_MICROMIPS_PC19_S2", 0, 19, 0 },
+ { "fixup_MICROMIPS_PC18_S3", 0, 18, 0 },
+ { "fixup_MICROMIPS_PC21_S1", 0, 21, 0 },
{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
@@ -504,7 +504,7 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_GPREL16", 16, 16, 0 },
{ "fixup_Mips_LITERAL", 16, 16, 0 },
{ "fixup_Mips_GOT", 16, 16, 0 },
- { "fixup_Mips_PC16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Mips_PC16", 16, 16, 0 },
{ "fixup_Mips_CALL16", 16, 16, 0 },
{ "fixup_Mips_SHIFT5", 21, 5, 0 },
{ "fixup_Mips_SHIFT6", 21, 5, 0 },
@@ -516,11 +516,11 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_TLSLDM", 16, 16, 0 },
{ "fixup_Mips_DTPREL_HI", 16, 16, 0 },
{ "fixup_Mips_DTPREL_LO", 16, 16, 0 },
- { "fixup_Mips_Branch_PCRel",16, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Mips_Branch_PCRel",16, 16, 0 },
{ "fixup_Mips_GPOFF_HI", 16, 16, 0 },
- { "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 },
+ { "fixup_MICROMIPS_GPOFF_HI", 16, 16, 0 },
{ "fixup_Mips_GPOFF_LO", 16, 16, 0 },
- { "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 },
+ { "fixup_MICROMIPS_GPOFF_LO", 16, 16, 0 },
{ "fixup_Mips_GOT_PAGE", 16, 16, 0 },
{ "fixup_Mips_GOT_OFST", 16, 16, 0 },
{ "fixup_Mips_GOT_DISP", 16, 16, 0 },
@@ -532,23 +532,23 @@ MCFixupKindInfo MipsAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
{ "fixup_Mips_GOT_LO16", 16, 16, 0 },
{ "fixup_Mips_CALL_HI16", 16, 16, 0 },
{ "fixup_Mips_CALL_LO16", 16, 16, 0 },
- { "fixup_Mips_PC18_S3", 14, 18, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PC19_S2", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PC21_S2", 11, 21, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PC26_S2", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PCHI16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MIPS_PCLO16", 16, 16, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_Mips_PC18_S3", 14, 18, 0 },
+ { "fixup_MIPS_PC19_S2", 13, 19, 0 },
+ { "fixup_MIPS_PC21_S2", 11, 21, 0 },
+ { "fixup_MIPS_PC26_S2", 6, 26, 0 },
+ { "fixup_MIPS_PCHI16", 16, 16, 0 },
+ { "fixup_MIPS_PCLO16", 16, 16, 0 },
{ "fixup_MICROMIPS_26_S1", 6, 26, 0 },
{ "fixup_MICROMIPS_HI16", 16, 16, 0 },
{ "fixup_MICROMIPS_LO16", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT16", 16, 16, 0 },
- { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC26_S1", 6, 26, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC19_S2",13, 19, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC18_S3",14, 18, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_MICROMIPS_PC21_S1",11, 21, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_MICROMIPS_PC7_S1", 9, 7, 0 },
+ { "fixup_MICROMIPS_PC10_S1", 6, 10, 0 },
+ { "fixup_MICROMIPS_PC16_S1",16, 16, 0 },
+ { "fixup_MICROMIPS_PC26_S1", 6, 26, 0 },
+ { "fixup_MICROMIPS_PC19_S2",13, 19, 0 },
+ { "fixup_MICROMIPS_PC18_S3",14, 18, 0 },
+ { "fixup_MICROMIPS_PC21_S1",11, 21, 0 },
{ "fixup_MICROMIPS_CALL16", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 16, 16, 0 },
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
index 2fd2b16560d4d..2f2c3584d23c7 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -55,6 +55,30 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
} // end namespace llvm
+static void addFixup(SmallVectorImpl<MCFixup> &Fixups, uint32_t Offset,
+ const MCExpr *Value, uint16_t Kind) {
+ bool PCRel = false;
+ switch (Kind) {
+ case Mips::fixup_Mips_PC16:
+ case Mips::fixup_Mips_Branch_PCRel:
+ case Mips::fixup_MIPS_PC18_S3:
+ case Mips::fixup_MIPS_PC19_S2:
+ case Mips::fixup_MIPS_PC21_S2:
+ case Mips::fixup_MIPS_PC26_S2:
+ case Mips::fixup_MIPS_PCHI16:
+ case Mips::fixup_MIPS_PCLO16:
+ case Mips::fixup_MICROMIPS_PC7_S1:
+ case Mips::fixup_MICROMIPS_PC10_S1:
+ case Mips::fixup_MICROMIPS_PC16_S1:
+ case Mips::fixup_MICROMIPS_PC26_S1:
+ case Mips::fixup_MICROMIPS_PC19_S2:
+ case Mips::fixup_MICROMIPS_PC18_S3:
+ case Mips::fixup_MICROMIPS_PC21_S1:
+ PCRel = true;
+ }
+ Fixups.push_back(MCFixup::create(Offset, Value, Kind, PCRel));
+}
+
// If the D<shift> instruction has a shift amount that is greater
// than 31 (checked in calling routine), lower it to a D<shift>32 instruction
static void LowerLargeShift(MCInst& Inst) {
@@ -236,8 +260,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(MCFixup::create(0, FixupExpression,
- MCFixupKind(Mips::fixup_Mips_PC16)));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
return 0;
}
@@ -258,8 +281,7 @@ getBranchTargetOpValue1SImm16(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(MCFixup::create(0, FixupExpression,
- MCFixupKind(Mips::fixup_Mips_PC16)));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
return 0;
}
@@ -281,8 +303,7 @@ getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-2, Ctx), Ctx);
- Fixups.push_back(MCFixup::create(0, FixupExpression,
- MCFixupKind(Mips::fixup_Mips_PC16)));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
return 0;
}
@@ -304,8 +325,7 @@ getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(MCFixup::create(0, FixupExpression,
- MCFixupKind(Mips::fixup_Mips_PC16)));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_Mips_PC16);
return 0;
}
@@ -325,8 +345,7 @@ getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValueMM expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(0, Expr,
- MCFixupKind(Mips::fixup_MICROMIPS_PC7_S1)));
+ addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_PC7_S1);
return 0;
}
@@ -346,8 +365,7 @@ getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValuePC10 expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(0, Expr,
- MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1)));
+ addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_PC10_S1);
return 0;
}
@@ -367,7 +385,7 @@ getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo,
"getBranchTargetOpValueMM expects only expressions or immediates");
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(0, Expr, Mips::fixup_MICROMIPS_PC16_S1));
+ addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_PC16_S1);
return 0;
}
@@ -388,8 +406,7 @@ getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(
- MCFixup::create(0, FixupExpression, Mips::fixup_MIPS_PC21_S2));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_MIPS_PC21_S2);
return 0;
}
@@ -410,8 +427,7 @@ getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(
- MCFixup::create(0, FixupExpression, Mips::fixup_MICROMIPS_PC21_S1));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_MICROMIPS_PC21_S1);
return 0;
}
@@ -432,8 +448,7 @@ getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo,
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(
- MCFixup::create(0, FixupExpression, Mips::fixup_MIPS_PC26_S2));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_MIPS_PC26_S2);
return 0;
}
@@ -454,8 +469,7 @@ unsigned MipsMCCodeEmitter::getBranchTarget26OpValueMM(
const MCExpr *FixupExpression = MCBinaryExpr::createAdd(
MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx);
- Fixups.push_back(MCFixup::create(0, FixupExpression,
- MCFixupKind(Mips::fixup_MICROMIPS_PC26_S1)));
+ addFixup(Fixups, 0, FixupExpression, Mips::fixup_MICROMIPS_PC26_S1);
return 0;
}
@@ -476,7 +490,7 @@ getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo,
const MCExpr *Expr = MO.getExpr();
Mips::Fixups FixupKind =
isMicroMips(STI) ? Mips::fixup_MICROMIPS_LO16 : Mips::fixup_Mips_LO16;
- Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
+ addFixup(Fixups, 0, Expr, MCFixupKind(FixupKind));
return 0;
}
@@ -495,8 +509,7 @@ getJumpTargetOpValue(const MCInst &MI, unsigned OpNo,
"getJumpTargetOpValue expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(0, Expr,
- MCFixupKind(Mips::fixup_Mips_26)));
+ addFixup(Fixups, 0, Expr, Mips::fixup_Mips_26);
return 0;
}
@@ -512,8 +525,7 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo,
"getJumpTargetOpValueMM expects only expressions or an immediate");
const MCExpr *Expr = MO.getExpr();
- Fixups.push_back(MCFixup::create(0, Expr,
- MCFixupKind(Mips::fixup_MICROMIPS_26_S1)));
+ addFixup(Fixups, 0, Expr, Mips::fixup_MICROMIPS_26_S1);
return 0;
}
@@ -691,7 +703,7 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB;
break;
}
- Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind)));
+ addFixup(Fixups, 0, MipsExpr, MCFixupKind(FixupKind));
return 0;
}
@@ -732,8 +744,7 @@ unsigned MipsMCCodeEmitter::getImmOpValue(const MCInst &MI, const MCOperand &MO,
return Res;
unsigned MIFrm = MipsII::getFormat(MCII.get(MI.getOpcode()).TSFlags);
if (!isa<MCSpecifierExpr>(Expr) && MIFrm == MipsII::FrmI) {
- Fixups.push_back(
- MCFixup::create(0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16)));
+ addFixup(Fixups, 0, Expr, MCFixupKind(Mips::fixup_Mips_AnyImm16));
return 0;
}
return getExprOpValue(Expr, Fixups, STI);
@@ -962,7 +973,7 @@ MipsMCCodeEmitter::getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo,
const MCExpr *Expr = MO.getExpr();
Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC19_S2
: Mips::fixup_MIPS_PC19_S2;
- Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
+ addFixup(Fixups, 0, Expr, MCFixupKind(FixupKind));
return 0;
}
@@ -984,7 +995,7 @@ MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo,
const MCExpr *Expr = MO.getExpr();
Mips::Fixups FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_PC18_S3
: Mips::fixup_MIPS_PC18_S3;
- Fixups.push_back(MCFixup::create(0, Expr, MCFixupKind(FixupKind)));
+ addFixup(Fixups, 0, Expr, MCFixupKind(FixupKind));
return 0;
}
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