[llvm] [DAG] combineVSelectWithAllOnesOrZeros - convert "select(setgt lhs, -1), 1, -1" match to SDPatternMatch. NFC. (PR #146842)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-selectiondag

Author: Simon Pilgrim (RKSimon)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/146842.diff


1 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+3-9) 


``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 586eb2f3cf45e..72b6f268a079d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13097,16 +13097,10 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
   }
 
   // check select(setgt lhs, -1), 1, -1 --> or (sra lhs, bitwidth - 1), 1
-  APInt TValAPInt;
-  if (Cond.getOpcode() == ISD::SETCC &&
-      Cond.getOperand(2) == DAG.getCondCode(ISD::SETGT) &&
-      Cond.getOperand(0).getValueType() == VT && VT.isSimple() &&
-      ISD::isConstantSplatVector(TVal.getNode(), TValAPInt) &&
-      TValAPInt.isOne() &&
-      ISD::isConstantSplatVectorAllOnes(Cond.getOperand(1).getNode()) &&
-      ISD::isConstantSplatVectorAllOnes(FVal.getNode())) {
+  if (sd_match(TVal, m_One()) && sd_match(FVal, m_AllOnes()) &&
+      sd_match(Cond, m_SetCC(m_SpecificVT(VT), m_AllOnes(),
+                             m_SpecificCondCode(ISD::SETGT))))
     return SDValue();
-  }
 
   // To use the condition operand as a bitwise mask, it must have elements that
   // are the same size as the select elements. i.e, the condition operand must

``````````

</details>


https://github.com/llvm/llvm-project/pull/146842