[llvm] [DAG] combineVSelectWithAllOnesOrZeros - convert "select(setgt lhs, -1), 1, -1" match to SDPatternMatch. NFC. (PR #146842)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/146842

None

>From d7528e1fc04d674422c8a76c4ca845e533d43229 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Thu, 3 Jul 2025 11:05:38 +0100
Subject: [PATCH] [DAG] combineVSelectWithAllOnesOrZeros - convert
 "select(setgt lhs, -1), 1, -1" match to SDPatternMatch. NFC.

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 586eb2f3cf45e..72b6f268a079d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13097,16 +13097,10 @@ static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
   }
 
   // check select(setgt lhs, -1), 1, -1 --> or (sra lhs, bitwidth - 1), 1
-  APInt TValAPInt;
-  if (Cond.getOpcode() == ISD::SETCC &&
-      Cond.getOperand(2) == DAG.getCondCode(ISD::SETGT) &&
-      Cond.getOperand(0).getValueType() == VT && VT.isSimple() &&
-      ISD::isConstantSplatVector(TVal.getNode(), TValAPInt) &&
-      TValAPInt.isOne() &&
-      ISD::isConstantSplatVectorAllOnes(Cond.getOperand(1).getNode()) &&
-      ISD::isConstantSplatVectorAllOnes(FVal.getNode())) {
+  if (sd_match(TVal, m_One()) && sd_match(FVal, m_AllOnes()) &&
+      sd_match(Cond, m_SetCC(m_SpecificVT(VT), m_AllOnes(),
+                             m_SpecificCondCode(ISD::SETGT))))
     return SDValue();
-  }
 
   // To use the condition operand as a bitwise mask, it must have elements that
   // are the same size as the select elements. i.e, the condition operand must