[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (PR #146675)

[Sam Elliott via llvm-commits]

================
@@ -122,6 +136,13 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
 ; RV32-XQCICM-NEXT:    mv a0, a3
 ; RV32-XQCICM-NEXT:    ret
 ;
+; RV32-XQCICS-LABEL: select_i32_eq:
+; RV32-XQCICS:       # %bb.0:
+; RV32-XQCICS-NEXT:    xor a0, a0, a1
+; RV32-XQCICS-NEXT:    seqz a0, a0
+; RV32-XQCICS-NEXT:    qc.selecteqi a0, 0, a3, a2
----------------
lenary wrote:

This sequence is:
- xoring a0 and a1, 
- setting a0 to `1` if the the xor result is zero, or to `0` if it is non-zero (an invert)
- then checking whether the value in `a0` is 0 or not

I think this could be done with just the xor and a `qc.selectnei`. The same sort-of applies to `select_i32_ne`, below.

This makes me wonder if we should be using `riscv_seteq` and `riscv_setne` - the reason we didn't for `qc.mv<cc>` was because we had other comparisons to cover, but with `qc.select*` the only comparisons are eq/ne. 

I'm not 100% sure what the right thing to do here is (because the `riscv_seteq/ne` don't quite seem to match with the patterns in this PR), so maybe the current implementation maybe good enough for the moment, and we can come back in the future to see if `riscv_seteq/ne` are helpful.

https://github.com/llvm/llvm-project/pull/146675