[llvm] [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (PR #146675)

[Sam Elliott via llvm-commits]

================
@@ -1461,6 +1485,31 @@ def : QCIMVCCIPat <SETLT,  QC_MVLTI>;
 def : QCIMVCCIPat <SETULT, QC_MVLTUI>;
 }
 
+let Predicates = [HasVendorXqcics, IsRV32] in {
+def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
+          (QC_SELECTEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs3, GPRNoX0:$rs2)>;
+
+let AddedComplexity = 1 in {
----------------
lenary wrote:

Please add a comment as to why the `AddedComplexity` is needed.



https://github.com/llvm/llvm-project/pull/146675