[llvm] [ISel/RISCV] Custom-promote [b]f16 in [l]lrint (PR #146507)

[Craig Topper via llvm-commits]

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@@ -1456,6 +1457,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
             // available.
             setOperationAction(ISD::BUILD_VECTOR, MVT::f16, Custom);
           }
+          if (Subtarget.hasVInstructionsF16Minimal())
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topperc wrote:

hasVInstructionF16Minimal()==true is guaranteed by the `useRVVForFixedLengthVectorVT` earlier in the loop we're in here.

https://github.com/llvm/llvm-project/pull/146507