[llvm] [ISel/RISCV] Custom-promote [b]f16 in [l]lrint (PR #146507)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 1 12:19:20 PDT 2025
================
@@ -249,3 +249,351 @@ define <8 x iXLen> @lrint_v8f64(<8 x double> %x) {
ret <8 x iXLen> %a
}
declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f64(<8 x double>)
+
+define <1 x iXLen> @lrint_v1f16(<1 x half> %x) {
+; RV32-LABEL: lrint_v1f16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v1f16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v1f16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
+; RV64-i64-NEXT: ret
+ %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half> %x)
+ ret <1 x iXLen> %a
+}
+declare <1 x iXLen> @llvm.lrint.v1iXLen.v1f16(<1 x half>)
+
+define <2 x iXLen> @lrint_v2f16(<2 x half> %x) {
+; RV32-LABEL: lrint_v2f16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v2f16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v2f16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV64-i64-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
+; RV64-i64-NEXT: ret
+ %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half> %x)
+ ret <2 x iXLen> %a
+}
+declare <2 x iXLen> @llvm.lrint.v2iXLen.v2f16(<2 x half>)
+
+define <3 x iXLen> @lrint_v3f16(<3 x half> %x) {
+; RV32-LABEL: lrint_v3f16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v3f16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v3f16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
+; RV64-i64-NEXT: ret
+ %a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3f16(<3 x half> %x)
+ ret <3 x iXLen> %a
+}
+declare <3 x iXLen> @llvm.lrint.v3iXLen.v3f16(<3 x half>)
+
+define <4 x iXLen> @lrint_v4f16(<4 x half> %x) {
+; RV32-LABEL: lrint_v4f16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32-NEXT: vfwcvt.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v4f16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i32-NEXT: vfwcvt.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v4f16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.f.f.v v10, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
+; RV64-i64-NEXT: ret
+ %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half> %x)
+ ret <4 x iXLen> %a
+}
+declare <4 x iXLen> @llvm.lrint.v4iXLen.v4f16(<4 x half>)
+
+define <8 x iXLen> @lrint_v8f16(<8 x half> %x) {
+; RV32-LABEL: lrint_v8f16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT: vfwcvt.f.f.v v10, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v8f16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64-i32-NEXT: vfwcvt.f.f.v v10, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v10
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v8f16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64-i64-NEXT: vfwcvt.f.f.v v12, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
+; RV64-i64-NEXT: ret
+ %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half> %x)
+ ret <8 x iXLen> %a
+}
+declare <8 x iXLen> @llvm.lrint.v8iXLen.v8f16(<8 x half>)
+
+define <16 x iXLen> @lrint_v16f16(<16 x half> %x) {
+; RV32-LABEL: lrint_v16f16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV32-NEXT: vfwcvt.f.f.v v12, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v16f16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV64-i32-NEXT: vfwcvt.f.f.v v12, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v12
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v16f16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV64-i64-NEXT: vfwcvt.f.f.v v16, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
+; RV64-i64-NEXT: ret
+ %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half> %x)
+ ret <16 x iXLen> %a
+}
+declare <16 x iXLen> @llvm.lrint.v16iXLen.v16f16(<16 x half>)
+
+define <1 x iXLen> @lrint_v1bf16(<1 x bfloat> %x) {
+; RV32-LABEL: lrint_v1bf16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v1bf16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v1bf16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
+; RV64-i64-NEXT: ret
+ %a = call <1 x iXLen> @llvm.lrint.v1iXLen.v1bf16(<1 x bfloat> %x)
+ ret <1 x iXLen> %a
+}
+declare <1 x iXLen> @llvm.lrint.v1iXLen.v1bf16(<1 x bfloat>)
+
+define <2 x iXLen> @lrint_v2bf16(<2 x bfloat> %x) {
+; RV32-LABEL: lrint_v2bf16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v2bf16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v2bf16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; RV64-i64-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v9
+; RV64-i64-NEXT: ret
+ %a = call <2 x iXLen> @llvm.lrint.v2iXLen.v2bf16(<2 x bfloat> %x)
+ ret <2 x iXLen> %a
+}
+declare <2 x iXLen> @llvm.lrint.v2iXLen.v2bf16(<2 x bfloat>)
+
+define <3 x iXLen> @lrint_v3bf16(<3 x bfloat> %x) {
+; RV32-LABEL: lrint_v3bf16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v3bf16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v3bf16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
+; RV64-i64-NEXT: ret
+ %a = call <3 x iXLen> @llvm.lrint.v3iXLen.v3bf16(<3 x bfloat> %x)
+ ret <3 x iXLen> %a
+}
+declare <3 x iXLen> @llvm.lrint.v3iXLen.v3bf16(<3 x bfloat>)
+
+define <4 x iXLen> @lrint_v4bf16(<4 x bfloat> %x) {
+; RV32-LABEL: lrint_v4bf16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v9
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v4bf16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i32-NEXT: vfwcvtbf16.f.f.v v9, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v9
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v4bf16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; RV64-i64-NEXT: vfwcvtbf16.f.f.v v10, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v10
+; RV64-i64-NEXT: ret
+ %a = call <4 x iXLen> @llvm.lrint.v4iXLen.v4bf16(<4 x bfloat> %x)
+ ret <4 x iXLen> %a
+}
+declare <4 x iXLen> @llvm.lrint.v4iXLen.v4bf16(<4 x bfloat>)
+
+define <8 x iXLen> @lrint_v8bf16(<8 x bfloat> %x) {
+; RV32-LABEL: lrint_v8bf16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV32-NEXT: vfwcvtbf16.f.f.v v10, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v10
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v8bf16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64-i32-NEXT: vfwcvtbf16.f.f.v v10, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v10
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v8bf16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; RV64-i64-NEXT: vfwcvtbf16.f.f.v v12, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v12
+; RV64-i64-NEXT: ret
+ %a = call <8 x iXLen> @llvm.lrint.v8iXLen.v8bf16(<8 x bfloat> %x)
+ ret <8 x iXLen> %a
+}
+declare <8 x iXLen> @llvm.lrint.v8iXLen.v8bf16(<8 x bfloat>)
+
+define <16 x iXLen> @lrint_v16bf16(<16 x bfloat> %x) {
+; RV32-LABEL: lrint_v16bf16:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV32-NEXT: vfwcvtbf16.f.f.v v12, v8
+; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v12
+; RV32-NEXT: ret
+;
+; RV64-i32-LABEL: lrint_v16bf16:
+; RV64-i32: # %bb.0:
+; RV64-i32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV64-i32-NEXT: vfwcvtbf16.f.f.v v12, v8
+; RV64-i32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i32-NEXT: vfcvt.x.f.v v8, v12
+; RV64-i32-NEXT: ret
+;
+; RV64-i64-LABEL: lrint_v16bf16:
+; RV64-i64: # %bb.0:
+; RV64-i64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; RV64-i64-NEXT: vfwcvtbf16.f.f.v v16, v8
+; RV64-i64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; RV64-i64-NEXT: vfwcvt.x.f.v v8, v16
+; RV64-i64-NEXT: ret
+ %a = call <16 x iXLen> @llvm.lrint.v16iXLen.v16bf16(<16 x bfloat> %x)
+ ret <16 x iXLen> %a
+}
+declare <16 x iXLen> @llvm.lrint.v16iXLen.v16bf16(<16 x bfloat>)
----------------
topperc wrote:
Please add a test where the bf16 type uses lmul=8 so the promotion needs to split.
https://github.com/llvm/llvm-project/pull/146507
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