[llvm] [RISCV] Fix Compression with Symbols for Xqci (PR #146184)

[Sam Elliott via llvm-commits]

lenary wrote:

Honestly, I don't know if this is correct or not, but I'm posting the patch anyway.

I thought I had solved most of the issues in #142702, BUT then I was getting crashes in `RISCVMCCodeEmitter::getImmOpValue` (from the assert at the end) when trying to assemble `qc.e.li a0, undef` and similar instructions.

`MCOp.isBareSymbolRef()` might need to be accepted for the simm6 immediates when e.g. you have `.set foo, 10; c.li a0, foo`, but we have no tests like this. We do have tests for similar using `addi` or `li`, which fail if I take `MCOp.isBareSymbolRef()` out of the MCOperandPredicate in `simm12` - but usually `simm12` appears in instructions with a format that `RISCVMCCodeEmitter::getImmOpValue` can handle (i.e., `InstFormatI`). Note we have no fixups for `InstFormatCI`, as there are no public relocations that apply to a CI-type instruction.

The problem is that we use this MCOperandPredicate in two places:
- Checking whether an alias applies
- Checking whether we can compress an instruction
Arguably, these are two different uses, because an alias may cope with being printed with a symbol where we cannot emit a relocation to an object.

All that said, I want `qc.e.li a1, undef` not to crash when not in exact mode, which right now we're struggling with.

https://github.com/llvm/llvm-project/pull/146184