[llvm] [RISCV] Fix Compression with Symbols for Xqci (PR #146184)

Fri Jun 27 18:29:06 PDT 2025

llvmbot wrote:




@llvm/pr-subscribers-mc

Author: Sam Elliott (lenary)

<details>
<summary>Changes</summary>

This adds more tests for emitting Xqci instructions with symbols, to check the case where the instruction has a symbol but may get compressed. Some of these tests were causing crashes before.

This change then fixes the crashes, by changing the MCOperandPredicates, which are used for compression. This prevents compressing instructions with symbols when we have no way of applying the fixup to the compressed instruction, as is the case for CI-type instructions, but also for `qc.li` which takes a symbol with a specifier.

---
Full diff: https://github.com/llvm/llvm-project/pull/146184.diff


6 Files Affected:

- (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp (+3) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+6-6) 
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+6-1) 
- (modified) llvm/test/MC/RISCV/xqcibi-relocations.s (+16) 
- (modified) llvm/test/MC/RISCV/xqcilb-relocations.s (+18) 
- (modified) llvm/test/MC/RISCV/xqcili-relocations.s (+18) 


``````````diff

diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
index d407beffcd7d1..835d38382acd5 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
@@ -12,9 +12,12 @@
 //===----------------------------------------------------------------------===//
 
 #include "RISCVBaseInfo.h"
+#include "MCTargetDesc/RISCVMCAsmInfo.h"
+#include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Casting.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TargetParser/TargetParser.h"
 #include "llvm/TargetParser/Triple.h"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index 8252a9b170eb3..de235b3d8dde8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -37,9 +37,9 @@ def uimmlog2xlennonzero : RISCVOp, ImmLeaf<XLenVT, [{
 def simm6 : RISCVSImmLeafOp<6> {
   let MCOperandPredicate = [{
     int64_t Imm;
-    if (MCOp.evaluateAsConstantImm(Imm))
-      return isInt<6>(Imm);
-    return MCOp.isBareSymbolRef();
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return isInt<6>(Imm);
   }];
 }
 
@@ -51,9 +51,9 @@ def simm6nonzero : RISCVOp,
   let OperandType = "OPERAND_SIMM6_NONZERO";
   let MCOperandPredicate = [{
     int64_t Imm;
-    if (MCOp.evaluateAsConstantImm(Imm))
-      return (Imm != 0) && isInt<6>(Imm);
-    return MCOp.isBareSymbolRef();
+    if (!MCOp.evaluateAsConstantImm(Imm))
+      return false;
+    return (Imm != 0) && isInt<6>(Imm);
   }];
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 64c5910293b55..240d91c03488b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -146,7 +146,12 @@ def simm20_li : RISCVOp<XLenVT>,
     int64_t Imm;
     if (MCOp.evaluateAsConstantImm(Imm))
       return isInt<20>(Imm);
-    return MCOp.isBareSymbolRef();
+
+    if (!MCOp.isExpr())
+      return false;
+
+    return MCOp.getExpr()->getKind() == MCExpr::Specifier &&
+      cast<MCSpecifierExpr>(MCOp.getExpr())->getSpecifier() == RISCV::S_QC_ABS20;
   }];
 }
 
diff --git a/llvm/test/MC/RISCV/xqcibi-relocations.s b/llvm/test/MC/RISCV/xqcibi-relocations.s
index 0f7cc8c5787a1..6af496f353ee3 100644
--- a/llvm/test/MC/RISCV/xqcibi-relocations.s
+++ b/llvm/test/MC/RISCV/xqcibi-relocations.s
@@ -86,6 +86,22 @@ qc.e.bgeui s2, 24, same_section
 
 .option norelax
 
+## Enable compression/relaxation to check how symbols are handled.
+.option noexact
+.option relax
+
+# ASM: qc.bnei t1, 10, undef
+# OBJ: qc.beqi t1, 0xa, 0x42 <same_section_extern+0x16>
+# OBJ-NEXT: j 0x3e <same_section_extern+0x12>
+# OBJ-NEXT: R_RISCV_JAL undef{{$}}
+qc.bnei t1, 10, undef
+
+# ASM: qc.e.bgeui s0, 40, undef
+# OBJ-NEXT: qc.e.bltui s0, 0x28, 0x4c <same_section_extern+0x20>
+# OBJ-NEXT: j 0x48 <same_section_extern+0x1c>
+# OBJ-NEXT: R_RISCV_JAL undef{{$}}
+qc.e.bgeui s0, 40, undef
+
 .section .text.second, "ax", @progbits
 
 # ASM-LABEL: other_section:
diff --git a/llvm/test/MC/RISCV/xqcilb-relocations.s b/llvm/test/MC/RISCV/xqcilb-relocations.s
index ab08beed9be94..daf84a6b200c5 100644
--- a/llvm/test/MC/RISCV/xqcilb-relocations.s
+++ b/llvm/test/MC/RISCV/xqcilb-relocations.s
@@ -94,6 +94,24 @@ qc.e.jal same_section
 
 .option norelax
 
+## Enable compression/relaxation to check how symbols are handled.
+.option noexact
+.option relax
+
+qc.e.j undef
+# ASM: j undef
+# OBJ: qc.e.j 0x44 <same_section_extern+0x10>
+# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
+# OBJ-NEXT: R_RISCV_RELAX
+
+qc.e.jal undef
+# ASM: jal undef
+# OBJ: qc.e.jal 0x4a <same_section_extern+0x16>
+# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM195 undef{{$}}
+# OBJ-NEXT: R_RISCV_RELAX
+
 .section .text.other, "ax", @progbits
 
 # ASM-LABEL: other_section:
diff --git a/llvm/test/MC/RISCV/xqcili-relocations.s b/llvm/test/MC/RISCV/xqcili-relocations.s
index 866586236fa46..356c1c89a516d 100644
--- a/llvm/test/MC/RISCV/xqcili-relocations.s
+++ b/llvm/test/MC/RISCV/xqcili-relocations.s
@@ -99,6 +99,24 @@ qc.e.li s1, undef
 
 .option norelax
 
+## Enable compression/relaxation to check how symbols are handled.
+.option noexact
+.option relax
+
+# ASM: qc.li a1, %qc.abs20(undef)
+# OBJ-NEXT: qc.li a1, 0x0
+# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM192 undef{{$}}
+# OBJ-NEXT: R_RISCV_RELAX
+qc.li a1, %qc.abs20(undef)
+
+# ASM: qc.e.li a1, undef
+# OBJ-NEXT: qc.e.li a1, 0x0
+# OBJ-NEXT: R_RISCV_VENDOR QUALCOMM{{$}}
+# OBJ-NEXT: R_RISCV_CUSTOM194 undef{{$}}
+# OBJ-NEXT: R_RISCV_RELAX
+qc.e.li a1, undef
+
 .section .text.other, "ax", @progbits
 
 # ASM-LABEL: other_section:

``````````

</details>


https://github.com/llvm/llvm-project/pull/146184
