[llvm] [AMDGPU] Support merging 16-bit TBUFFER load/store instruction (PR #145078)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 24 03:03:41 PDT 2025
https://github.com/arsenm commented:
I still think we should be doing this kind of merging in the IR. SILoadStoreOptimizer was originally intended only for the case of combining the DS read/write from non-consecutive offsets. Everything else could have been done like a normal vectorization
https://github.com/llvm/llvm-project/pull/145078
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