[llvm] [AMDGPU] Support merging 16-bit TBUFFER load/store instruction (PR #145078)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm commented:

I still think we should be doing this kind of merging in the IR. SILoadStoreOptimizer was originally intended only for the case of combining the DS read/write from non-consecutive offsets. Everything else could have been done like a normal vectorization 

https://github.com/llvm/llvm-project/pull/145078