[llvm] [RISCV] Support RVV register overlapping constraints (PR #145004)

[Philip Reames via llvm-commits]

preames wrote:

Glad to see the investigation.  I've stumbled into this a few times myself, and agree that the first step is trying to get some sense of how much impact fixing this would be.  All of the approaches I've come up with involve significant investment, so getting a bound on the benefit seems quite worthwhile.  

@wangpc-pp - Did you get any estimate of runtime impact?  I realize this might be quite challenging, but even something like dynamic icount for a modified qemu might be interesting.  Essentially, I'm curious as to where the spills and fills are, and whether removing some of them actually helps.  

Worth noting is that once we get to implementation, there's a couple possible sub-cases we can handle without solving the whole problem.  e.g. If I remember my prior investigation correctly, I think we can handle many of the mask generating instructions with some extra pseudos in the current scheme.  

https://github.com/llvm/llvm-project/pull/145004