[llvm] [DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (PR #145298)

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woruyu wrote:

Note 2:
There are many cases involved, the backends include AArch64 ARM lasx msa powerPC SystmeZ，Currently, I haven't debug them. What I've seen is that some backends seem to have vsel xxsel instructions. ARM seems to have its own optimized code, which will cause the register position to change. In addition, some case instructions have increased significantly.

https://github.com/llvm/llvm-project/pull/145298