[llvm] [DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (PR #145298)

[via llvm-commits]

woruyu wrote:

Note 1:
urem-seteq-vec-tautological.ll, i print debug log and find the difference just in one DAG Node
origin debug log
```
// origin debug log
Combining: t33: v4i32 = vselect t31, t32, t27
Creating new node: t34: v4i32 = vector_shuffle<4,1,6,3> t32, t27
 ... into: t34: v4i32 = vector_shuffle<4,1,6,3> t32, t27

// pr debug log
Combining: t33: v4i32 = vselect t31, t32, t27
Creating new node: t34: v4i32 = or t27, t31
 ... into: t34: v4i32 = or t27, t31

// DAG
Optimized lowered selection DAG: %bb.0 't1_all_odd_ne:'
SelectionDAG has 17 nodes:
  t0: ch,glue = EntryToken
      t32: v4i32 = BUILD_VECTOR Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>
          t2: v4i32,ch = CopyFromReg t0, Register:v4i32 %0
          t22: v4i32 = BUILD_VECTOR Constant:i32<-1431655765>, Constant:i32<-1431655765>, Constant:i32<-1431655765>, Constant:i32<-1431655765>
        t25: v4i32 = mul t2, t22
        t24: v4i32 = BUILD_VECTOR Constant:i32<1431655765>, Constant:i32<-1>, Constant:i32<-1>, Constant:i32<-1>
      t27: v4i32 = setcc t25, t24, setugt:ch
    t34: v4i32 = vector_shuffle<4,1,6,3> t32, t27
  t16: ch,glue = CopyToReg t0, Register:v4i32 $xmm0, t34
  t17: ch = X86ISD::RET_GLUE t16, TargetConstant:i32<0>, Register:v4i32 $xmm0, t16:1
```

The reason is the execution order of the code. After moving to DAGCombine, the combineVSelectWithAllOnesOrZeros is executed first. It should be a problem of optimization order, but I think this case should be faster (fewer instructions)
```
if (N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::BLENDV) {
    SmallVector<int, 64> Mask;
    if (createShuffleMaskFromVSELECT(Mask, Cond,
                                     N->getOpcode() == X86ISD::BLENDV)) {
      // Convert vselects with constant condition into shuffles.
      if (DCI.isBeforeLegalizeOps())
        return DAG.getVectorShuffle(VT, DL, LHS, RHS, Mask);

      // Attempt to combine as shuffle.
      SDValue Op(N, 0);
      if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
        return Res;
    }
  }
```

https://github.com/llvm/llvm-project/pull/145298