[llvm] [RISCV] Add isel patterns for generating XAndesPerf branch immediate instructions (PR #145147)

[Jim Lin via llvm-commits]

================
@@ -1501,6 +1525,11 @@ bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
   switch (BranchOp) {
   default:
     llvm_unreachable("Unexpected opcode!");
+  case RISCV::NDS_BBC:
+  case RISCV::NDS_BBS:
+  case RISCV::NDS_BEQC:
+  case RISCV::NDS_BNEC:
+    return isIntN(11, BrOffset);
----------------
tclin914 wrote:

Done. Thanks

https://github.com/llvm/llvm-project/pull/145147