[llvm] [AVR] Don't apply post-indexing on mismatched pointers (PR #145224)

[Patryk Wychowaniec via llvm-commits]

https://github.com/Patryk27 updated https://github.com/llvm/llvm-project/pull/145224

>From f5c46ce01e78c0a1845fb2663ccff21a70a6940b Mon Sep 17 00:00:00 2001
From: Patryk Wychowaniec <pwychowaniec at pm.me>
Date: Sun, 22 Jun 2025 10:46:16 +0200
Subject: [PATCH] [AVR] Don't apply post-indexing on mismatched pointers

Cut out of https://github.com/llvm/llvm-project/pull/145040; thanks to
@tomtor for preparing the test.

Basically, we're hitting the same edge case as RISC-V and aarch64:

- https://github.com/llvm/llvm-project/blob/2ed089fb18b92ad668509076b9830f55d96d27fe/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L23545
- https://github.com/llvm/llvm-project/blob/2ed089fb18b92ad668509076b9830f55d96d27fe/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L27144

Closes https://github.com/llvm/llvm-project/issues/143247.
---
 llvm/lib/Target/AVR/AVRISelLowering.cpp |  9 +++++++
 llvm/test/CodeGen/AVR/bug-143247.ll     | 36 +++++++++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 llvm/test/CodeGen/AVR/bug-143247.ll

diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 9747ad0c5cd58..3955f2a252e76 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1071,14 +1071,17 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                                    ISD::MemIndexedMode &AM,
                                                    SelectionDAG &DAG) const {
   EVT VT;
+  SDValue Ptr;
   SDLoc DL(N);
 
   if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
     VT = LD->getMemoryVT();
+    Ptr = LD->getBasePtr();
     if (LD->getExtensionType() != ISD::NON_EXTLOAD)
       return false;
   } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
     VT = ST->getMemoryVT();
+    Ptr = ST->getBasePtr();
     // We can not store to program memory.
     if (AVR::isProgramMemoryAccess(ST))
       return false;
@@ -1115,6 +1118,12 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
         return false;
 
     Base = Op->getOperand(0);
+
+    // Post-indexing updates the base, so it's not a valid transform
+    // if that's not the same as the load's pointer.
+    if (Ptr != Base)
+      return false;
+
     Offset = DAG.getConstant(RHSC, DL, MVT::i8);
     AM = ISD::POST_INC;
 
diff --git a/llvm/test/CodeGen/AVR/bug-143247.ll b/llvm/test/CodeGen/AVR/bug-143247.ll
new file mode 100644
index 0000000000000..07c4c6562c950
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/bug-143247.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -O=2 -mtriple=avr-none --mcpu=avr128db28 -verify-machineinstrs | FileCheck %s
+
+declare dso_local void @nil(i16 noundef) addrspace(1)
+
+define void @complex_sbi() {
+; CHECK-LABEL: complex_sbi:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    push r16
+; CHECK-NEXT:    push r17
+; CHECK-NEXT:    ldi r24, 0
+; CHECK-NEXT:    ldi r25, 0
+; CHECK-NEXT:  .LBB0_1: ; %while.cond
+; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    sbi 1, 7
+; CHECK-NEXT:    adiw r24, 1
+; CHECK-NEXT:    movw r16, r24
+; CHECK-NEXT:    andi r24, 15
+; CHECK-NEXT:    andi r25, 0
+; CHECK-NEXT:    adiw r24, 1
+; CHECK-NEXT:    call nil
+; CHECK-NEXT:    movw r24, r16
+; CHECK-NEXT:    rjmp .LBB0_1
+entry:
+  br label %while.cond
+while.cond:
+  %s.0 = phi i16 [ 0, %entry ], [ %inc, %while.cond ]
+  %inc = add nuw nsw i16 %s.0, 1
+  %0 = load volatile i8, ptr inttoptr (i16 1 to ptr), align 1
+  %or = or i8 %0, -128
+  store volatile i8 %or, ptr inttoptr (i16 1 to ptr), align 1
+  %and = and i16 %inc, 15
+  %add = add nuw nsw i16 %and, 1
+  tail call addrspace(1) void @nil(i16 noundef %add)
+  br label %while.cond
+}