[llvm] [AArch64] Use 0-cycle reg2reg MOVs for FPR32, FPR16, FPR8 (PR #144152)

[Tomer Shafir via llvm-commits]

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@@ -5302,30 +5302,73 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   if (AArch64::FPR32RegClass.contains(DestReg) &&
       AArch64::FPR32RegClass.contains(SrcReg)) {
-    BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
-        .addReg(SrcReg, getKillRegState(KillSrc));
+    if (Subtarget.isTargetDarwin() && Subtarget.hasZeroCycleRegMove()) {
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tomershafir wrote:

I agree. Ill add new subtarget features, though per register class and not underlying register names, like `hasZeroCycleRegMoveFPR64`.

https://github.com/llvm/llvm-project/pull/144152