[llvm] CodeGen: Emit error if getRegisterByName fails (PR #145194)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 21 16:59:07 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
This avoids using report_fatal_error and standardizes the error
message in a subset of the error conditions.
---
Patch is 29.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/145194.diff
29 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+12-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+36-11)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+2-5)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-5)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+3-7)
- (modified) llvm/lib/Target/Hexagon/HexagonISelLowering.cpp (+1-4)
- (modified) llvm/lib/Target/Lanai/LanaiISelLowering.cpp (+3-6)
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+3-4)
- (modified) llvm/lib/Target/Mips/MipsISelLowering.cpp (+7-10)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+1-2)
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4-4)
- (modified) llvm/lib/Target/Sparc/SparcISelLowering.cpp (+2-5)
- (modified) llvm/lib/Target/SystemZ/SystemZISelLowering.cpp (+2-4)
- (modified) llvm/lib/Target/VE/VEISelLowering.cpp (+2-6)
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+1-4)
- (modified) llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll (+4-4)
- (modified) llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll (+4-4)
- (added) llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll (+90)
- (added) llvm/test/CodeGen/AMDGPU/write-register-invalid-register.ll (+10)
- (modified) llvm/test/CodeGen/ARM/named-reg-alloc.ll (+4-4)
- (modified) llvm/test/CodeGen/ARM/named-reg-notareg.ll (+4-4)
- (modified) llvm/test/CodeGen/ARM/special-reg-acore.ll (+4-2)
- (modified) llvm/test/CodeGen/ARM/special-reg-mcore.ll (+5-4)
- (modified) llvm/test/CodeGen/ARM/special-reg-v8m-base.ll (+2-2)
- (modified) llvm/test/CodeGen/ARM/special-reg-v8m-main.ll (+2-2)
- (modified) llvm/test/CodeGen/RISCV/get-register-invalid.ll (+2-2)
- (modified) llvm/test/CodeGen/SPARC/reserved-regs-unavailable.ll (+2-2)
- (modified) llvm/test/CodeGen/X86/named-reg-alloc.ll (+4-4)
- (modified) llvm/test/CodeGen/X86/named-reg-notareg.ll (+4-4)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a28361051b418..e0656141d4326 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9107,8 +9107,18 @@ LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));
Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF);
- if (!PhysReg.isValid())
- return UnableToLegalize;
+ if (!PhysReg) {
+ const Function &Fn = MF.getFunction();
+ Fn.getContext().diagnose(DiagnosticInfoGenericWithLoc(
+ "invalid register \"" + Twine(RegStr->getString().data()) + "\" for " +
+ (IsRead ? "llvm.read_register" : "llvm.write_register"),
+ Fn, MI.getDebugLoc()));
+ if (IsRead)
+ MIRBuilder.buildUndef(ValReg);
+
+ MI.eraseFromParent();
+ return Legalized;
+ }
if (IsRead)
MIRBuilder.buildCopy(ValReg, PhysReg);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 4b98d87fcc63b..d9b9cf6bcc772 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2460,11 +2460,25 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
EVT VT = Op->getValueType(0);
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
- Register Reg =
- TLI->getRegisterByName(RegStr->getString().data(), Ty,
- CurDAG->getMachineFunction());
- SDValue New = CurDAG->getCopyFromReg(
- Op->getOperand(0), dl, Reg, Op->getValueType(0));
+
+ const MachineFunction &MF = CurDAG->getMachineFunction();
+ Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
+
+ SDValue New;
+ if (!Reg) {
+ const Function &Fn = MF.getFunction();
+ Fn.getContext().diagnose(DiagnosticInfoGenericWithLoc(
+ "invalid register \"" + Twine(RegStr->getString().data()) +
+ "\" for llvm.read_register",
+ Fn, Op->getDebugLoc()));
+ New =
+ SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
+ ReplaceUses(SDValue(Op, 1), Op->getOperand(0));
+ } else {
+ New =
+ CurDAG->getCopyFromReg(Op->getOperand(0), dl, Reg, Op->getValueType(0));
+ }
+
New->setNodeId(-1);
ReplaceUses(Op, New.getNode());
CurDAG->RemoveDeadNode(Op);
@@ -2478,12 +2492,23 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
EVT VT = Op->getOperand(2).getValueType();
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
- Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
- CurDAG->getMachineFunction());
- SDValue New = CurDAG->getCopyToReg(
- Op->getOperand(0), dl, Reg, Op->getOperand(2));
- New->setNodeId(-1);
- ReplaceUses(Op, New.getNode());
+ const MachineFunction &MF = CurDAG->getMachineFunction();
+ Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
+
+ if (!Reg) {
+ const Function &Fn = MF.getFunction();
+ Fn.getContext().diagnose(DiagnosticInfoGenericWithLoc(
+ "invalid register \"" + Twine(RegStr->getString().data()) +
+ "\" for llvm.write_register",
+ Fn, Op->getDebugLoc()));
+ ReplaceUses(SDValue(Op, 0), Op->getOperand(0));
+ } else {
+ SDValue New =
+ CurDAG->getCopyToReg(Op->getOperand(0), dl, Reg, Op->getOperand(2));
+ New->setNodeId(-1);
+ ReplaceUses(Op, New.getNode());
+ }
+
CurDAG->RemoveDeadNode(Op);
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index a2c914c6e09c2..1f98d69edb473 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11977,12 +11977,9 @@ getRegisterByName(const char* RegName, LLT VT, const MachineFunction &MF) const
unsigned DwarfRegNum = MRI->getDwarfRegNum(Reg, false);
if (!Subtarget->isXRegisterReserved(DwarfRegNum) &&
!MRI->isReservedReg(MF, Reg))
- Reg = 0;
+ Reg = Register();
}
- if (Reg)
- return Reg;
- report_fatal_error(Twine("Invalid register name \""
- + StringRef(RegName) + "\"."));
+ return Reg;
}
SDValue AArch64TargetLowering::LowerADDROFRETURNADDR(SDValue Op,
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index b9023b6d7a3a6..6d0736aa792f5 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4492,11 +4492,8 @@ Register SITargetLowering::getRegisterByName(const char *RegName, LLT VT,
.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
.Default(Register());
-
- if (Reg == AMDGPU::NoRegister) {
- report_fatal_error(
- Twine("invalid register name \"" + StringRef(RegName) + "\"."));
- }
+ if (!Reg)
+ return Reg;
if (!Subtarget->hasFlatScrRegister() &&
Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 4567081fe78dc..2400761975f81 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -6166,13 +6166,9 @@ SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
// this table could be generated automatically from RegInfo.
Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
const MachineFunction &MF) const {
- Register Reg = StringSwitch<unsigned>(RegName)
- .Case("sp", ARM::SP)
- .Default(0);
- if (Reg)
- return Reg;
- report_fatal_error(Twine("Invalid register name \""
- + StringRef(RegName) + "\"."));
+ return StringSwitch<Register>(RegName)
+ .Case("sp", ARM::SP)
+ .Default(Register());
}
// Result is 64 bit value so split into two 32 bit values and return as a
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 078eccaa706a2..6534ae938fede 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -329,10 +329,7 @@ Register HexagonTargetLowering::getRegisterByName(
.Case("cs0", Hexagon::CS0)
.Case("cs1", Hexagon::CS1)
.Default(Register());
- if (Reg)
- return Reg;
-
- report_fatal_error("Invalid register name global variable");
+ return Reg;
}
/// LowerCallResult - Lower the result values of an ISD::CALL into the
diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index 7781817aef71a..16ea2c8461fa4 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -211,7 +211,7 @@ Register LanaiTargetLowering::getRegisterByName(
const char *RegName, LLT /*VT*/,
const MachineFunction & /*MF*/) const {
// Only unallocatable registers should be matched here.
- Register Reg = StringSwitch<unsigned>(RegName)
+ Register Reg = StringSwitch<Register>(RegName)
.Case("pc", Lanai::PC)
.Case("sp", Lanai::SP)
.Case("fp", Lanai::FP)
@@ -220,11 +220,8 @@ Register LanaiTargetLowering::getRegisterByName(
.Case("rr2", Lanai::RR2)
.Case("r11", Lanai::R11)
.Case("rca", Lanai::RCA)
- .Default(0);
-
- if (Reg)
- return Reg;
- report_fatal_error("Invalid register name global variable");
+ .Default(Register());
+ return Reg;
}
std::pair<unsigned, const TargetRegisterClass *>
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 99dae6ec3eb08..6946ed554a7e5 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -7957,11 +7957,10 @@ LoongArchTargetLowering::getRegisterByName(const char *RegName, LLT VT,
std::pair<StringRef, StringRef> Name = StringRef(RegName).split('$');
std::string NewRegName = Name.second.str();
Register Reg = MatchRegisterAltName(NewRegName);
- if (Reg == LoongArch::NoRegister)
+ if (!Reg)
Reg = MatchRegisterName(NewRegName);
- if (Reg == LoongArch::NoRegister)
- report_fatal_error(
- Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
+ if (!Reg)
+ return Reg;
BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
if (!ReservedRegs.test(Reg))
report_fatal_error(Twine("Trying to obtain non-reserved register \"" +
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index e933e97ea3706..9b4b336727235 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4969,17 +4969,14 @@ MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
.Case("$28", Mips::GP_64)
.Case("sp", Mips::SP_64)
.Default(Register());
- if (Reg)
- return Reg;
- } else {
- Register Reg = StringSwitch<Register>(RegName)
- .Case("$28", Mips::GP)
- .Case("sp", Mips::SP)
- .Default(Register());
- if (Reg)
- return Reg;
+ return Reg;
}
- report_fatal_error("Invalid register name global variable");
+
+ Register Reg = StringSwitch<Register>(RegName)
+ .Case("$28", Mips::GP)
+ .Case("sp", Mips::SP)
+ .Default(Register());
+ return Reg;
}
MachineBasicBlock *MipsTargetLowering::emitLDR_W(MachineInstr &MI,
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f502d8570425a..421a808de667a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -17984,8 +17984,7 @@ Register PPCTargetLowering::getRegisterByName(const char *RegName, LLT VT,
Register Reg = MatchRegisterName(RegName);
if (!Reg)
- report_fatal_error(
- Twine("Invalid global name register \"" + StringRef(RegName) + "\"."));
+ return Reg;
// FIXME: Unable to generate code for `-O2` but okay for `-O0`.
// Need followup investigation as to why.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 9e568052079ce..d7cfdd9905d00 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -24563,11 +24563,11 @@ Register
RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const {
Register Reg = MatchRegisterAltName(RegName);
- if (Reg == RISCV::NoRegister)
+ if (!Reg)
Reg = MatchRegisterName(RegName);
- if (Reg == RISCV::NoRegister)
- report_fatal_error(
- Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
+ if (!Reg)
+ return Reg;
+
BitVector ReservedRegs = Subtarget.getRegisterInfo()->getReservedRegs(MF);
if (!ReservedRegs.test(Reg) && !Subtarget.isRegisterReservedByUser(Reg))
report_fatal_error(Twine("Trying to obtain non-reserved register \"" +
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 21ecf3d5ed70e..7abe84a2451b9 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1162,12 +1162,9 @@ Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
// make sure that said register is in the reserve list.
const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
if (!TRI->isReservedReg(MF, Reg))
- Reg = 0;
+ Reg = Register();
- if (Reg)
- return Reg;
-
- report_fatal_error("Invalid register name global variable");
+ return Reg;
}
// Fixup floating point arguments in the ... part of a varargs call.
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 1c59b1e63b7bc..831618c4eff5f 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1713,11 +1713,9 @@ SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT,
: SystemZ::NoRegister)
.Case("r15",
Subtarget.isTargetELF() ? SystemZ::R15D : SystemZ::NoRegister)
- .Default(SystemZ::NoRegister);
+ .Default(Register());
- if (Reg)
- return Reg;
- report_fatal_error("Invalid register name global variable");
+ return Reg;
}
Register SystemZTargetLowering::getExceptionPointerRegister(
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 98c5fdd138986..a0389aef6dce4 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -563,12 +563,8 @@ Register VETargetLowering::getRegisterByName(const char *RegName, LLT VT,
.Case("info", VE::SX17) // Info area register
.Case("got", VE::SX15) // Global offset table register
.Case("plt", VE::SX16) // Procedure linkage table register
- .Default(0);
-
- if (Reg)
- return Reg;
-
- report_fatal_error("Invalid register name global variable");
+ .Default(Register());
+ return Reg;
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 53c0da45f2f66..1c2b7ea5641ed 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -28312,10 +28312,7 @@ Register X86TargetLowering::getRegisterByName(const char* RegName, LLT VT,
#endif
}
- if (Reg)
- return Reg;
-
- report_fatal_error("Invalid register name global variable");
+ return Reg;
}
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll
index bd14ec61b55cc..1f18e9266fa90 100644
--- a/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-alloc.ll
@@ -1,11 +1,11 @@
-; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=arm64-apple-darwin -filetype=null 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=arm64-linux-gnueabi -filetype=null 2>&1 | FileCheck %s
define i32 @get_stack() nounwind {
entry:
; FIXME: Include an allocatable-specific error message
-; CHECK: Invalid register name "x5".
- %sp = call i32 @llvm.read_register.i32(metadata !0)
+; CHECK: error: <unknown>:0:0: invalid register "x5" for llvm.read_register
+ %sp = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %sp
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
index fe5f000a393e7..b671026251da8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-named-reg-notareg.ll
@@ -1,10 +1,10 @@
-; RUN: not --crash llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=arm64-apple-darwin 2>&1 | FileCheck %s
+; RUN: not llc < %s -mtriple=arm64-linux-gnueabi 2>&1 | FileCheck %s
define i32 @get_stack() nounwind {
entry:
-; CHECK: Invalid register name "notareg".
- %sp = call i32 @llvm.read_register.i32(metadata !0)
+; CHECK: error: <unknown>:0:0: invalid register "notareg" for llvm.read_register
+ %sp = call i32 @llvm.read_register.i32(metadata !0)
ret i32 %sp
}
diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
new file mode 100644
index 0000000000000..28f9ca8d6576f
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-register.ll
@@ -0,0 +1,90 @@
+; RUN: not llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error %s
+; RUN: not llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error %s
+
+declare i32 @llvm.read_register.i32(metadata) #0
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_i1(ptr addrspace(1) %out) nounwind {
+ %reg = call i1 @llvm.read_register.i1(metadata !0)
+ store i1 %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_i16(ptr addrspace(1) %out) nounwind {
+ %reg = call i16 @llvm.read_register.i16(metadata !0)
+ store i16 %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_i32(ptr addrspace(1) %out) nounwind {
+ %reg = call i32 @llvm.read_register.i32(metadata !0)
+ store i32 %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_i64(ptr addrspace(1) %out) nounwind {
+ %reg = call i64 @llvm.read_register.i64(metadata !0)
+ store i64 %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v2i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <2 x i32> @llvm.read_register.v2i32(metadata !0)
+ store <2 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v3i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <3 x i32> @llvm.read_register.v3i32(metadata !0)
+ store <3 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v4i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <4 x i32> @llvm.read_register.v4i32(metadata !0)
+ store <4 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v5i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <5 x i32> @llvm.read_register.v5i32(metadata !0)
+ store <5 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v6i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <6 x i32> @llvm.read_register.v6i32(metadata !0)
+ store <6 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v8i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <8 x i32> @llvm.read_register.v8i32(metadata !0)
+ store <8 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid register "not-a-register" for llvm.read_register
+define amdgpu_kernel void @test_invalid_register_v16i32(ptr addrspace(1) %out) nounwind {
+ %reg = call <16 x i32> @llvm.read_register.v16i32(metadata !0)
+ store <16 x i32> %reg, ptr addrspace(1) %out
+ ret void
+}
+
+; CHECK: error: <unknown>:0:0: invalid...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/145194
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