[llvm] [SelectionDAG][RISCV] Add support for splitting vp.splice (PR #145184)

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github-actions[bot] wrote:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 745f386e5..206c99d99 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3269,7 +3269,8 @@ void DAGTypeLegalizer::SplitVecRes_VP_SPLICE(SDNode *N, SDValue &Lo,
     SDValue TrailingBytes = DAG.getConstant(TrailingElts * EltWidth, DL, PtrVT);
 
     // Make sure TrailingBytes doesn't exceed the size of vec1.
-    TrailingBytes = DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, OffsetToV2);
+    TrailingBytes =
+        DAG.getNode(ISD::UMIN, DL, PtrVT, TrailingBytes, OffsetToV2);
 
     // Calculate the start address of the spliced result.
     StackPtr2 = DAG.getNode(ISD::SUB, DL, PtrVT, StackPtr2, TrailingBytes);

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https://github.com/llvm/llvm-project/pull/145184