[llvm] [AVR] Temp fix for getPostIndexedAddressParts() (PR #145040)

[Patryk Wychowaniec via llvm-commits]

Patryk27 wrote:

Ok, got it - I think we're hitting the same condition RISC-V and aarch64 are already guarded against:

- https://github.com/llvm/llvm-project/blob/2ed089fb18b92ad668509076b9830f55d96d27fe/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L23545
- https://github.com/llvm/llvm-project/blob/2ed089fb18b92ad668509076b9830f55d96d27fe/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L27144

So _I thiiiink_ the proper fix would be to:

```patch
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index d65ef8986c98..c319499ecc05 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -1120,12 +1120,22 @@ bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
       if (AVR::isProgramMemoryAccess(LD))
         return false;
 
-    // Fixes https://github.com/llvm/llvm-project/issues/143247
-    if (Op->getOperand(0)->hasOneUse())
+    SDValue Ptr;
+    if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
+      Ptr = LD->getBasePtr();
+    } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
+      Ptr = ST->getBasePtr();
+    } else
       return false;
 
     Base = Op->getOperand(0);
     Offset = DAG.getConstant(RHSC, DL, MVT::i8);
+
+    // Post-indexing updates the base, so it's not a valid transform
+    // if that's not the same as the load's pointer.
+    if (Ptr != Base)
+      return false;
+
     AM = ISD::POST_INC;
 
     return true;
```

https://github.com/llvm/llvm-project/pull/145040