[llvm] [WebAssembly] Fix missed optimization in 50142 (PR #144741)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 21 09:41:46 PDT 2025
https://github.com/badumbatish updated https://github.com/llvm/llvm-project/pull/144741
>From f1182710b66e1793bd8a9688aa6113b0470bce10 Mon Sep 17 00:00:00 2001
From: badumbatish <tanghocle456 at gmail.com>
Date: Wed, 18 Jun 2025 16:38:11 -0700
Subject: [PATCH 1/3] Precommit missed optimization test for #50142
---
.../WebAssembly/simd-setcc-reductions.ll | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
new file mode 100644
index 0000000000000..2cc730e6ff530
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+
+target triple = "wasm64"
+
+define i32 @all_true_16_i8(<16 x i8> %v) {
+; CHECK-LABEL: all_true_16_i8:
+; CHECK: .functype all_true_16_i8 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i8x16.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <16 x i8> %v, zeroinitializer
+ %2 = bitcast <16 x i1> %1 to i16
+ %3 = icmp eq i16 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_4_i32(<4 x i32> %v) {
+; CHECK-LABEL: all_true_4_i32:
+; CHECK: .functype all_true_4_i32 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0
+; CHECK-NEXT: i32x4.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <4 x i32> %v, zeroinitializer
+ %2 = bitcast <4 x i1> %1 to i4
+ %3 = icmp eq i4 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_8_i16(<8 x i16> %v) {
+; CHECK-LABEL: all_true_8_i16:
+; CHECK: .functype all_true_8_i16 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i16x8.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <8 x i16> %v, zeroinitializer
+ %2 = bitcast <8 x i1> %1 to i8
+ %3 = icmp eq i8 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_2_i64(<2 x i64> %v) {
+; CHECK-LABEL: all_true_2_i64:
+; CHECK: .functype all_true_2_i64 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0
+; CHECK-NEXT: i64x2.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <2 x i64> %v, zeroinitializer
+ %2 = bitcast <2 x i1> %1 to i2
+ %3 = icmp eq i2 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
>From 4c08f49e2310f11c5402928e730246405d740697 Mon Sep 17 00:00:00 2001
From: badumbatish <jjasmine at igalia.com>
Date: Thu, 19 Jun 2025 15:31:21 -0700
Subject: [PATCH 2/3] Fix issue 50142 by adding AnyTrueCombine
This introduces the fold (any_true (setcc <X> 0, eq)) to (not
(all_true)), allowing potential extra fold of (not (not ...))
Introduces test simd-setcc-reductions and readjusts simd-vecreduce-bool
---
.../WebAssembly/WebAssemblyISelLowering.cpp | 41 ++++++++++++++++++-
.../WebAssembly/simd-setcc-reductions.ll | 40 ++++--------------
.../WebAssembly/simd-vecreduce-bool.ll | 6 +--
3 files changed, 51 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 3cd923c0ba058..bce8f0e7b84ee 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -3239,6 +3239,42 @@ static SDValue performBitcastCombine(SDNode *N,
return SDValue();
}
+static SDValue performAnyTrueCombine(SDNode *N, SelectionDAG &DAG) {
+ // any_true (setcc <X>, 0, eq)
+ // => not (all_true X)
+
+ SDLoc DL(N);
+ assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
+ if (N->getConstantOperandVal(0) != Intrinsic::wasm_anytrue)
+ return SDValue();
+
+ SDValue SetCC = N->getOperand(1);
+ if (SetCC.getOpcode() != ISD::SETCC)
+ return SDValue();
+
+ SDValue LHS = SetCC->getOperand(0);
+ SDValue RHS = SetCC->getOperand(1);
+ ISD::CondCode Cond = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
+ EVT LT = LHS.getValueType();
+ unsigned NumElts = LT.getVectorNumElements();
+ if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
+ return SDValue();
+
+ EVT Width = MVT::getIntegerVT(128 / NumElts);
+
+ if (!isNullOrNullSplat(RHS) || Cond != ISD::SETEQ)
+ return SDValue();
+
+ SDValue Ret = DAG.getZExtOrTrunc(
+ DAG.getNode(
+ ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+ {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
+ DAG.getSExtOrTrunc(LHS, DL, LT.changeVectorElementType(Width))}),
+ DL, MVT::i1);
+ Ret = DAG.getNOT(DL, Ret, MVT::i1);
+ return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
+}
+
static SDValue performSETCCCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
auto &DAG = DCI.DAG;
@@ -3400,8 +3436,11 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
return performVectorTruncZeroCombine(N, DCI);
case ISD::TRUNCATE:
return performTruncateCombine(N, DCI);
- case ISD::INTRINSIC_WO_CHAIN:
+ case ISD::INTRINSIC_WO_CHAIN: {
+ if (auto AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
+ return AnyTrueCombine;
return performLowerPartialReduction(N, DCI.DAG);
+ }
case ISD::MUL:
return performMulCombine(N, DCI.DAG);
}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
index 2cc730e6ff530..1d0a688216765 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
@@ -7,14 +7,8 @@ define i32 @all_true_16_i8(<16 x i8> %v) {
; CHECK-LABEL: all_true_16_i8:
; CHECK: .functype all_true_16_i8 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: i8x16.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i8x16.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <16 x i8> %v, zeroinitializer
%2 = bitcast <16 x i1> %1 to i16
%3 = icmp eq i16 %2, 0
@@ -27,14 +21,8 @@ define i32 @all_true_4_i32(<4 x i32> %v) {
; CHECK-LABEL: all_true_4_i32:
; CHECK: .functype all_true_4_i32 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT: i32x4.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i32x4.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <4 x i32> %v, zeroinitializer
%2 = bitcast <4 x i1> %1 to i4
%3 = icmp eq i4 %2, 0
@@ -47,14 +35,8 @@ define i32 @all_true_8_i16(<8 x i16> %v) {
; CHECK-LABEL: all_true_8_i16:
; CHECK: .functype all_true_8_i16 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: i16x8.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i16x8.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <8 x i16> %v, zeroinitializer
%2 = bitcast <8 x i1> %1 to i8
%3 = icmp eq i8 %2, 0
@@ -67,14 +49,8 @@ define i32 @all_true_2_i64(<2 x i64> %v) {
; CHECK-LABEL: all_true_2_i64:
; CHECK: .functype all_true_2_i64 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0
-; CHECK-NEXT: i64x2.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i64x2.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <2 x i64> %v, zeroinitializer
%2 = bitcast <2 x i1> %1 to i2
%3 = icmp eq i2 %2, 0
diff --git a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
index e6497bca98dc2..f7143711394fa 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll
@@ -1086,9 +1086,9 @@ define i1 @test_cmp_v16i8(<16 x i8> %x) {
; CHECK-LABEL: test_cmp_v16i8:
; CHECK: .functype test_cmp_v16i8 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: i8x16.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i8x16.all_true $push0=, $0
+; CHECK-NEXT: i32.const $push1=, 1
+; CHECK-NEXT: i32.xor $push2=, $pop0, $pop1
; CHECK-NEXT: return $pop2
%zero = icmp eq <16 x i8> %x, zeroinitializer
%ret = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %zero)
>From b9667b155b22696ca440d60d6ccb1dc27646d721 Mon Sep 17 00:00:00 2001
From: badumbatish <jjasmine at igalia.com>
Date: Fri, 20 Jun 2025 09:59:18 -0700
Subject: [PATCH 3/3] Use SDPatternMatching and remove truncate...
Use SDPatternMatching and remove truncation. Also added 4xi64 case to
reflect that.
---
.../WebAssembly/WebAssemblyISelLowering.cpp | 24 ++++++++-----------
.../WebAssembly/simd-setcc-reductions.ll | 23 ++++++++++++++++++
2 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index bce8f0e7b84ee..15d4d38fcbe18 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SDPatternMatch.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/DiagnosticInfo.h"
@@ -3243,34 +3244,29 @@ static SDValue performAnyTrueCombine(SDNode *N, SelectionDAG &DAG) {
// any_true (setcc <X>, 0, eq)
// => not (all_true X)
+ using namespace llvm::SDPatternMatch;
+
SDLoc DL(N);
assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
if (N->getConstantOperandVal(0) != Intrinsic::wasm_anytrue)
return SDValue();
- SDValue SetCC = N->getOperand(1);
- if (SetCC.getOpcode() != ISD::SETCC)
+ SDValue LHS;
+ if (!sd_match(N->getOperand(1), m_c_SetCC(m_Value(LHS), m_Zero(),
+ m_SpecificCondCode(ISD::SETEQ))))
return SDValue();
- SDValue LHS = SetCC->getOperand(0);
- SDValue RHS = SetCC->getOperand(1);
- ISD::CondCode Cond = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
EVT LT = LHS.getValueType();
unsigned NumElts = LT.getVectorNumElements();
- if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
- return SDValue();
-
- EVT Width = MVT::getIntegerVT(128 / NumElts);
-
- if (!isNullOrNullSplat(RHS) || Cond != ISD::SETEQ)
+ if (LT.getScalarSizeInBits() > 128 / NumElts)
return SDValue();
SDValue Ret = DAG.getZExtOrTrunc(
DAG.getNode(
ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
- {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
- DAG.getSExtOrTrunc(LHS, DL, LT.changeVectorElementType(Width))}),
+ {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32), LHS}),
DL, MVT::i1);
+
Ret = DAG.getNOT(DL, Ret, MVT::i1);
return DAG.getZExtOrTrunc(Ret, DL, N->getValueType(0));
}
@@ -3437,7 +3433,7 @@ WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::TRUNCATE:
return performTruncateCombine(N, DCI);
case ISD::INTRINSIC_WO_CHAIN: {
- if (auto AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
+ if (SDValue AnyTrueCombine = performAnyTrueCombine(N, DCI.DAG))
return AnyTrueCombine;
return performLowerPartialReduction(N, DCI.DAG);
}
diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
index 1d0a688216765..c6a387c022f22 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
@@ -57,3 +57,26 @@ define i32 @all_true_2_i64(<2 x i64> %v) {
%conv3 = zext i1 %3 to i32
ret i32 %conv3
}
+
+
+define i32 @all_true_4_i64(<4 x i64> %v) {
+; CHECK-LABEL: all_true_4_i64:
+; CHECK: .functype all_true_4_i64 (v128, v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push9=, 0, 0
+; CHECK-NEXT: local.tee $push8=, $2=, $pop9
+; CHECK-NEXT: i64x2.eq $push1=, $0, $pop8
+; CHECK-NEXT: i64x2.eq $push0=, $1, $2
+; CHECK-NEXT: i8x16.shuffle $push2=, $pop1, $pop0, 0, 1, 2, 3, 8, 9, 10, 11, 16, 17, 18, 19, 24, 25, 26, 27
+; CHECK-NEXT: v128.any_true $push3=, $pop2
+; CHECK-NEXT: i32.const $push4=, -1
+; CHECK-NEXT: i32.xor $push5=, $pop3, $pop4
+; CHECK-NEXT: i32.const $push6=, 1
+; CHECK-NEXT: i32.and $push7=, $pop5, $pop6
+; CHECK-NEXT: return $pop7
+ %1 = icmp eq <4 x i64> %v, zeroinitializer
+ %2 = bitcast <4 x i1> %1 to i4
+ %3 = icmp eq i4 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
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