[llvm] AMDGPU: Avoid report_fatal_error for getRegisterByName subtarget case (PR #145173)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 21 08:20:25 PDT 2025
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/145173
None
>From b361700230118e796bb158813faac13e13f544bc Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 22 Jun 2025 00:19:23 +0900
Subject: [PATCH] AMDGPU: Avoid report_fatal_error for getRegisterByName
subtarget case
---
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 6 ++++--
llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll | 4 ++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 3281eabcd4adb..b9023b6d7a3a6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4481,6 +4481,8 @@ SDValue SITargetLowering::lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const {
Register SITargetLowering::getRegisterByName(const char *RegName, LLT VT,
const MachineFunction &MF) const {
+ const Function &Fn = MF.getFunction();
+
Register Reg = StringSwitch<Register>(RegName)
.Case("m0", AMDGPU::M0)
.Case("exec", AMDGPU::EXEC)
@@ -4498,8 +4500,8 @@ Register SITargetLowering::getRegisterByName(const char *RegName, LLT VT,
if (!Subtarget->hasFlatScrRegister() &&
Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
- report_fatal_error(Twine("invalid register \"" + StringRef(RegName) +
- "\" for subtarget."));
+ Fn.getContext().emitError(Twine("invalid register \"" + StringRef(RegName) +
+ "\" for subtarget."));
}
switch (Reg) {
diff --git a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
index 0e9ea0c341cd3..a91bba41bed4f 100644
--- a/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
+++ b/llvm/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll
@@ -1,6 +1,6 @@
-; RUN: not --crash llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s
-; CHECK: invalid register "flat_scratch_lo" for subtarget.
+; CHECK: error: invalid register "flat_scratch_lo" for subtarget.
declare i32 @llvm.read_register.i32(metadata) #0
More information about the llvm-commits
mailing list