[clang] [llvm] [RISCV] Add Support of RISCV Zibimm Experimental Extension (PR #127463)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,48 @@
+//===-- RISCVInstrInfoZibimm.td - 'Zibimm' instructions ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'Zibimm' (branch with imm).
+///
+//===----------------------------------------------------------------------===//
+// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
+def uimm5_zibimm : RISCVOp, ImmLeaf<XLenVT, [{
+    return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1;
+}]> {
+  let ParserMatchClass = UImmAsmOperand<5, "Zibimm">;
+  let EncoderMethod = "getImmOpValueZibimm";
+  let DecoderMethod = "decodeUImmZibimmOperand<5>";
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topperc wrote:

Drop the `<5>`

https://github.com/llvm/llvm-project/pull/127463