[llvm] [PowerPC] eliminate RLWINM instruction following LBARX as possible (PR #144089)

[via llvm-commits]

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@@ -4961,6 +4961,21 @@ bool PPCDAGToDAGISel::tryAsSingleRLWINM(SDNode *N) {
   // If this is just a masked value where the input is not handled, and
   // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
   if (isRunOfOnes(Imm, MB, ME) && Val.getOpcode() != ISD::ROTL) {
+    // The result of LBARX/LHARX do not need to be cleared as the instructions
+    // implicitly clear the upper bits.
+    unsigned AlreadyCleared = 0;
+    if (Val.getOpcode() == ISD::INTRINSIC_W_CHAIN) {
+      auto IntrinsicID = Val.getConstantOperandVal(1);
+      if (IntrinsicID == Intrinsic::ppc_lbarx)
+        AlreadyCleared = 24;
+      else if (IntrinsicID == Intrinsic::ppc_lharx)
+        AlreadyCleared = 16;
+      if (AlreadyCleared != 0 && AlreadyCleared == MB) {
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RolandF77 wrote:

The mask will normally be what is expected, but you haven't proven it is. I don't think there is anything stopping the user from writing atomic_var & my_own_mask, in which case that and and the auto-generated one for data size will likely be merged into one and with a narrower mask by optimization. So I think it's safer to put in an if check even if it is an unusual case.

https://github.com/llvm/llvm-project/pull/144089