[llvm] [AArch64] Match indexed forms of fmul/fmla/fmls (PR #144892)

[Paul Walker via llvm-commits]

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@@ -877,6 +889,46 @@ let Predicates = [HasSVE_or_SME] in {
 
   defm FCMLA_ZZZI : sve_fp_fcmla_by_indexed_elem<"fcmla", int_aarch64_sve_fcmla_lane>;
   defm FMUL_ZZZI   : sve_fp_fmul_by_indexed_elem<"fmul", int_aarch64_sve_fmul_lane>;
+
+  // Fold segmented lane splats in where possible.
+  def : Pat<(nxv8f16 (AArch64fmulidx nxv8f16:$L, nxv8f16:$R, VectorIndexH32b_timm:$Idx)),
+            (FMUL_ZZZI_H $L, $R, $Idx)>;
+  def : Pat<(nxv8f16 (AArch64fmlaidx nxv8f16:$Acc, nxv8f16:$L, nxv8f16:$R, VectorIndexH32b_timm:$Idx)),
+            (FMLA_ZZZI_H $Acc, $L, $R, $Idx)>;
+  def : Pat<(nxv8f16 (AArch64fmlsidx nxv8f16:$Acc, nxv8f16:$L, nxv8f16:$R, VectorIndexH32b_timm:$Idx)),
+            (FMLS_ZZZI_H $Acc, $L, $R, $Idx)>;
+  def : Pat<(nxv4f32 (AArch64fmulidx nxv4f32:$L, nxv4f32:$R, VectorIndexS32b_timm:$Idx)),
+            (FMUL_ZZZI_S $L, $R, $Idx)>;
+  def : Pat<(nxv4f32 (AArch64fmlaidx nxv4f32:$Acc, nxv4f32:$L, nxv4f32:$R, VectorIndexS32b_timm:$Idx)),
+            (FMLA_ZZZI_S $Acc, $L, $R, $Idx)>;
+  def : Pat<(nxv4f32 (AArch64fmlsidx nxv4f32:$Acc, nxv4f32:$L, nxv4f32:$R, VectorIndexS32b_timm:$Idx)),
+            (FMLS_ZZZI_S $Acc, $L, $R, $Idx)>;
+
+  // 64B segmented lane splats currently end up as trn instructions instead.
+  def : Pat<(nxv2f64 (AArch64fmul nxv2f64:$L, (AArch64trn1 nxv2f64:$R, nxv2f64:$R))),
+            (FMUL_ZZZI_D $L, $R, 0)>;
+  def : Pat<(nxv2f64 (AArch64fmul (AArch64trn1 nxv2f64:$R, nxv2f64:$R), nxv2f64:$L)),
+            (FMUL_ZZZI_D $L, $R, 0)>;
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paulwalker-arm wrote:

`fmul` is already marked as commutative so perhaps this is because `AArch64fmul_p` isn't? In which case, does adding `(AArch64fmul_p (SVEAllActive), node:$op2, node:$op1)` to `AArch64fmul` solve the problem?

https://github.com/llvm/llvm-project/pull/144892