[llvm] [X86] combineConcatVectorOps - only always concat logic ops on AVX512 targets (PR #145036)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 20 06:05:11 PDT 2025
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/145036
We should only concat logic ops if at least one operand will freely concatenate. We've now addressed the remaining regressions on AVX2 targets, but still have a number on AVX512 targets which can aggressively use VPTERNLOG in many cases.
>From 5c1a8fef333a78f77f57418bee86d7cb1d634bb8 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 20 Jun 2025 14:04:21 +0100
Subject: [PATCH] [X86] combineConcatVectorOps - only always concat logic ops
on AVX512 targets
We should only concat logic ops if at least one operand will freely concatenate. We've now addressed the remaining regressions on AVX2 targets, but still have a number on AVX512 targets which can aggressively use VPTERNLOG in many cases.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 4 ++--
llvm/test/CodeGen/X86/vector-fshl-256.ll | 26 ++++++++++++------------
llvm/test/CodeGen/X86/vector-fshr-256.ll | 26 ++++++++++++------------
3 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index defb7730b4c7d..085f44e724764 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -58885,7 +58885,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
case ISD::OR:
case ISD::XOR:
case X86ISD::ANDNP:
- // TODO: AVX2+ targets should only use CombineSubOperand like AVX1.
+ // TODO: AVX512 targets should only use CombineSubOperand like AVX1/2.
if (!IsSplat && (VT.is256BitVector() ||
(VT.is512BitVector() && Subtarget.useAVX512Regs()))) {
// Don't concatenate root AVX1 NOT patterns.
@@ -58897,7 +58897,7 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
break;
SDValue Concat0 = CombineSubOperand(VT, Ops, 0);
SDValue Concat1 = CombineSubOperand(VT, Ops, 1);
- if (Concat0 || Concat1 || Subtarget.hasInt256())
+ if (Concat0 || Concat1 || Subtarget.useAVX512Regs())
return DAG.getNode(Opcode, DL, VT,
Concat0 ? Concat0 : ConcatSubOperand(VT, Ops, 0),
Concat1 ? Concat1 : ConcatSubOperand(VT, Ops, 1));
diff --git a/llvm/test/CodeGen/X86/vector-fshl-256.ll b/llvm/test/CodeGen/X86/vector-fshl-256.ll
index c6e1aa9cd90ca..6fbc10307e0bb 100644
--- a/llvm/test/CodeGen/X86/vector-fshl-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshl-256.ll
@@ -739,15 +739,15 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; XOPAVX2-NEXT: vpbroadcastb {{.*#+}} xmm6 = [249,249,249,249,249,249,249,249,249,249,249,249,249,249,249,249]
; XOPAVX2-NEXT: vpaddb %xmm6, %xmm5, %xmm7
; XOPAVX2-NEXT: vpshlb %xmm7, %xmm3, %xmm3
+; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm7
+; XOPAVX2-NEXT: vpshlb %xmm5, %xmm7, %xmm5
+; XOPAVX2-NEXT: vpor %xmm3, %xmm5, %xmm3
; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
; XOPAVX2-NEXT: vpaddb %xmm6, %xmm2, %xmm4
; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
-; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1
-; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
-; XOPAVX2-NEXT: vpshlb %xmm5, %xmm3, %xmm3
; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0
-; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
ret <32 x i8> %res
@@ -1992,17 +1992,17 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,2,3,4,5,6,7,0,7,6,5,4,3,2,1]
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
+; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm4
+; XOPAVX2-NEXT: vpcmpeqd %xmm5, %xmm5, %xmm5
+; XOPAVX2-NEXT: vpshlb %xmm5, %xmm4, %xmm4
+; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm6 = [249,250,251,252,253,254,255,0,249,0,255,254,253,252,251,250]
+; XOPAVX2-NEXT: vpshlb %xmm6, %xmm4, %xmm4
+; XOPAVX2-NEXT: vpor %xmm4, %xmm2, %xmm2
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpshlb %xmm5, %xmm1, %xmm1
+; XOPAVX2-NEXT: vpshlb %xmm6, %xmm1, %xmm1
+; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
-; XOPAVX2-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
-; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
-; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm4 = [249,250,251,252,253,254,255,0,249,0,255,254,253,252,251,250]
-; XOPAVX2-NEXT: vpshlb %xmm4, %xmm2, %xmm2
-; XOPAVX2-NEXT: vpshlb %xmm3, %xmm1, %xmm1
-; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1
-; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <32 x i8> %res
diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll
index 9479174d964cd..b0a1a91bdccc5 100644
--- a/llvm/test/CodeGen/X86/vector-fshr-256.ll
+++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll
@@ -766,18 +766,18 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
; XOPAVX2-NEXT: vpsubb %xmm4, %xmm5, %xmm6
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm7
; XOPAVX2-NEXT: vpshlb %xmm6, %xmm7, %xmm6
+; XOPAVX2-NEXT: vpxor %xmm3, %xmm4, %xmm4
+; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm7
+; XOPAVX2-NEXT: vpaddb %xmm7, %xmm7, %xmm7
+; XOPAVX2-NEXT: vpshlb %xmm4, %xmm7, %xmm4
+; XOPAVX2-NEXT: vpor %xmm6, %xmm4, %xmm4
; XOPAVX2-NEXT: vpsubb %xmm2, %xmm5, %xmm5
; XOPAVX2-NEXT: vpshlb %xmm5, %xmm1, %xmm1
-; XOPAVX2-NEXT: vinserti128 $1, %xmm6, %ymm1, %ymm1
-; XOPAVX2-NEXT: vpxor %xmm3, %xmm4, %xmm4
-; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm5
-; XOPAVX2-NEXT: vpaddb %xmm5, %xmm5, %xmm5
-; XOPAVX2-NEXT: vpshlb %xmm4, %xmm5, %xmm4
; XOPAVX2-NEXT: vpxor %xmm3, %xmm2, %xmm2
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm4, %ymm0, %ymm0
-; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt)
ret <32 x i8> %res
@@ -1793,16 +1793,16 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [0,255,254,253,252,251,250,249,0,249,250,251,252,253,254,255]
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
+; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm4
+; XOPAVX2-NEXT: vpaddb %xmm4, %xmm4, %xmm4
+; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm5 = [7,6,5,4,3,2,1,0,7,0,1,2,3,4,5,6]
+; XOPAVX2-NEXT: vpshlb %xmm5, %xmm4, %xmm4
+; XOPAVX2-NEXT: vpor %xmm2, %xmm4, %xmm2
; XOPAVX2-NEXT: vpshlb %xmm3, %xmm1, %xmm1
-; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
-; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
-; XOPAVX2-NEXT: vpaddb %xmm2, %xmm2, %xmm2
-; XOPAVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [7,6,5,4,3,2,1,0,7,0,1,2,3,4,5,6]
-; XOPAVX2-NEXT: vpshlb %xmm3, %xmm2, %xmm2
; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0
-; XOPAVX2-NEXT: vpshlb %xmm3, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpshlb %xmm5, %xmm0, %xmm0
+; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
-; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
; XOPAVX2-NEXT: retq
%res = call <32 x i8> @llvm.fshr.v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <32 x i8> %res
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