[llvm] cbd4965 - [NFC][AMDGPU] Automate any_extend_vector_inreg.ll check line generation (#145013)
via llvm-commits
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Fri Jun 20 04:17:05 PDT 2025
Author: Chris Jackson
Date: 2025-06-20T12:17:01+01:00
New Revision: cbd496581fb6953a9a8d8387a010cc3a67d4654b
URL: https://github.com/llvm/llvm-project/commit/cbd496581fb6953a9a8d8387a010cc3a67d4654b
DIFF: https://github.com/llvm/llvm-project/commit/cbd496581fb6953a9a8d8387a010cc3a67d4654b.diff
LOG: [NFC][AMDGPU] Automate any_extend_vector_inreg.ll check line generation (#145013)
Convert the test to use update_llc_test_checks.py.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
index 8bcef24c8e23d..cc9f595f9d0b6 100644
--- a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
@@ -1,30 +1,149 @@
-; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
-; GCN-LABEL: {{^}}any_extend_vector_inreg_v16i8_to_v4i32:
-; GCN: s_load_dwordx8
-; GCN-DAG: s_load_dword
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
-; GCN: {{buffer|flat}}_store_byte
define amdgpu_kernel void @any_extend_vector_inreg_v16i8_to_v4i32(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) %arg1) local_unnamed_addr #0 {
+; GFX6-LABEL: any_extend_vector_inreg_v16i8_to_v4i32:
+; GFX6: ; %bb.0: ; %bb
+; GFX6-NEXT: s_load_dwordx4 s[12:15], s[4:5], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v0, 0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s14
+; GFX6-NEXT: s_mov_b32 s1, s15
+; GFX6-NEXT: s_load_dwordx8 s[4:11], s[12:13], 0x0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s4, s[12:13], 0x8
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:13
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:15
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:14
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:8
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:11
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:10
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:4
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:6
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:1
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:3
+; GFX6-NEXT: s_lshr_b32 s8, s9, 16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
+; GFX6-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:9
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
+; GFX6-NEXT: v_alignbit_b32 v0, s8, v0, 16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:12
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0
+; GFX6-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:5
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0 offset:7
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: any_extend_vector_inreg_v16i8_to_v4i32:
+; GFX8: ; %bb.0: ; %bb
+; GFX8-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dword s0, s[8:9], 0x20
+; GFX8-NEXT: s_lshr_b32 s6, s5, 24
+; GFX8-NEXT: s_lshr_b32 s8, s2, 24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshl_b64 s[2:3], s[0:1], 8
+; GFX8-NEXT: s_add_u32 s4, s10, 13
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 15
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 14
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 8
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 11
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 10
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 4
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 6
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 1
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NEXT: s_add_u32 s4, s10, 3
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s10, 9
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NEXT: s_add_u32 s4, s10, 2
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s5, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_add_u32 s0, s10, 5
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s1, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NEXT: s_add_u32 s0, s10, 12
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s1, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: s_add_u32 s0, s10, 7
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_addc_u32 s1, s11, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_endpgm
bb:
%tmp2 = load <16 x i8>, ptr addrspace(1) %arg, align 16
%tmp3 = extractelement <16 x i8> %tmp2, i64 4
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