[compiler-rt] [RISCV] Implement Feature Bit for Q (PR #145001)

[Iris Shi via llvm-commits]

https://github.com/el-ev created https://github.com/llvm/llvm-project/pull/145001

Follow-up of #143436 and https://github.com/riscv-non-isa/riscv-c-api-doc/pull/107.

The corresponding bitmask in `RISCVFeatures.td` has already been updated in #139369.

>From d18fe40a4c982031e3e501165f7be346567016b6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0.0 at owo.li>
Date: Fri, 20 Jun 2025 17:07:10 +0800
Subject: [PATCH] [RISCV] Implement Feature Bits for Q

---
 compiler-rt/lib/builtins/cpu_model/riscv.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 16d55fcfffe75..c02f6e9961ca4 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -40,6 +40,8 @@ struct {
 #define I_BITMASK (1ULL << 8)
 #define M_GROUPID 0
 #define M_BITMASK (1ULL << 12)
+#define Q_GROUPID 0
+#define Q_BITMASK (1ULL << 16)
 #define V_GROUPID 0
 #define V_BITMASK (1ULL << 21)
 #define ZACAS_GROUPID 0