[llvm] [RISCV] Combine (vp.splice (insert_elt poison, scalar, 0), vec, 0, mask, 1, vl) to vslide1up. (PR #144871)

[Ming Yan via llvm-commits]

https://github.com/NexMing updated https://github.com/llvm/llvm-project/pull/144871

>From ef2d94d6146b857364a70fb629c169724c7198b2 Mon Sep 17 00:00:00 2001
From: yanming <ming.yan at terapines.com>
Date: Fri, 20 Jun 2025 11:05:33 +0800
Subject: [PATCH 1/2] Add testcases.

---
 llvm/test/CodeGen/RISCV/rvv/vp-splice.ll | 30 ++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
index a4f91c3e7c99e..80621bbe4b433 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
@@ -286,3 +286,33 @@ define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float>
   %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
   ret <vscale x 2 x float> %v
 }
+
+define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
+; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vmv.s.x v9, a0
+; CHECK-NEXT:    vslidedown.vi v9, v9, 0, v0.t
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
+; CHECK-NEXT:    vslideup.vi v9, v8, 1, v0.t
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+  %va = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
+  %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
+  ret <vscale x 2 x i32> %v
+}
+
+define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
+; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vfmv.s.f v9, fa0
+; CHECK-NEXT:    vslidedown.vi v9, v9, 0, v0.t
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
+; CHECK-NEXT:    vslideup.vi v9, v8, 1, v0.t
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+  %va = insertelement <vscale x 2 x float> poison, float %first, i32 0
+  %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
+  ret <vscale x 2 x float> %v
+}

>From 99bc05d2c74e941c4ece143c824a97dde4785251 Mon Sep 17 00:00:00 2001
From: yanming <ming.yan at terapines.com>
Date: Fri, 20 Jun 2025 11:08:52 +0800
Subject: [PATCH 2/2] [RISCV] Combine (vp.splice (insert_elt poison, scalar,
 0), vec, 0, mask, 1, vl) to vslide1up.

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 33 +++++++++++++++++++++
 llvm/test/CodeGen/RISCV/rvv/vp-splice.ll    | 14 +++------
 2 files changed, 37 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b8ef221742a26..13c010ddac928 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17601,6 +17601,36 @@ static SDValue performFP_TO_INT_SATCombine(SDNode *N,
   return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO);
 }
 
+static SDValue performVSLIDECombine(SDNode *N, SelectionDAG &DAG) {
+  assert((N->getOpcode() == RISCVISD::VSLIDEUP_VL ||
+          N->getOpcode() == RISCVISD::VSLIDEDOWN_VL) &&
+         "Unexpected opcode");
+
+  using namespace SDPatternMatch;
+
+  SDLoc DL(N);
+  SDValue Vec;
+  // (vslideup_vl/vslidedown_vl undef, vec, 0, mask, vl, policy) -> (vec)
+  if (sd_match(N, m_Node(N->getOpcode(), m_Undef(), m_Value(Vec), m_Zero(),
+                         m_Value(), m_Value(), m_Value())))
+    return Vec;
+
+  SDValue FirstEle, Mask, VL;
+  //    (vslideup_vl (insert_ele poison first, 0), vec, 1, mask, vl, policy)
+  // -> (vslide1up_vl/vfslide1up_vl undef, vec, first, mask, vl)
+  if (sd_match(N, m_Node(RISCVISD::VSLIDEUP_VL,
+                         m_InsertElt(m_Poison(), m_Value(FirstEle), m_Zero()),
+                         m_Value(Vec), m_One(), m_Value(Mask), m_Value(VL),
+                         m_Value()))) {
+    EVT VT = Vec.getValueType();
+    return DAG.getNode(VT.isFloatingPoint() ? RISCVISD::VFSLIDE1UP_VL
+                                            : RISCVISD::VSLIDE1UP_VL,
+                       DL, VT, DAG.getUNDEF(VT), Vec, FirstEle, Mask, VL);
+  }
+
+  return SDValue();
+}
+
 // Combine (bitreverse (bswap X)) to the BREV8 GREVI encoding if the type is
 // smaller than XLenVT.
 static SDValue performBITREVERSECombine(SDNode *N, SelectionDAG &DAG,
@@ -19881,6 +19911,9 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
 
     return SDValue();
   }
+  case RISCVISD::VSLIDEUP_VL:
+  case RISCVISD::VSLIDEDOWN_VL:
+    return performVSLIDECombine(N, DAG);
   case ISD::BITREVERSE:
     return performBITREVERSECombine(N, DAG, Subtarget);
   case ISD::FP_TO_SINT:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
index 80621bbe4b433..f0ff6d622cef5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
@@ -290,11 +290,8 @@ define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float>
 define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
 ; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a2, zero, e32, m1, ta, ma
-; CHECK-NEXT:    vmv.s.x v9, a0
-; CHECK-NEXT:    vslidedown.vi v9, v9, 0, v0.t
-; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT:    vslideup.vi v9, v8, 1, v0.t
+; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT:    vslide1up.vx v9, v8, a0, v0.t
 ; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
   %va = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
@@ -305,11 +302,8 @@ define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vsc
 define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
 ; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
-; CHECK-NEXT:    vfmv.s.f v9, fa0
-; CHECK-NEXT:    vslidedown.vi v9, v9, 0, v0.t
-; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu
-; CHECK-NEXT:    vslideup.vi v9, v8, 1, v0.t
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT:    vfslide1up.vf v9, v8, fa0, v0.t
 ; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
   %va = insertelement <vscale x 2 x float> poison, float %first, i32 0