[llvm] dfb5cad - [SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 19 15:12:54 PDT 2025
Author: Koakuma
Date: 2025-06-20T05:12:51+07:00
New Revision: dfb5cadf5e816e542e46d3f0551b6a148a93ce3d
URL: https://github.com/llvm/llvm-project/commit/dfb5cadf5e816e542e46d3f0551b6a148a93ce3d
DIFF: https://github.com/llvm/llvm-project/commit/dfb5cadf5e816e542e46d3f0551b6a148a93ce3d.diff
LOG: [SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
Some SPARC ISA levels and/or extensions are defined in a way such that
the availability of it implies the availability of other, more fundamental
ISA features (for example, targeting 64-bit environment implies that
V9 instructions are available).
Properly set those in the TableGen definitions.
Fixes https://github.com/llvm/llvm-project/issues/142388.
Added:
Modified:
llvm/lib/Target/Sparc/Sparc.td
llvm/lib/Target/Sparc/SparcInstrInfo.td
llvm/test/CodeGen/SPARC/ctlz.ll
llvm/test/CodeGen/SPARC/cttz.ll
llvm/test/CodeGen/SPARC/inlineasm-v9.ll
llvm/test/CodeGen/SPARC/inlineasm.ll
llvm/test/MC/Sparc/Relocations/relocation-specifier.s
llvm/test/MC/Sparc/sparcv9-instructions.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 6e6c887e60e12..8588d2d28b715 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -42,22 +42,28 @@ def FeatureV8Deprecated
"Enable deprecated V8 instructions in V9 mode">;
def FeatureVIS
: SubtargetFeature<"vis", "IsVIS", "true",
- "Enable UltraSPARC Visual Instruction Set extensions">;
+ "Enable UltraSPARC Visual Instruction Set extensions",
+ [FeatureV9]>;
def FeatureVIS2
: SubtargetFeature<"vis2", "IsVIS2", "true",
- "Enable Visual Instruction Set extensions II">;
+ "Enable Visual Instruction Set extensions II",
+ [FeatureV9]>;
def FeatureVIS3
: SubtargetFeature<"vis3", "IsVIS3", "true",
- "Enable Visual Instruction Set extensions III">;
+ "Enable Visual Instruction Set extensions III",
+ [FeatureV9]>;
def FeatureUA2005
: SubtargetFeature<"ua2005", "IsUA2005", "true",
- "Enable UltraSPARC Architecture 2005 extensions">;
+ "Enable UltraSPARC Architecture 2005 extensions",
+ [FeatureV9, FeatureVIS, FeatureVIS2]>;
def FeatureUA2007
: SubtargetFeature<"ua2007", "IsUA2007", "true",
- "Enable UltraSPARC Architecture 2007 extensions">;
+ "Enable UltraSPARC Architecture 2007 extensions",
+ [FeatureV9, FeatureVIS, FeatureVIS2]>;
def FeatureOSA2011
: SubtargetFeature<"osa2011", "IsOSA2011", "true",
- "Enable Oracle SPARC Architecture 2011 extensions">;
+ "Enable Oracle SPARC Architecture 2011 extensions",
+ [FeatureV9, FeatureVIS, FeatureVIS2, FeatureVIS3]>;
def FeatureLeon
: SubtargetFeature<"leon", "IsLeon", "true",
"Enable LEON extensions">;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index 074a04a5dd747..1be017be1c64f 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -24,7 +24,8 @@ include "SparcInstrFormats.td"
def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
// True when generating 64-bit code. This also implies HasV9.
-def Is64Bit : Predicate<"Subtarget->is64Bit()">;
+def Is64Bit : Predicate<"Subtarget->is64Bit()">,
+ AssemblerPredicate<(all_of FeatureV9)>;
def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
AssemblerPredicate<(all_of FeatureSoftMulDiv)>;
diff --git a/llvm/test/CodeGen/SPARC/ctlz.ll b/llvm/test/CodeGen/SPARC/ctlz.ll
index 75930190f5166..f7dc309452b35 100644
--- a/llvm/test/CodeGen/SPARC/ctlz.ll
+++ b/llvm/test/CodeGen/SPARC/ctlz.ll
@@ -207,20 +207,15 @@ define i64 @i64_nopoison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_nopoison:
; SPARC-VIS3: ! %bb.0:
+; SPARC-VIS3-NEXT: srl %o0, 0, %o2
+; SPARC-VIS3-NEXT: lzcnt %o2, %o2
+; SPARC-VIS3-NEXT: add %o2, -32, %o2
+; SPARC-VIS3-NEXT: srl %o1, 0, %o1
+; SPARC-VIS3-NEXT: lzcnt %o1, %o1
+; SPARC-VIS3-NEXT: add %o1, -32, %o1
+; SPARC-VIS3-NEXT: add %o1, 32, %o1
; SPARC-VIS3-NEXT: cmp %o0, 0
-; SPARC-VIS3-NEXT: bne .LBB2_2
-; SPARC-VIS3-NEXT: nop
-; SPARC-VIS3-NEXT: ! %bb.1:
-; SPARC-VIS3-NEXT: srl %o1, 0, %o0
-; SPARC-VIS3-NEXT: lzcnt %o0, %o0
-; SPARC-VIS3-NEXT: add %o0, -32, %o0
-; SPARC-VIS3-NEXT: add %o0, 32, %o1
-; SPARC-VIS3-NEXT: retl
-; SPARC-VIS3-NEXT: mov %g0, %o0
-; SPARC-VIS3-NEXT: .LBB2_2:
-; SPARC-VIS3-NEXT: srl %o0, 0, %o0
-; SPARC-VIS3-NEXT: lzcnt %o0, %o0
-; SPARC-VIS3-NEXT: add %o0, -32, %o1
+; SPARC-VIS3-NEXT: movne %icc, %o2, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %g0, %o0
;
@@ -311,20 +306,15 @@ define i64 @i64_poison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_poison:
; SPARC-VIS3: ! %bb.0:
+; SPARC-VIS3-NEXT: srl %o0, 0, %o2
+; SPARC-VIS3-NEXT: lzcnt %o2, %o2
+; SPARC-VIS3-NEXT: add %o2, -32, %o2
+; SPARC-VIS3-NEXT: srl %o1, 0, %o1
+; SPARC-VIS3-NEXT: lzcnt %o1, %o1
+; SPARC-VIS3-NEXT: add %o1, -32, %o1
+; SPARC-VIS3-NEXT: add %o1, 32, %o1
; SPARC-VIS3-NEXT: cmp %o0, 0
-; SPARC-VIS3-NEXT: bne .LBB3_2
-; SPARC-VIS3-NEXT: nop
-; SPARC-VIS3-NEXT: ! %bb.1:
-; SPARC-VIS3-NEXT: srl %o1, 0, %o0
-; SPARC-VIS3-NEXT: lzcnt %o0, %o0
-; SPARC-VIS3-NEXT: add %o0, -32, %o0
-; SPARC-VIS3-NEXT: add %o0, 32, %o1
-; SPARC-VIS3-NEXT: retl
-; SPARC-VIS3-NEXT: mov %g0, %o0
-; SPARC-VIS3-NEXT: .LBB3_2:
-; SPARC-VIS3-NEXT: srl %o0, 0, %o0
-; SPARC-VIS3-NEXT: lzcnt %o0, %o0
-; SPARC-VIS3-NEXT: add %o0, -32, %o1
+; SPARC-VIS3-NEXT: movne %icc, %o2, %o1
; SPARC-VIS3-NEXT: retl
; SPARC-VIS3-NEXT: mov %g0, %o0
;
diff --git a/llvm/test/CodeGen/SPARC/cttz.ll b/llvm/test/CodeGen/SPARC/cttz.ll
index edabd7d560eda..138f67dbf684a 100644
--- a/llvm/test/CodeGen/SPARC/cttz.ll
+++ b/llvm/test/CodeGen/SPARC/cttz.ll
@@ -254,28 +254,25 @@ define i64 @i64_nopoison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_nopoison:
; SPARC-VIS3: ! %bb.0:
-; SPARC-VIS3-NEXT: cmp %o1, 0
-; SPARC-VIS3-NEXT: bne .LBB2_2
-; SPARC-VIS3-NEXT: nop
-; SPARC-VIS3-NEXT: ! %bb.1:
-; SPARC-VIS3-NEXT: add %o0, -1, %o1
-; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -1, %o2
+; SPARC-VIS3-NEXT: andn %o2, %o0, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
-; SPARC-VIS3-NEXT: ba .LBB2_3
-; SPARC-VIS3-NEXT: mov 64, %o1
-; SPARC-VIS3-NEXT: .LBB2_2:
+; SPARC-VIS3-NEXT: mov 64, %o2
+; SPARC-VIS3-NEXT: sub %o2, %o0, %o2
; SPARC-VIS3-NEXT: add %o1, -1, %o0
; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
-; SPARC-VIS3-NEXT: mov 32, %o1
-; SPARC-VIS3-NEXT: .LBB2_3:
-; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
-; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: mov 32, %o3
+; SPARC-VIS3-NEXT: sub %o3, %o0, %o0
+; SPARC-VIS3-NEXT: cmp %o1, 0
+; SPARC-VIS3-NEXT: movne %icc, %o0, %o2
; SPARC-VIS3-NEXT: mov %g0, %o0
+; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: mov %o2, %o1
;
; SPARC64-LABEL: i64_nopoison:
; SPARC64: ! %bb.0:
@@ -376,28 +373,25 @@ define i64 @i64_poison(i64 %x) nounwind {
;
; SPARC-VIS3-LABEL: i64_poison:
; SPARC-VIS3: ! %bb.0:
-; SPARC-VIS3-NEXT: cmp %o1, 0
-; SPARC-VIS3-NEXT: bne .LBB3_2
-; SPARC-VIS3-NEXT: nop
-; SPARC-VIS3-NEXT: ! %bb.1:
-; SPARC-VIS3-NEXT: add %o0, -1, %o1
-; SPARC-VIS3-NEXT: andn %o1, %o0, %o0
+; SPARC-VIS3-NEXT: add %o0, -1, %o2
+; SPARC-VIS3-NEXT: andn %o2, %o0, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
-; SPARC-VIS3-NEXT: ba .LBB3_3
-; SPARC-VIS3-NEXT: mov 64, %o1
-; SPARC-VIS3-NEXT: .LBB3_2:
+; SPARC-VIS3-NEXT: mov 64, %o2
+; SPARC-VIS3-NEXT: sub %o2, %o0, %o2
; SPARC-VIS3-NEXT: add %o1, -1, %o0
; SPARC-VIS3-NEXT: andn %o0, %o1, %o0
; SPARC-VIS3-NEXT: srl %o0, 0, %o0
; SPARC-VIS3-NEXT: lzcnt %o0, %o0
; SPARC-VIS3-NEXT: add %o0, -32, %o0
-; SPARC-VIS3-NEXT: mov 32, %o1
-; SPARC-VIS3-NEXT: .LBB3_3:
-; SPARC-VIS3-NEXT: sub %o1, %o0, %o1
-; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: mov 32, %o3
+; SPARC-VIS3-NEXT: sub %o3, %o0, %o0
+; SPARC-VIS3-NEXT: cmp %o1, 0
+; SPARC-VIS3-NEXT: movne %icc, %o0, %o2
; SPARC-VIS3-NEXT: mov %g0, %o0
+; SPARC-VIS3-NEXT: retl
+; SPARC-VIS3-NEXT: mov %o2, %o1
;
; SPARC64-LABEL: i64_poison:
; SPARC64: ! %bb.0:
diff --git a/llvm/test/CodeGen/SPARC/inlineasm-v9.ll b/llvm/test/CodeGen/SPARC/inlineasm-v9.ll
index 47126d5d64daa..289bb33fb864b 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm-v9.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm-v9.ll
@@ -58,3 +58,12 @@ Entry:
tail call void asm sideeffect "", "{o0}"(i64 %val)
ret void
}
+
+; CHECK-LABEL: test_twinword:
+; CHECK: rd %pc, %i1
+; CHECK: srlx %i1, 32, %i0
+
+define i64 @test_twinword(){
+ %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"()
+ ret i64 %1
+}
diff --git a/llvm/test/CodeGen/SPARC/inlineasm.ll b/llvm/test/CodeGen/SPARC/inlineasm.ll
index 3ca2168efb71b..07411385bdf37 100644
--- a/llvm/test/CodeGen/SPARC/inlineasm.ll
+++ b/llvm/test/CodeGen/SPARC/inlineasm.ll
@@ -144,15 +144,6 @@ entry:
ret void
}
-; CHECK-LABEL: test_twinword:
-; CHECK: rd %asr5, %i1
-; CHECK: srlx %i1, 32, %i0
-
-define i64 @test_twinword(){
- %1 = tail call i64 asm sideeffect "rd %asr5, ${0:L} \0A\09 srlx ${0:L}, 32, ${0:H}", "={i0}"()
- ret i64 %1
-}
-
; CHECK-LABEL: test_symbol:
; CHECK: ba,a brtarget
define void @test_symbol() {
diff --git a/llvm/test/MC/Sparc/Relocations/relocation-specifier.s b/llvm/test/MC/Sparc/Relocations/relocation-specifier.s
index 1d89babb5e6cd..8a996c99e55ac 100644
--- a/llvm/test/MC/Sparc/Relocations/relocation-specifier.s
+++ b/llvm/test/MC/Sparc/Relocations/relocation-specifier.s
@@ -1,20 +1,21 @@
# RUN: llvm-mc %s -triple=sparc | FileCheck %s --check-prefix=ASM
-# RUN: llvm-mc %s -triple=sparcv9 | FileCheck %s --check-prefix=ASM
+# RUN: llvm-mc %s --defsym V9=1 -triple=sparcv9 | FileCheck %s --check-prefixes=ASM,ASM-V9
# RUN: llvm-mc %s -triple=sparc -filetype=obj -o %t
# RUN: llvm-objdump -dr %t | FileCheck %s --check-prefix=OBJDUMP
-# RUN: llvm-mc %s -triple=sparcv9 -filetype=obj -o %t
-# RUN: llvm-objdump -dr %t | FileCheck %s --check-prefix=OBJDUMP
# RUN: llvm-readelf -s - < %t | FileCheck %s --check-prefix=READELF --implicit-check-not=TLS
+# RUN: llvm-mc %s --defsym V9=1 -triple=sparcv9 -filetype=obj -o %t
+# RUN: llvm-objdump -dr %t | FileCheck %s --check-prefixes=OBJDUMP,OBJDUMP-V9
+# RUN: llvm-readelf -s - < %t | FileCheck %s --check-prefixes=READELF,READELF-V9 --implicit-check-not=TLS
# READELF: TLS LOCAL DEFAULT [[#]] s_tle_hix22
# READELF: TLS LOCAL DEFAULT [[#]] s_tldo_hix22
# READELF: TLS GLOBAL DEFAULT UND s_tle_lox10
-# READELF: TLS GLOBAL DEFAULT UND s_tie_hi22
-# READELF: TLS GLOBAL DEFAULT UND s_tie_lo10
-# READELF: TLS GLOBAL DEFAULT UND s_tie_ld
-# READELF: TLS GLOBAL DEFAULT UND s_tie_ldx
-# READELF: TLS GLOBAL DEFAULT UND s_tie_add
+# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_hi22
+# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_lo10
+# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_ld
+# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_ldx
+# READELF-V9: TLS GLOBAL DEFAULT UND s_tie_add
# READELF: TLS GLOBAL DEFAULT UND s_tldm_hi22
# READELF: TLS GLOBAL DEFAULT UND s_tldm_lo10
# READELF: TLS GLOBAL DEFAULT UND s_tldm_add
@@ -72,23 +73,24 @@ or %g1, %hm(sym), %g3
or %g1, %ulo(sym), %g3
sethi %lm(sym), %l0
-# ASM: sethi %hix(sym), %g1
-# ASM-NEXT: xor %g1, %lox(sym), %g1
-# ASM-NEXT: sethi %gdop_hix22(sym), %l1
-# ASM-NEXT: or %l1, %gdop_lox10(sym), %l1
-# ASM-NEXT: ldx [%l7+%l1], %l2, %gdop(sym)
-# OBJDUMP: sethi 0x3fffff, %g0
-# OBJDUMP-NEXT: xor %g0, -0x400, %g0
-# OBJDUMP-NEXT: sethi 0x0, %g1
-# OBJDUMP-NEXT: R_SPARC_HIX22 sym
-# OBJDUMP-NEXT: xor %g1, 0x0, %g1
-# OBJDUMP-NEXT: R_SPARC_LOX10 sym
-# OBJDUMP-NEXT: sethi 0x0, %l1
-# OBJDUMP-NEXT: R_SPARC_GOTDATA_OP_HIX22 sym
-# OBJDUMP-NEXT: or %l1, 0x0, %l1
-# OBJDUMP-NEXT: R_SPARC_GOTDATA_OP_LOX10 sym
-# OBJDUMP-NEXT: ldx [%l7+%l1], %l2
-# OBJDUMP-NEXT: R_SPARC_GOTDATA_OP sym
+.ifdef V9
+# ASM-V9: sethi %hix(sym), %g1
+# ASM-V9-NEXT: xor %g1, %lox(sym), %g1
+# ASM-V9-NEXT: sethi %gdop_hix22(sym), %l1
+# ASM-V9-NEXT: or %l1, %gdop_lox10(sym), %l1
+# ASM-V9-NEXT: ldx [%l7+%l1], %l2, %gdop(sym)
+# OBJDUMP-V9: sethi 0x3fffff, %g0
+# OBJDUMP-V9-NEXT: xor %g0, -0x400, %g0
+# OBJDUMP-V9-NEXT: sethi 0x0, %g1
+# OBJDUMP-V9-NEXT: R_SPARC_HIX22 sym
+# OBJDUMP-V9-NEXT: xor %g1, 0x0, %g1
+# OBJDUMP-V9-NEXT: R_SPARC_LOX10 sym
+# OBJDUMP-V9-NEXT: sethi 0x0, %l1
+# OBJDUMP-V9-NEXT: R_SPARC_GOTDATA_OP_HIX22 sym
+# OBJDUMP-V9-NEXT: or %l1, 0x0, %l1
+# OBJDUMP-V9-NEXT: R_SPARC_GOTDATA_OP_LOX10 sym
+# OBJDUMP-V9-NEXT: ldx [%l7+%l1], %l2
+# OBJDUMP-V9-NEXT: R_SPARC_GOTDATA_OP sym
sethi %hix(zero), %g0
xor %g0, %lox(zero), %g0
sethi %hix(sym), %g1
@@ -96,6 +98,7 @@ xor %g1, %lox(sym), %g1
sethi %gdop_hix22(sym), %l1
or %l1, %gdop_lox10(sym), %l1
ldx [%l7 + %l1], %l2, %gdop(sym)
+.endif
.set abs, 0xfedcba98
.set abs48, 0xfedcba987654
@@ -147,23 +150,25 @@ xor %o0, %lox(abs), %o0
sethi %tle_hix22(s_tle_hix22), %i0
xor %i0, %tle_lox10(s_tle_lox10), %i0
+.ifdef V9
## Initial Executable model
-# ASM: sethi %tie_hi22(s_tie_hi22), %i1
-# ASM-NEXT: add %i1, %tie_lo10(s_tie_lo10), %i1
-# ASM-NEXT: ld [%i0+%i1], %i0, %tie_ld(s_tie_ld)
-# ASM-NEXT: ldx [%i0+%i1], %i0, %tie_ldx(s_tie_ldx)
-# ASM-NEXT: add %g7, %i0, %o0, %tie_add(s_tie_add)
-
-# OBJDUMP: R_SPARC_TLS_IE_HI22 s_tie_hi22
-# OBJDUMP: R_SPARC_TLS_IE_LO10 s_tie_lo10
-# OBJDUMP: R_SPARC_TLS_IE_LD s_tie_ld
-# OBJDUMP: R_SPARC_TLS_IE_LDX s_tie_ldx
-# OBJDUMP: R_SPARC_TLS_IE_ADD s_tie_add
+# ASM-V9: sethi %tie_hi22(s_tie_hi22), %i1
+# ASM-V9-NEXT: add %i1, %tie_lo10(s_tie_lo10), %i1
+# ASM-V9-NEXT: ld [%i0+%i1], %i0, %tie_ld(s_tie_ld)
+# ASM-V9-NEXT: ldx [%i0+%i1], %i0, %tie_ldx(s_tie_ldx)
+# ASM-V9-NEXT: add %g7, %i0, %o0, %tie_add(s_tie_add)
+
+# OBJDUMP-V9: R_SPARC_TLS_IE_HI22 s_tie_hi22
+# OBJDUMP-V9: R_SPARC_TLS_IE_LO10 s_tie_lo10
+# OBJDUMP-V9: R_SPARC_TLS_IE_LD s_tie_ld
+# OBJDUMP-V9: R_SPARC_TLS_IE_LDX s_tie_ldx
+# OBJDUMP-V9: R_SPARC_TLS_IE_ADD s_tie_add
sethi %tie_hi22(s_tie_hi22), %i1
add %i1, %tie_lo10(s_tie_lo10), %i1
ld [%i0+%i1], %i0, %tie_ld(s_tie_ld)
ldx [%i0+%i1], %i0, %tie_ldx(s_tie_ldx)
add %g7, %i0, %o0, %tie_add(s_tie_add)
+.endif
## Local Dynamic model
# ASM: sethi %tldo_hix22(s_tldo_hix22), %i1
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
index de9fe03201b19..6dd0dc3d64e0a 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -53,14 +53,19 @@
! V9: lda [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0x86,0x10,0x76]
lduwa [%i0 + %l6] (130+1), %o2
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldsw [%i0+%l6], %o2 ! encoding: [0xd4,0x46,0x00,0x16]
ldsw [%i0 + %l6], %o2
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldsw [%i0+32], %o2 ! encoding: [0xd4,0x46,0x20,0x20]
ldsw [%i0 + 32], %o2
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldsw [%g1], %o2 ! encoding: [0xd4,0x40,0x40,0x00]
ldsw [%g1], %o2
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldswa [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0xc6,0x10,0x76]
ldswa [%i0 + %l6] 131, %o2
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldswa [%i0+%l6] #ASI_SNF, %o2 ! encoding: [0xd4,0xc6,0x10,0x76]
ldswa [%i0 + %l6] (130+1), %o2
@@ -121,8 +126,10 @@
! V9: ldx [%g2+%i5], %fsr ! encoding: [0xc3,0x08,0x80,0x1d]
ldx [%g2 + %i5],%fsr
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldxa [%g2+%i5] #ASI_SNF, %g0 ! encoding: [0xc0,0xd8,0x90,0x7d]
ldxa [%g2 + %i5] 131, %g0
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldxa [%g2+%i5] #ASI_SNF, %g0 ! encoding: [0xc0,0xd8,0x90,0x7d]
ldxa [%g2 + %i5] (130+1), %g0
@@ -134,8 +141,10 @@
! V9: stx %fsr, [%g2+%i5] ! encoding: [0xc3,0x28,0x80,0x1d]
stx %fsr,[%g2 + %i5]
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d]
stxa %g0, [%g2 + %i5] 131
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d]
stxa %g0, [%g2 + %i5] (130+1)
@@ -398,33 +407,45 @@
! V9: wr %i0, 1, %asr21 ! encoding: [0xab,0x86,0x20,0x01]
wr %i0, 1, %clear_softint
+ ! V8: [[#@LINE+2]]:9: error: invalid instruction mnemonic
! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00]
stw %o1, [%o0]
+ ! V8: [[#@LINE+2]]:9: error: invalid instruction mnemonic
! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00]
stuw %o1, [%o0]
+ ! V8: [[#@LINE+2]]:9: error: invalid instruction mnemonic
! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00]
stsw %o1, [%o0]
+ ! V8: [[#@LINE+2]]:9: error: invalid instruction mnemonic
! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
stwa %o2, [%i0 + %l6] 131
+ ! V8: [[#@LINE+2]]:9: error: invalid instruction mnemonic
! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
stuwa %o2, [%i0 + %l6] 131
+ ! V8: [[#@LINE+2]]:9: error: invalid instruction mnemonic
! V9: sta %o2, [%i0+%l6] #ASI_SNF ! encoding: [0xd4,0xa6,0x10,0x76]
stswa %o2, [%i0 + %l6] 131
!! SPARCv9 provides a new variant of ASI-tagged memory accesses.
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldxa [%g2] %asi, %g0 ! encoding: [0xc0,0xd8,0xa0,0x00]
ldxa [%g2] %asi, %g0
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: stxa %g0, [%g2] %asi ! encoding: [0xc0,0xf0,0xa0,0x00]
stxa %g0, [%g2] %asi
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldxa [%g2+5] %asi, %g0 ! encoding: [0xc0,0xd8,0xa0,0x05]
ldxa [%g2 + 5] %asi, %g0
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: stxa %g0, [%g2+5] %asi ! encoding: [0xc0,0xf0,0xa0,0x05]
stxa %g0, [%g2 + 5] %asi
!! Also make sure named ASI tags are parsed properly.
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: ldxa [%g2+%i5] #ASI_SNF, %g0 ! encoding: [0xc0,0xd8,0x90,0x7d]
ldxa [%g2 + %i5] #ASI_SNF, %g0
+ ! V8: [[#@LINE+2]]:9: error: instruction requires a CPU feature not currently enabled
! V9: stxa %g0, [%g2+%i5] #ASI_SNF ! encoding: [0xc0,0xf0,0x90,0x7d]
stxa %g0, [%g2 + %i5] #ASI_SNF
More information about the llvm-commits
mailing list