[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #144620)

[Sam Elliott via llvm-commits]

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@@ -0,0 +1,31 @@
+# RUN: %clang --target=fuchsia-elf-riscv32 -march=rv32g_zclsd_zilsd %s -nostdlib -o %t
+# RUN: llvm-objdump -d %t | FileCheck %s
+
+# CHECK: 00001000 <_start>:
+# CHECK-NEXT:     1000: 00000517     	auipc	a0, 0x0
+# CHECK-NEXT:     1004: 0559         	addi	a0, a0, 0x16 <target>
+# CHECK-NEXT:     1006: 00000517     	auipc	a0, 0x0
+# CHECK-NEXT:     100a: 6910         	ld	a2, 0x10(a0) <target>
+# CHECK-NEXT:     100c: 00000517     	auipc	a0, 0x0
+# CHECK-NEXT:     1010: 00c53523     	sd	a2, 0xa(a0) <target>
+# CHECK-NEXT:     1014: 0000         	unimp
+
+# the structure of this test file is similar to that of riscv64-ar-coverage
+# with the major difference being that these tests are focused on instructions
+# for 32 bit architecture
+
+.global _start
+.text
+_start:
+  auipc a0, 0x0
+  addi a0, a0, 0x16   # addi -- behavior changes with differentr architectures
----------------
lenary wrote:

```suggestion
  addi a0, a0, 0x16   # addi -- behavior changes with different architectures
```

https://github.com/llvm/llvm-project/pull/144620