[llvm] [llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (PR #142529)
Lakshay Kumar via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 19 09:31:13 PDT 2025
https://github.com/lakshayk-nv updated https://github.com/llvm/llvm-project/pull/142529
>From b1919dde1492495ed8bf53d852deabc3808c41df Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Fri, 30 May 2025 06:43:53 -0700
Subject: [PATCH 01/11] [llvm-exegesis] [AArch64] Resolve " Not all operands
were initialized by the snippet generator" by omit OPERAND_UNKNOWN to
Immediate
---
.../llvm-exegesis/lib/AArch64/Target.cpp | 22 +++++++++++++++++++
.../llvm-exegesis/lib/SnippetGenerator.cpp | 6 +++++
2 files changed, 28 insertions(+)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index a1eb5a46f21fc..d768673944bd4 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -162,6 +162,10 @@ class ExegesisAArch64Target : public ExegesisTarget {
ExegesisAArch64Target()
: ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
+ Error randomizeTargetMCOperand(
+ const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+ const BitVector &ForbiddenRegs) const override;
+
private:
std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
const APInt &Value) const override {
@@ -229,6 +233,24 @@ class ExegesisAArch64Target : public ExegesisTarget {
}
};
+Error ExegesisAArch64Target::randomizeTargetMCOperand(
+ const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+ const BitVector &ForbiddenRegs) const {
+ unsigned Opcode = Instr.getOpcode();
+ switch (Opcode) {
+ case AArch64::MOVIv2s_msl:
+ case AArch64::MOVIv4s_msl:
+ case AArch64::MVNIv2s_msl:
+ case AArch64::MVNIv4s_msl:
+ AssignedValue = MCOperand::createImm(8); // or 16, as needed
+ break;
+ default:
+ AssignedValue = MCOperand::createImm(0);
+ break;
+ }
+ return Error::success();
+}
+
} // namespace
static ExegesisTarget *getTheExegesisAArch64Target() {
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index 04064ae1d8441..de2bc4d54d1d5 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -276,6 +276,12 @@ static Error randomizeMCOperand(const LLVMState &State,
AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
break;
}
+ /// Omit unknown operands to default immediate value based on the instruction
+#ifdef __aarch64__
+ case MCOI::OperandType::OPERAND_UNKNOWN:
+ return State.getExegesisTarget().randomizeTargetMCOperand(
+ Instr, Var, AssignedValue, ForbiddenRegs);
+#endif
default:
break;
}
>From af68e0ff850d0ff5b2a8e517145a99421cd6fb9e Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Sun, 1 Jun 2025 11:52:13 -0700
Subject: [PATCH 02/11] [llvm-exegesis] [AArch64] Include OPERAND_PCREL operand
handling in snippet generation, omiting immediate valued 0.
---
.../llvm-exegesis/lib/AArch64/Target.cpp | 32 ++++++++++++-------
.../llvm-exegesis/lib/SnippetGenerator.cpp | 4 ++-
2 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index d768673944bd4..4e8150ae79ee8 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -236,19 +236,29 @@ class ExegesisAArch64Target : public ExegesisTarget {
Error ExegesisAArch64Target::randomizeTargetMCOperand(
const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
const BitVector &ForbiddenRegs) const {
- unsigned Opcode = Instr.getOpcode();
- switch (Opcode) {
- case AArch64::MOVIv2s_msl:
- case AArch64::MOVIv4s_msl:
- case AArch64::MVNIv2s_msl:
- case AArch64::MVNIv4s_msl:
- AssignedValue = MCOperand::createImm(8); // or 16, as needed
- break;
- default:
+ const Operand &Op = Instr.getPrimaryOperand(Var);
+ switch (Op.getExplicitOperandInfo().OperandType) {
+ case MCOI::OperandType::OPERAND_UNKNOWN: {
+ unsigned Opcode = Instr.getOpcode();
+ switch (Opcode) {
+ case AArch64::MOVIv2s_msl:
+ case AArch64::MOVIv4s_msl:
+ case AArch64::MVNIv2s_msl:
+ case AArch64::MVNIv4s_msl:
+ AssignedValue = MCOperand::createImm(8); // or 16, as needed
+ break;
+ default:
+ AssignedValue = MCOperand::createImm(0);
+ break;
+ }
+ return Error::success();
+ }
+ case MCOI::OperandType::OPERAND_PCREL:
AssignedValue = MCOperand::createImm(0);
- break;
+ return Error::success();
+ default:
+ llvm_unreachable("Unexpected operand type in randomizeTargetMCOperand");
}
- return Error::success();
}
} // namespace
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index de2bc4d54d1d5..fef2c0f6077dc 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -276,9 +276,11 @@ static Error randomizeMCOperand(const LLVMState &State,
AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
break;
}
- /// Omit unknown operands to default immediate value based on the instruction
+ /// Omit unknown and pc-relative operands to imm value based on the instruction
+ // TODO: Is aarch64 gaurd neccessary ?
#ifdef __aarch64__
case MCOI::OperandType::OPERAND_UNKNOWN:
+ case MCOI::OperandType::OPERAND_PCREL:
return State.getExegesisTarget().randomizeTargetMCOperand(
Instr, Var, AssignedValue, ForbiddenRegs);
#endif
>From 5697760a959d24cd83a43830ebcb0365b9cae730 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Sun, 1 Jun 2025 23:00:27 -0700
Subject: [PATCH 03/11] [llvm-exegesis] [AArch64] WIP. Introduce handling for
OPERAND_FIRST_TARGET.
---
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 4e8150ae79ee8..c152122171949 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -256,6 +256,9 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
case MCOI::OperandType::OPERAND_PCREL:
AssignedValue = MCOperand::createImm(0);
return Error::success();
+ case MCOI::OperandType::OPERAND_FIRST_TARGET:
+ AssignedValue = MCOperand::createImm(0);
+ return Error::success();
default:
llvm_unreachable("Unexpected operand type in randomizeTargetMCOperand");
}
>From 75c2e65b11f90528914f9938bbf49dbd033567c4 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Sun, 1 Jun 2025 23:01:28 -0700
Subject: [PATCH 04/11] [llvm-exegesis] [AArch64] Explore opcode-specific
immediate values for omitted opcode type.
---
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index c152122171949..38c3bafb88952 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -237,6 +237,8 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
const BitVector &ForbiddenRegs) const {
const Operand &Op = Instr.getPrimaryOperand(Var);
+ // Introducing some illegal instructions for (15) a few opcodes
+ // TODO: Look into immediate values to be opcode specific
switch (Op.getExplicitOperandInfo().OperandType) {
case MCOI::OperandType::OPERAND_UNKNOWN: {
unsigned Opcode = Instr.getOpcode();
>From 9d425dc4f9f8053b7b969c0f35395a8905273155 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Mon, 2 Jun 2025 03:06:06 -0700
Subject: [PATCH 05/11] [llvm-exegesis] [AArch64] Refactor operand handling in
randomizeTargetMCOperand.
---
.../llvm-exegesis/lib/AArch64/Target.cpp | 46 ++++++++++---------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 38c3bafb88952..8fc5feded832b 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -237,33 +237,35 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
const BitVector &ForbiddenRegs) const {
const Operand &Op = Instr.getPrimaryOperand(Var);
+ const auto OperandType = Op.getExplicitOperandInfo().OperandType;
// Introducing some illegal instructions for (15) a few opcodes
// TODO: Look into immediate values to be opcode specific
- switch (Op.getExplicitOperandInfo().OperandType) {
- case MCOI::OperandType::OPERAND_UNKNOWN: {
- unsigned Opcode = Instr.getOpcode();
- switch (Opcode) {
- case AArch64::MOVIv2s_msl:
- case AArch64::MOVIv4s_msl:
- case AArch64::MVNIv2s_msl:
- case AArch64::MVNIv4s_msl:
- AssignedValue = MCOperand::createImm(8); // or 16, as needed
- break;
- default:
+ switch (OperandType) {
+ case MCOI::OperandType::OPERAND_UNKNOWN: {
+ unsigned Opcode = Instr.getOpcode();
+ switch (Opcode) {
+ case AArch64::MOVIv2s_msl:
+ case AArch64::MOVIv4s_msl:
+ case AArch64::MVNIv2s_msl:
+ case AArch64::MVNIv4s_msl:
+ AssignedValue = MCOperand::createImm(8); // or 16, as needed
+ return Error::success();
+ default:
+ AssignedValue = MCOperand::createImm(0);
+ return Error::success();
+ }
+ }
+ case MCOI::OperandType::OPERAND_PCREL:
+ case MCOI::OperandType::OPERAND_FIRST_TARGET:
AssignedValue = MCOperand::createImm(0);
+ return Error::success();
+ default:
break;
- }
- return Error::success();
- }
- case MCOI::OperandType::OPERAND_PCREL:
- AssignedValue = MCOperand::createImm(0);
- return Error::success();
- case MCOI::OperandType::OPERAND_FIRST_TARGET:
- AssignedValue = MCOperand::createImm(0);
- return Error::success();
- default:
- llvm_unreachable("Unexpected operand type in randomizeTargetMCOperand");
}
+
+ return make_error<Failure>(
+ Twine("Unimplemented operand type: MCOI::OperandType:")
+ .concat(Twine(static_cast<int>(OperandType))));
}
} // namespace
>From 9a1feb2d99b4dc9bd5cea7f6ea117bb21d3d72bb Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Mon, 2 Jun 2025 22:28:44 -0700
Subject: [PATCH 06/11] [llvm-exegesis] [AArch64] Update comments for operand
handling and remove out of scope operand type.
---
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 1 -
llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 8fc5feded832b..285d888770a53 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -256,7 +256,6 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
}
}
case MCOI::OperandType::OPERAND_PCREL:
- case MCOI::OperandType::OPERAND_FIRST_TARGET:
AssignedValue = MCOperand::createImm(0);
return Error::success();
default:
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index fef2c0f6077dc..d4381c3b123f0 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -277,7 +277,7 @@ static Error randomizeMCOperand(const LLVMState &State,
break;
}
/// Omit unknown and pc-relative operands to imm value based on the instruction
- // TODO: Is aarch64 gaurd neccessary ?
+ // TODO: Neccesity of AArch64 guard ?
#ifdef __aarch64__
case MCOI::OperandType::OPERAND_UNKNOWN:
case MCOI::OperandType::OPERAND_PCREL:
>From f56787028235b5328ea5dc3a20637532a1db4c68 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Tue, 3 Jun 2025 00:58:47 -0700
Subject: [PATCH 07/11] [llvm-exegesis] [AArch64] Format changes.
---
.../llvm-exegesis/lib/AArch64/Target.cpp | 40 +++++++++----------
.../llvm-exegesis/lib/SnippetGenerator.cpp | 3 +-
2 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 285d888770a53..8ee7983f87731 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -162,9 +162,9 @@ class ExegesisAArch64Target : public ExegesisTarget {
ExegesisAArch64Target()
: ExegesisTarget(AArch64CpuPfmCounters, AArch64_MC::isOpcodeAvailable) {}
- Error randomizeTargetMCOperand(
- const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
- const BitVector &ForbiddenRegs) const override;
+ Error randomizeTargetMCOperand(const Instruction &Instr, const Variable &Var,
+ MCOperand &AssignedValue,
+ const BitVector &ForbiddenRegs) const override;
private:
std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, MCRegister Reg,
@@ -241,25 +241,25 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
// Introducing some illegal instructions for (15) a few opcodes
// TODO: Look into immediate values to be opcode specific
switch (OperandType) {
- case MCOI::OperandType::OPERAND_UNKNOWN: {
- unsigned Opcode = Instr.getOpcode();
- switch (Opcode) {
- case AArch64::MOVIv2s_msl:
- case AArch64::MOVIv4s_msl:
- case AArch64::MVNIv2s_msl:
- case AArch64::MVNIv4s_msl:
- AssignedValue = MCOperand::createImm(8); // or 16, as needed
- return Error::success();
- default:
- AssignedValue = MCOperand::createImm(0);
- return Error::success();
- }
- }
- case MCOI::OperandType::OPERAND_PCREL:
- AssignedValue = MCOperand::createImm(0);
+ case MCOI::OperandType::OPERAND_UNKNOWN: {
+ unsigned Opcode = Instr.getOpcode();
+ switch (Opcode) {
+ case AArch64::MOVIv2s_msl:
+ case AArch64::MOVIv4s_msl:
+ case AArch64::MVNIv2s_msl:
+ case AArch64::MVNIv4s_msl:
+ AssignedValue = MCOperand::createImm(8); // or 16, as needed
return Error::success();
default:
- break;
+ AssignedValue = MCOperand::createImm(0);
+ return Error::success();
+ }
+ }
+ case MCOI::OperandType::OPERAND_PCREL:
+ AssignedValue = MCOperand::createImm(0);
+ return Error::success();
+ default:
+ break;
}
return make_error<Failure>(
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index d4381c3b123f0..6859a9d496250 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -276,7 +276,8 @@ static Error randomizeMCOperand(const LLVMState &State,
AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
break;
}
- /// Omit unknown and pc-relative operands to imm value based on the instruction
+ /// Omit unknown and pc-relative operands to imm value based on the
+ /// instruction
// TODO: Neccesity of AArch64 guard ?
#ifdef __aarch64__
case MCOI::OperandType::OPERAND_UNKNOWN:
>From 66fdd3973e378b199348e9d7de2043ef1785421f Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Tue, 3 Jun 2025 07:35:58 -0700
Subject: [PATCH 08/11] [llvm-exegesis] [AArch64] Remove unneccessary AArch64
guard
---
llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp | 3 ---
1 file changed, 3 deletions(-)
diff --git a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
index 6859a9d496250..156739bd9de34 100644
--- a/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+++ b/llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
@@ -278,13 +278,10 @@ static Error randomizeMCOperand(const LLVMState &State,
}
/// Omit unknown and pc-relative operands to imm value based on the
/// instruction
- // TODO: Neccesity of AArch64 guard ?
-#ifdef __aarch64__
case MCOI::OperandType::OPERAND_UNKNOWN:
case MCOI::OperandType::OPERAND_PCREL:
return State.getExegesisTarget().randomizeTargetMCOperand(
Instr, Var, AssignedValue, ForbiddenRegs);
-#endif
default:
break;
}
>From 59452e553938b59c1897a551a709da14ce0612b9 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Wed, 11 Jun 2025 08:44:16 -0700
Subject: [PATCH 09/11] [llvm-exegesis] [AArch64] Add handling for
OPERAND_FIRST_TARGET in randomizeTargetMCOperand to omit to Immediate
---
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 8ee7983f87731..4aa4b60815de7 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -248,7 +248,7 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
case AArch64::MOVIv4s_msl:
case AArch64::MVNIv2s_msl:
case AArch64::MVNIv4s_msl:
- AssignedValue = MCOperand::createImm(8); // or 16, as needed
+ AssignedValue = MCOperand::createImm(8); // or 16
return Error::success();
default:
AssignedValue = MCOperand::createImm(0);
@@ -256,6 +256,7 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
}
}
case MCOI::OperandType::OPERAND_PCREL:
+ case MCOI::OperandType::OPERAND_FIRST_TARGET:
AssignedValue = MCOperand::createImm(0);
return Error::success();
default:
>From 1726beaed75c7bc7427ea5f92f7078d941f494b4 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Wed, 11 Jun 2025 08:49:23 -0700
Subject: [PATCH 10/11] [llvm-exegesis] [AArch64] Documenting opcodes requiring
some specific omittion to resolve illegal instruction
---
llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
index 4aa4b60815de7..fe6703f7ffd3f 100644
--- a/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp
@@ -238,8 +238,8 @@ Error ExegesisAArch64Target::randomizeTargetMCOperand(
const BitVector &ForbiddenRegs) const {
const Operand &Op = Instr.getPrimaryOperand(Var);
const auto OperandType = Op.getExplicitOperandInfo().OperandType;
- // Introducing some illegal instructions for (15) a few opcodes
- // TODO: Look into immediate values to be opcode specific
+ // TODO: Look into immediate values to be opcode specific for
+ // MRS, MSR, MSRpstatesvcrImm1, SYSLxt, SYSxt, UDF (illegal instruction)
switch (OperandType) {
case MCOI::OperandType::OPERAND_UNKNOWN: {
unsigned Opcode = Instr.getOpcode();
>From c26aa00fff88807a6fc8d69d21f1ca44db161310 Mon Sep 17 00:00:00 2001
From: lakshayk-nv <lakshayk at nvidia.com>
Date: Mon, 16 Jun 2025 08:12:15 -0700
Subject: [PATCH 11/11] [llvm-exegesis] [AArch64] Add tests for operand
omission scenarios in error-resolution.s
---
.../llvm-exegesis/AArch64/error-resolution.s | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
diff --git a/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
new file mode 100644
index 0000000000000..35ad6e870e1b1
--- /dev/null
+++ b/llvm/test/tools/llvm-exegesis/AArch64/error-resolution.s
@@ -0,0 +1,82 @@
+# REQUIRES: aarch64-registered-target
+
+
+
+// Test for omitting OperandType::OPERAND_UNKNOWN
+
+// ADDXri: ADD Xd, Xn, #imm{, shift}
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_latency
+# ADDXri_latency-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode
+# ADDXri_latency: ---
+# ADDXri_latency-NEXT: mode: latency
+# ADDXri_latency-NEXT: key:
+# ADDXri_latency-NEXT: instructions:
+# ADDXri_latency-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0
+# ADDXri_latency: ...
+
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=ADDXri 2>&1 | FileCheck %s --check-prefix=ADDXri_throughput
+# ADDXri_throughput-NOT: Not all operands were initialized by the snippet generator for ADDXri opcode
+# ADDXri_throughput: ---
+# ADDXri_throughput-NEXT: mode: inverse_throughput
+# ADDXri_throughput-NEXT: key:
+# ADDXri_throughput-NEXT: instructions:
+# ADDXri_throughput-NEXT: ADDXri [[REG1:X[0-9]+|LR]] [[REG2:X[0-9]+|LR]] i_0x0 i_0x0
+# ADDXri_throughput: ...
+
+// MOVIv2s_msl: MOVI vd, #imm{, shift}
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_latency
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=MOVIv2s_msl 2>&1 | FileCheck %s --check-prefix=MOVIv2s_msl_throughput
+# MOVIv2s_msl_latency-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode
+
+// TODO: Update this test when serial execution strategy is added
+# MOVIv2s_msl_latency: MOVIv2s_msl: No strategy found to make the execution serial
+
+
+# MOVIv2s_msl_throughput-NOT: Not all operands were initialized by the snippet generator for MOVIv2s_msl opcode
+# MOVIv2s_msl_throughput: ---
+# MOVIv2s_msl_throughput-NEXT: mode: inverse_throughput
+# MOVIv2s_msl_throughput-NEXT: key:
+# MOVIv2s_msl_throughput-NEXT: instructions:
+# MOVIv2s_msl_throughput-NEXT: MOVIv2s_msl [[REG1:D[0-9]+|LR]] i_0x1 i_0x8
+# MOVIv2s_msl_throughput: ...
+
+
+
+// Test for omitting OperandType::OPERAND_PCREL
+// LDRDl: LDRD ldr1, ldr2, [pc, #imm]
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_latency
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=LDRDl 2>&1 | FileCheck %s --check-prefix=LDRDl_throughput
+
+# LDRDl_latency-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes
+# LDRDl_throughput-NOT: Not all operands were initialized by the snippet generator for LDRDl opcodes
+
+# LDRDl_throughput: ---
+# LDRDl_throughput-NEXT: mode: inverse_throughput
+# LDRDl_throughput-NEXT: key:
+# LDRDl_throughput-NEXT: instructions:
+# LDRDl_throughput-NEXT: LDRDl [[REG1:D[0-9]+|LR]] i_0x0
+# LDRDl_throughput: ...
+
+
+
+// Test for omitting OperandType::OPERAND_FIRST_TARGET
+
+// UMOVvi16_idx0: UMOV wd, vn.h[index]
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=latency --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_latency
+# RUN: llvm-exegesis --mtriple=aarch64 --mcpu=neoverse-v2 --mode=inverse_throughput --benchmark-phase=prepare-and-assemble-snippet --opcode-name=UMOVvi16_idx0 2>&1 | FileCheck %s --check-prefix=UMOVvi16_idx0_throughput
+
+# UMOVvi16_idx0_latency-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode
+# UMOVvi16_idx0_latency: ---
+# UMOVvi16_idx0_latency-NEXT: mode: latency
+# UMOVvi16_idx0_latency-NEXT: key:
+# UMOVvi16_idx0_latency-NEXT: instructions:
+# UMOVvi16_idx0_latency-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0
+# UMOVvi16_idx0_latency: ...
+
+# UMOVvi16_idx0_throughput-NOT: Not all operands were initialized by the snippet generator for UMOVvi16_idx0 opcode
+# UMOVvi16_idx0_throughput: ---
+# UMOVvi16_idx0_throughput-NEXT: mode: inverse_throughput
+# UMOVvi16_idx0_throughput-NEXT: key:
+# UMOVvi16_idx0_throughput-NEXT: instructions:
+# UMOVvi16_idx0_throughput-NEXT: UMOVvi16_idx0 [[REG1:W[0-9]+|LR]] [[REG2:Q[0-9]+|LR]] i_0x0
+# UMOVvi16_idx0_throughput: ...
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