[llvm] Enumerate all passes being invoked in each optimization level with comprehensive script code to generate the comparison report between optimization level O2 and O3. (PR #144921)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 19 09:17:56 PDT 2025
https://github.com/RohitSuresh28 created https://github.com/llvm/llvm-project/pull/144921
**Introduction**
This project develops a comprehensive pass tracking and analysis system for the LLVM compiler infrastructure to provide enhanced visibility into optimization pipeline execution. The primary contribution involves implementing a new debugging feature, debug-pass=List, within LLVM's Legacy Pass Manager that generates clean, structured output listing each optimization pass as it executes, addressing the current lack of accessible tools for tracking pass execution sequences across different optimization levels.
**Objectives**
- Study the output of -mllvm -print-after-all and -mllvm -print-before-all to observe IR changes after/before each pass.
- Analyze the output of -debug-pass=Structure to understand the structure of the pass pipeline.
- Implement a new option -debug-pass=List that lists the names of passes being invoked, instead of IR.
- Ensure the new option reflects changes in passes based on different optimization levels.
- Use the new option to compare and differentiate pass sequences for optimization levels like -O2 and -O3.
**Key Feature**
-debug-pass=List
-debug-pass=List will offer a lightweight, dynamic, and readable way to trace exactly what LLVM is doing at various optimization levels — without the clutter of IR or the abstraction of static pass structures.
**Command Execution Instructions
1. Debug Pass Structure**
bash
**./bin/clang -mllvm -debug-pass=Structure test.c > structure_new.txt 2>&1**
What it does: Shows the hierarchical structure of all pass managers and passes before execution. Displays how passes are organized (Module Pass Manager, Function Pass Manager, etc.) in a tree-like format.The result is saved in a new file Structure_new.txt.
**2. Print Before All Passes
bash**
**./bin/clang -mllvm -print-before-all test.c > print_before_all_new.txt 2>&1**
What it does: Prints the LLVM IR (Intermediate Representation) before each optimization pass runs. Shows the state of your code before any transformations are applied.The result is saved in a new file print_before_all_new.txt.
**3. Print After All Passes
bash
./bin/clang -mllvm -print-after-all test.c > print_after_all_new.txt 2>&1**
What it does: Prints the LLVM IR after each optimization pass completes. Shows how each pass transforms your code step by step.The result is saved in a new file print_after_all_new.txt.
**Core Implementation: debug-pass=List Feature**
The central component of this project involves modifying LLVM's Legacy Pass Manager implementation, specifically the LegacyPassManager.cpp file, to introduce a new debugging option: debug-pass=List. This feature extends the existing debugging capabilities by providing a clean, structured output that lists each optimization pass as it executes. Unlike existing options that produce verbose debugging information or detailed IR dumps, this implementation focuses on generating a concise checklist of pass names, making it practical for everyday use by developers who need to track optimization pipeline behavior without overwhelming detail.
The implementation requires careful integration with LLVM's pass management infrastructure, ensuring compatibility with both module-level and function-level passes while maintaining the existing debugging framework's structure. The modification tracks pass execution across different pass managers (Module Pass Manager, Function Pass Manager, etc.) and provides consistent output formatting that clearly identifies which passes are running and in what order.
Changes in the LegacyPassManager.cpp
// Different debug levels that can be enabled...
enum PassDebugLevel {
Disabled,
Arguments,
Structure,
Executions,
Details,
List // Added this
};
static cl::opt PassDebugging(
"debug-pass", cl::Hidden,
cl::desc("Print legacy PassManager debugging information"),
cl::values(clEnumVal(Disabled, "disable debug output"),
clEnumVal(Arguments, "print pass arguments to pass to 'opt'"),
clEnumVal(Structure, "print pass structure before run()"),
clEnumVal(Executions, "print pass name before it is executed"),
clEnumVal(Details, "print pass details when it is executed"),
clEnumValN(List, "List", "List the passes being run"))); // add this
// Log the pass name if PassDebugging is set to List
if (PassDebugging == List) {
errs() << "Running pass: " << FP->getPassName() << "\n";
}
// Log the pass name if PassDebugging is set to List
if (PassDebugging == List) {
errs() << "Running pass: " << MP->getPassName() << "\n";
}
**Commands to run the Debug=list for all optimization levels -O0,O1,O2 and O3.**
**./bin/clang -O0 -mllvm -debug-pass=List test.c > optimization_0.txt 2>&1
./bin/clang -O0 -mllvm -debug-pass=List test.c > optimization_1.txt 2>&1
./bin/clang -O0 -mllvm -debug-pass=List test.c > optimization_2.txt 2>&1
./bin/clang -O0 -mllvm -debug-pass=List test.c > optimization_03txt 2>&1**
The result of each command is saved in the optimization_0.txt,optimization_1.txt,optimization_2.txt,optimization_3.txt respectively.
**We also have generated the Comparison report for Optimization level O2 and O3.**
you have to run the script file generate _o2_03_report.sh
**chmod +x generate_o2_o3_report.sh
./generate_o2_o3_report.sh**
**What the Script Does
Executes your commands:**
./bin/clang -O2 -mllvm -debug-pass=List test.c
./bin/clang -O3 -mllvm -debug-pass=List test.c
**Analyzes the differences:**
- Counts total passes in each level
- Identifies O3-only passes (what's new in O3)
- Shows pass execution order
- Categorizes passes by type (loop, function, memory optimizations)
- Generates a comprehensive report with:
**Executive summary with statistics**
- List of passes unique to O3
- Pass frequency analysis
- Categorization of optimization types
- Complete execution order comparison
- Performance implications
- Recommendations
- Note: we have created a test.c file which contains multiple dead statements to show the difference between different optimization levels.
**Contibutors:**
Rohit Suresh
Ranjana Prabhudas
>From 363519eb76ace7ea18fc4a869541468d6bb424de Mon Sep 17 00:00:00 2001
From: RohitSuresh28 <132984588+RohitSuresh28 at users.noreply.github.com>
Date: Thu, 19 Jun 2025 21:14:37 +0530
Subject: [PATCH] Add files via upload
---
LegacyPassManager.cpp | 1746 +++++++++++++
O2_vs_O3_comparison_report.txt | 566 +++++
generate_o2_o3_report.sh | 284 +++
optimization_0_new.txt | 676 +++++
optimization_1_new.txt | 1781 +++++++++++++
optimization_2_new.txt | 1792 +++++++++++++
optimization_3_new.txt | 1867 ++++++++++++++
print_after_all_new.txt | 4385 ++++++++++++++++++++++++++++++++
print_before_all_new.txt | 4310 +++++++++++++++++++++++++++++++
structure_new.txt | 87 +
test.c | 21 +
11 files changed, 17515 insertions(+)
create mode 100644 LegacyPassManager.cpp
create mode 100644 O2_vs_O3_comparison_report.txt
create mode 100644 generate_o2_o3_report.sh
create mode 100644 optimization_0_new.txt
create mode 100644 optimization_1_new.txt
create mode 100644 optimization_2_new.txt
create mode 100644 optimization_3_new.txt
create mode 100644 print_after_all_new.txt
create mode 100644 print_before_all_new.txt
create mode 100644 structure_new.txt
create mode 100644 test.c
diff --git a/LegacyPassManager.cpp b/LegacyPassManager.cpp
new file mode 100644
index 0000000000000..d0533fd8c9bdb
--- /dev/null
+++ b/LegacyPassManager.cpp
@@ -0,0 +1,1746 @@
+//===- LegacyPassManager.cpp - LLVM Pass Infrastructure Implementation ----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the legacy LLVM Pass Manager infrastructure.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/IR/LegacyPassManager.h"
+#include "llvm/ADT/MapVector.h"
+#include "llvm/IR/DiagnosticInfo.h"
+#include "llvm/IR/IRPrintingPasses.h"
+#include "llvm/IR/LLVMContext.h"
+#include "llvm/IR/LegacyPassManagers.h"
+#include "llvm/IR/Module.h"
+#include "llvm/IR/PassTimingInfo.h"
+#include "llvm/IR/PrintPasses.h"
+#include "llvm/Support/Chrono.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/Error.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/TimeProfiler.h"
+#include "llvm/Support/Timer.h"
+#include "llvm/Support/raw_ostream.h"
+#include <algorithm>
+
+using namespace llvm;
+
+extern cl::opt<bool> UseNewDbgInfoFormat;
+// See PassManagers.h for Pass Manager infrastructure overview.
+
+//===----------------------------------------------------------------------===//
+// Pass debugging information. Often it is useful to find out what pass is
+// running when a crash occurs in a utility. When this library is compiled with
+// debugging on, a command line option (--debug-pass) is enabled that causes the
+// pass name to be printed before it executes.
+//
+
+namespace {
+// Different debug levels that can be enabled...
+enum PassDebugLevel {
+ Disabled,
+ Arguments,
+ Structure,
+ Executions,
+ Details,
+ List
+};
+} // namespace
+
+static cl::opt<enum PassDebugLevel> PassDebugging(
+ "debug-pass", cl::Hidden,
+ cl::desc("Print legacy PassManager debugging information"),
+ cl::values(clEnumVal(Disabled, "disable debug output"),
+ clEnumVal(Arguments, "print pass arguments to pass to 'opt'"),
+ clEnumVal(Structure, "print pass structure before run()"),
+ clEnumVal(Executions, "print pass name before it is executed"),
+ clEnumVal(Details, "print pass details when it is executed"),
+ clEnumValN(List, "List", "List the passes being run")));
+
+/// isPassDebuggingExecutionsOrMore - Return true if -debug-pass=Executions
+/// or higher is specified.
+bool PMDataManager::isPassDebuggingExecutionsOrMore() const {
+ return PassDebugging >= Executions;
+}
+
+unsigned PMDataManager::initSizeRemarkInfo(
+ Module &M, StringMap<std::pair<unsigned, unsigned>> &FunctionToInstrCount) {
+ // Only calculate getInstructionCount if the size-info remark is requested.
+ unsigned InstrCount = 0;
+
+ // Collect instruction counts for every function. We'll use this to emit
+ // per-function size remarks later.
+ for (Function &F : M) {
+ unsigned FCount = F.getInstructionCount();
+
+ // Insert a record into FunctionToInstrCount keeping track of the current
+ // size of the function as the first member of a pair. Set the second
+ // member to 0; if the function is deleted by the pass, then when we get
+ // here, we'll be able to let the user know that F no longer contributes to
+ // the module.
+ FunctionToInstrCount[F.getName().str()] =
+ std::pair<unsigned, unsigned>(FCount, 0);
+ InstrCount += FCount;
+ }
+ return InstrCount;
+}
+
+void PMDataManager::emitInstrCountChangedRemark(
+ Pass *P, Module &M, int64_t Delta, unsigned CountBefore,
+ StringMap<std::pair<unsigned, unsigned>> &FunctionToInstrCount,
+ Function *F) {
+ // If it's a pass manager, don't emit a remark. (This hinges on the assumption
+ // that the only passes that return non-null with getAsPMDataManager are pass
+ // managers.) The reason we have to do this is to avoid emitting remarks for
+ // CGSCC passes.
+ if (P->getAsPMDataManager())
+ return;
+
+ // Set to true if this isn't a module pass or CGSCC pass.
+ bool CouldOnlyImpactOneFunction = (F != nullptr);
+
+ // Helper lambda that updates the changes to the size of some function.
+ auto UpdateFunctionChanges = [&FunctionToInstrCount](
+ Function &MaybeChangedFn) {
+ // Update the total module count.
+ unsigned FnSize = MaybeChangedFn.getInstructionCount();
+
+ // If we created a new function, then we need to add it to the map and
+ // say that it changed from 0 instructions to FnSize.
+ auto [It, Inserted] =
+ FunctionToInstrCount.try_emplace(MaybeChangedFn.getName(), 0, FnSize);
+ if (Inserted)
+ return;
+ // Insert the new function size into the second member of the pair. This
+ // tells us whether or not this function changed in size.
+ It->second.second = FnSize;
+ };
+
+ // We need to initially update all of the function sizes.
+ // If no function was passed in, then we're either a module pass or an
+ // CGSCC pass.
+ if (!CouldOnlyImpactOneFunction)
+ std::for_each(M.begin(), M.end(), UpdateFunctionChanges);
+ else
+ UpdateFunctionChanges(*F);
+
+ // Do we have a function we can use to emit a remark?
+ if (!CouldOnlyImpactOneFunction) {
+ // We need a function containing at least one basic block in order to output
+ // remarks. Since it's possible that the first function in the module
+ // doesn't actually contain a basic block, we have to go and find one that's
+ // suitable for emitting remarks.
+ auto It = llvm::find_if(M, [](const Function &Fn) { return !Fn.empty(); });
+
+ // Didn't find a function. Quit.
+ if (It == M.end())
+ return;
+
+ // We found a function containing at least one basic block.
+ F = &*It;
+ }
+ int64_t CountAfter = static_cast<int64_t>(CountBefore) + Delta;
+ BasicBlock &BB = *F->begin();
+ OptimizationRemarkAnalysis R("size-info", "IRSizeChange",
+ DiagnosticLocation(), &BB);
+ // FIXME: Move ore namespace to DiagnosticInfo so that we can use it. This
+ // would let us use NV instead of DiagnosticInfoOptimizationBase::Argument.
+ R << DiagnosticInfoOptimizationBase::Argument("Pass", P->getPassName())
+ << ": IR instruction count changed from "
+ << DiagnosticInfoOptimizationBase::Argument("IRInstrsBefore", CountBefore)
+ << " to "
+ << DiagnosticInfoOptimizationBase::Argument("IRInstrsAfter", CountAfter)
+ << "; Delta: "
+ << DiagnosticInfoOptimizationBase::Argument("DeltaInstrCount", Delta);
+ F->getContext().diagnose(R); // Not using ORE for layering reasons.
+
+ // Emit per-function size change remarks separately.
+ std::string PassName = P->getPassName().str();
+
+ // Helper lambda that emits a remark when the size of a function has changed.
+ auto EmitFunctionSizeChangedRemark = [&FunctionToInstrCount, &F, &BB,
+ &PassName](StringRef Fname) {
+ unsigned FnCountBefore, FnCountAfter;
+ std::pair<unsigned, unsigned> &Change = FunctionToInstrCount[Fname];
+ std::tie(FnCountBefore, FnCountAfter) = Change;
+ int64_t FnDelta = static_cast<int64_t>(FnCountAfter) -
+ static_cast<int64_t>(FnCountBefore);
+
+ if (FnDelta == 0)
+ return;
+
+ // FIXME: We shouldn't use BB for the location here. Unfortunately, because
+ // the function that we're looking at could have been deleted, we can't use
+ // it for the source location. We *want* remarks when a function is deleted
+ // though, so we're kind of stuck here as is. (This remark, along with the
+ // whole-module size change remarks really ought not to have source
+ // locations at all.)
+ OptimizationRemarkAnalysis FR("size-info", "FunctionIRSizeChange",
+ DiagnosticLocation(), &BB);
+ FR << DiagnosticInfoOptimizationBase::Argument("Pass", PassName)
+ << ": Function: "
+ << DiagnosticInfoOptimizationBase::Argument("Function", Fname)
+ << ": IR instruction count changed from "
+ << DiagnosticInfoOptimizationBase::Argument("IRInstrsBefore",
+ FnCountBefore)
+ << " to "
+ << DiagnosticInfoOptimizationBase::Argument("IRInstrsAfter",
+ FnCountAfter)
+ << "; Delta: "
+ << DiagnosticInfoOptimizationBase::Argument("DeltaInstrCount", FnDelta);
+ F->getContext().diagnose(FR);
+
+ // Update the function size.
+ Change.first = FnCountAfter;
+ };
+
+ // Are we looking at more than one function? If so, emit remarks for all of
+ // the functions in the module. Otherwise, only emit one remark.
+ if (!CouldOnlyImpactOneFunction)
+ std::for_each(FunctionToInstrCount.keys().begin(),
+ FunctionToInstrCount.keys().end(),
+ EmitFunctionSizeChangedRemark);
+ else
+ EmitFunctionSizeChangedRemark(F->getName().str());
+}
+
+void PassManagerPrettyStackEntry::print(raw_ostream &OS) const {
+ if (!V && !M)
+ OS << "Releasing pass '";
+ else
+ OS << "Running pass '";
+
+ OS << P->getPassName() << "'";
+
+ if (M) {
+ OS << " on module '" << M->getModuleIdentifier() << "'.\n";
+ return;
+ }
+ if (!V) {
+ OS << '\n';
+ return;
+ }
+
+ OS << " on ";
+ if (isa<Function>(V))
+ OS << "function";
+ else if (isa<BasicBlock>(V))
+ OS << "basic block";
+ else
+ OS << "value";
+
+ OS << " '";
+ V->printAsOperand(OS, /*PrintType=*/false, M);
+ OS << "'\n";
+}
+
+namespace llvm {
+namespace legacy {
+bool debugPassSpecified() { return PassDebugging != Disabled; }
+
+//===----------------------------------------------------------------------===//
+// FunctionPassManagerImpl
+//
+/// FunctionPassManagerImpl manages FPPassManagers
+class FunctionPassManagerImpl : public Pass,
+ public PMDataManager,
+ public PMTopLevelManager {
+ virtual void anchor();
+
+private:
+ bool wasRun;
+
+public:
+ static char ID;
+ explicit FunctionPassManagerImpl()
+ : Pass(PT_PassManager, ID), PMTopLevelManager(new FPPassManager()),
+ wasRun(false) {}
+
+ /// \copydoc FunctionPassManager::add()
+ void add(Pass *P) { schedulePass(P); }
+
+ /// createPrinterPass - Get a function printer pass.
+ Pass *createPrinterPass(raw_ostream &O,
+ const std::string &Banner) const override {
+ return createPrintFunctionPass(O, Banner);
+ }
+
+ // Prepare for running an on the fly pass, freeing memory if needed
+ // from a previous run.
+ void releaseMemoryOnTheFly();
+
+ /// run - Execute all of the passes scheduled for execution. Keep track of
+ /// whether any of the passes modifies the module, and if so, return true.
+ bool run(Function &F);
+
+ /// doInitialization - Run all of the initializers for the function passes.
+ ///
+ bool doInitialization(Module &M) override;
+
+ /// doFinalization - Run all of the finalizers for the function passes.
+ ///
+ bool doFinalization(Module &M) override;
+
+ PMDataManager *getAsPMDataManager() override { return this; }
+ Pass *getAsPass() override { return this; }
+ PassManagerType getTopLevelPassManagerType() override {
+ return PMT_FunctionPassManager;
+ }
+
+ /// Pass Manager itself does not invalidate any analysis info.
+ void getAnalysisUsage(AnalysisUsage &Info) const override {
+ Info.setPreservesAll();
+ }
+
+ FPPassManager *getContainedManager(unsigned N) {
+ assert(N < PassManagers.size() && "Pass number out of range!");
+ FPPassManager *FP = static_cast<FPPassManager *>(PassManagers[N]);
+ return FP;
+ }
+
+ void dumpPassStructure(unsigned Offset) override {
+ for (unsigned I = 0; I < getNumContainedManagers(); ++I)
+ getContainedManager(I)->dumpPassStructure(Offset);
+ }
+};
+
+void FunctionPassManagerImpl::anchor() {}
+
+char FunctionPassManagerImpl::ID = 0;
+
+//===----------------------------------------------------------------------===//
+// FunctionPassManagerImpl implementation
+//
+bool FunctionPassManagerImpl::doInitialization(Module &M) {
+ bool Changed = false;
+
+ dumpArguments();
+ dumpPasses();
+
+ for (ImmutablePass *ImPass : getImmutablePasses())
+ Changed |= ImPass->doInitialization(M);
+
+ for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index)
+ Changed |= getContainedManager(Index)->doInitialization(M);
+
+ return Changed;
+}
+
+bool FunctionPassManagerImpl::doFinalization(Module &M) {
+ bool Changed = false;
+
+ for (int Index = getNumContainedManagers() - 1; Index >= 0; --Index)
+ Changed |= getContainedManager(Index)->doFinalization(M);
+
+ for (ImmutablePass *ImPass : getImmutablePasses())
+ Changed |= ImPass->doFinalization(M);
+
+ return Changed;
+}
+
+void FunctionPassManagerImpl::releaseMemoryOnTheFly() {
+ if (!wasRun)
+ return;
+ for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) {
+ FPPassManager *FPPM = getContainedManager(Index);
+ for (unsigned Index = 0; Index < FPPM->getNumContainedPasses(); ++Index) {
+ FPPM->getContainedPass(Index)->releaseMemory();
+ }
+ }
+ wasRun = false;
+}
+
+// Execute all the passes managed by this top level manager.
+// Return true if any function is modified by a pass.
+
+bool FunctionPassManagerImpl::run(Function &F) {
+ bool Changed = false;
+
+ initializeAllAnalysisInfo();
+ for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) {
+ Changed |= getContainedManager(Index)->runOnFunction(F);
+ F.getContext().yield();
+ }
+
+ for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index)
+ getContainedManager(Index)->cleanup();
+
+ wasRun = true;
+ return Changed;
+}
+} // namespace legacy
+} // namespace llvm
+
+namespace {
+//===----------------------------------------------------------------------===//
+// MPPassManager
+//
+/// MPPassManager manages ModulePasses and function pass managers.
+/// It batches all Module passes and function pass managers together and
+/// sequences them to process one module.
+class MPPassManager : public Pass, public PMDataManager {
+public:
+ static char ID;
+ explicit MPPassManager() : Pass(PT_PassManager, ID) {}
+
+ // Delete on the fly managers.
+ ~MPPassManager() override {
+ for (auto &OnTheFlyManager : OnTheFlyManagers) {
+ legacy::FunctionPassManagerImpl *FPP = OnTheFlyManager.second;
+ delete FPP;
+ }
+ }
+
+ /// createPrinterPass - Get a module printer pass.
+ Pass *createPrinterPass(raw_ostream &O,
+ const std::string &Banner) const override {
+ return createPrintModulePass(O, Banner);
+ }
+
+ /// run - Execute all of the passes scheduled for execution. Keep track of
+ /// whether any of the passes modifies the module, and if so, return true.
+ bool runOnModule(Module &M);
+
+ using llvm::Pass::doFinalization;
+ using llvm::Pass::doInitialization;
+
+ /// Pass Manager itself does not invalidate any analysis info.
+ void getAnalysisUsage(AnalysisUsage &Info) const override {
+ Info.setPreservesAll();
+ }
+
+ /// Add RequiredPass into list of lower level passes required by pass P.
+ /// RequiredPass is run on the fly by Pass Manager when P requests it
+ /// through getAnalysis interface.
+ void addLowerLevelRequiredPass(Pass *P, Pass *RequiredPass) override;
+
+ /// Return function pass corresponding to PassInfo PI, that is
+ /// required by module pass MP. Instantiate analysis pass, by using
+ /// its runOnFunction() for function F.
+ std::tuple<Pass *, bool> getOnTheFlyPass(Pass *MP, AnalysisID PI,
+ Function &F) override;
+
+ StringRef getPassName() const override { return "Module Pass Manager"; }
+
+ PMDataManager *getAsPMDataManager() override { return this; }
+ Pass *getAsPass() override { return this; }
+
+ // Print passes managed by this manager
+ void dumpPassStructure(unsigned Offset) override {
+ dbgs().indent(Offset * 2) << "ModulePass Manager\n";
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ ModulePass *MP = getContainedPass(Index);
+ MP->dumpPassStructure(Offset + 1);
+ MapVector<Pass *, legacy::FunctionPassManagerImpl *>::const_iterator I =
+ OnTheFlyManagers.find(MP);
+ if (I != OnTheFlyManagers.end())
+ I->second->dumpPassStructure(Offset + 2);
+ dumpLastUses(MP, Offset + 1);
+ }
+ }
+
+ ModulePass *getContainedPass(unsigned N) {
+ assert(N < PassVector.size() && "Pass number out of range!");
+ return static_cast<ModulePass *>(PassVector[N]);
+ }
+
+ PassManagerType getPassManagerType() const override {
+ return PMT_ModulePassManager;
+ }
+
+private:
+ /// Collection of on the fly FPPassManagers. These managers manage
+ /// function passes that are required by module passes.
+ MapVector<Pass *, legacy::FunctionPassManagerImpl *> OnTheFlyManagers;
+};
+
+char MPPassManager::ID = 0;
+} // End anonymous namespace
+
+namespace llvm {
+namespace legacy {
+//===----------------------------------------------------------------------===//
+// PassManagerImpl
+//
+
+/// PassManagerImpl manages MPPassManagers
+class PassManagerImpl : public Pass,
+ public PMDataManager,
+ public PMTopLevelManager {
+ virtual void anchor();
+
+public:
+ static char ID;
+ explicit PassManagerImpl()
+ : Pass(PT_PassManager, ID), PMTopLevelManager(new MPPassManager()) {}
+
+ /// \copydoc PassManager::add()
+ void add(Pass *P) { schedulePass(P); }
+
+ /// createPrinterPass - Get a module printer pass.
+ Pass *createPrinterPass(raw_ostream &O,
+ const std::string &Banner) const override {
+ return createPrintModulePass(O, Banner);
+ }
+
+ /// run - Execute all of the passes scheduled for execution. Keep track of
+ /// whether any of the passes modifies the module, and if so, return true.
+ bool run(Module &M);
+
+ using llvm::Pass::doFinalization;
+ using llvm::Pass::doInitialization;
+
+ /// Pass Manager itself does not invalidate any analysis info.
+ void getAnalysisUsage(AnalysisUsage &Info) const override {
+ Info.setPreservesAll();
+ }
+
+ PMDataManager *getAsPMDataManager() override { return this; }
+ Pass *getAsPass() override { return this; }
+ PassManagerType getTopLevelPassManagerType() override {
+ return PMT_ModulePassManager;
+ }
+
+ MPPassManager *getContainedManager(unsigned N) {
+ assert(N < PassManagers.size() && "Pass number out of range!");
+ MPPassManager *MP = static_cast<MPPassManager *>(PassManagers[N]);
+ return MP;
+ }
+};
+
+void PassManagerImpl::anchor() {}
+
+char PassManagerImpl::ID = 0;
+
+//===----------------------------------------------------------------------===//
+// PassManagerImpl implementation
+
+//
+/// run - Execute all of the passes scheduled for execution. Keep track of
+/// whether any of the passes modifies the module, and if so, return true.
+bool PassManagerImpl::run(Module &M) {
+ bool Changed = false;
+
+ dumpArguments();
+ dumpPasses();
+
+ // RemoveDIs: if a command line flag is given, convert to the
+ // DbgVariableRecord representation of debug-info for the duration of these
+ // passes.
+ ScopedDbgInfoFormatSetter FormatSetter(M, UseNewDbgInfoFormat);
+
+ for (ImmutablePass *ImPass : getImmutablePasses())
+ Changed |= ImPass->doInitialization(M);
+
+ initializeAllAnalysisInfo();
+ for (unsigned Index = 0; Index < getNumContainedManagers(); ++Index) {
+ Changed |= getContainedManager(Index)->runOnModule(M);
+ M.getContext().yield();
+ }
+
+ for (ImmutablePass *ImPass : getImmutablePasses())
+ Changed |= ImPass->doFinalization(M);
+
+ return Changed;
+}
+} // namespace legacy
+} // namespace llvm
+
+//===----------------------------------------------------------------------===//
+// PMTopLevelManager implementation
+
+/// Initialize top level manager. Create first pass manager.
+PMTopLevelManager::PMTopLevelManager(PMDataManager *PMDM) {
+ PMDM->setTopLevelManager(this);
+ addPassManager(PMDM);
+ activeStack.push(PMDM);
+}
+
+/// Set pass P as the last user of the given analysis passes.
+void PMTopLevelManager::setLastUser(ArrayRef<Pass *> AnalysisPasses, Pass *P) {
+ unsigned PDepth = 0;
+ if (P->getResolver())
+ PDepth = P->getResolver()->getPMDataManager().getDepth();
+
+ for (Pass *AP : AnalysisPasses) {
+ // Record P as the new last user of AP.
+ auto &LastUserOfAP = LastUser[AP];
+ if (LastUserOfAP)
+ InversedLastUser[LastUserOfAP].erase(AP);
+ LastUserOfAP = P;
+ InversedLastUser[P].insert(AP);
+
+ if (P == AP)
+ continue;
+
+ // Update the last users of passes that are required transitive by AP.
+ AnalysisUsage *AnUsage = findAnalysisUsage(AP);
+ const AnalysisUsage::VectorType &IDs = AnUsage->getRequiredTransitiveSet();
+ SmallVector<Pass *, 12> LastUses;
+ SmallVector<Pass *, 12> LastPMUses;
+ for (AnalysisID ID : IDs) {
+ Pass *AnalysisPass = findAnalysisPass(ID);
+ assert(AnalysisPass && "Expected analysis pass to exist.");
+ AnalysisResolver *AR = AnalysisPass->getResolver();
+ assert(AR && "Expected analysis resolver to exist.");
+ unsigned APDepth = AR->getPMDataManager().getDepth();
+
+ if (PDepth == APDepth)
+ LastUses.push_back(AnalysisPass);
+ else if (PDepth > APDepth)
+ LastPMUses.push_back(AnalysisPass);
+ }
+
+ setLastUser(LastUses, P);
+
+ // If this pass has a corresponding pass manager, push higher level
+ // analysis to this pass manager.
+ if (P->getResolver())
+ setLastUser(LastPMUses, P->getResolver()->getPMDataManager().getAsPass());
+
+ // If AP is the last user of other passes then make P last user of
+ // such passes.
+ auto &LastUsedByAP = InversedLastUser[AP];
+ for (Pass *L : LastUsedByAP)
+ LastUser[L] = P;
+ InversedLastUser[P].insert_range(LastUsedByAP);
+ LastUsedByAP.clear();
+ }
+}
+
+/// Collect passes whose last user is P
+void PMTopLevelManager::collectLastUses(SmallVectorImpl<Pass *> &LastUses,
+ Pass *P) {
+ auto DMI = InversedLastUser.find(P);
+ if (DMI == InversedLastUser.end())
+ return;
+
+ auto &LU = DMI->second;
+ LastUses.append(LU.begin(), LU.end());
+}
+
+AnalysisUsage *PMTopLevelManager::findAnalysisUsage(Pass *P) {
+ AnalysisUsage *AnUsage = nullptr;
+ auto DMI = AnUsageMap.find(P);
+ if (DMI != AnUsageMap.end())
+ AnUsage = DMI->second;
+ else {
+ // Look up the analysis usage from the pass instance (different instances
+ // of the same pass can produce different results), but unique the
+ // resulting object to reduce memory usage. This helps to greatly reduce
+ // memory usage when we have many instances of only a few pass types
+ // (e.g. instcombine, simplifycfg, etc...) which tend to share a fixed set
+ // of dependencies.
+ AnalysisUsage AU;
+ P->getAnalysisUsage(AU);
+
+ AUFoldingSetNode *Node = nullptr;
+ FoldingSetNodeID ID;
+ AUFoldingSetNode::Profile(ID, AU);
+ void *IP = nullptr;
+ if (auto *N = UniqueAnalysisUsages.FindNodeOrInsertPos(ID, IP))
+ Node = N;
+ else {
+ Node = new (AUFoldingSetNodeAllocator.Allocate()) AUFoldingSetNode(AU);
+ UniqueAnalysisUsages.InsertNode(Node, IP);
+ }
+ assert(Node && "cached analysis usage must be non null");
+
+ AnUsageMap[P] = &Node->AU;
+ AnUsage = &Node->AU;
+ }
+ return AnUsage;
+}
+
+/// Schedule pass P for execution. Make sure that passes required by
+/// P are run before P is run. Update analysis info maintained by
+/// the manager. Remove dead passes. This is a recursive function.
+void PMTopLevelManager::schedulePass(Pass *P) {
+
+ // TODO : Allocate function manager for this pass, other wise required set
+ // may be inserted into previous function manager
+
+ // Give pass a chance to prepare the stage.
+ P->preparePassManager(activeStack);
+
+ // If P is an analysis pass and it is available then do not
+ // generate the analysis again. Stale analysis info should not be
+ // available at this point.
+ const PassInfo *PI = findAnalysisPassInfo(P->getPassID());
+ if (PI && PI->isAnalysis() && findAnalysisPass(P->getPassID())) {
+ // Remove any cached AnalysisUsage information.
+ AnUsageMap.erase(P);
+ delete P;
+ return;
+ }
+
+ AnalysisUsage *AnUsage = findAnalysisUsage(P);
+
+ bool checkAnalysis = true;
+ while (checkAnalysis) {
+ checkAnalysis = false;
+
+ const AnalysisUsage::VectorType &RequiredSet = AnUsage->getRequiredSet();
+ for (const AnalysisID ID : RequiredSet) {
+
+ Pass *AnalysisPass = findAnalysisPass(ID);
+ if (!AnalysisPass) {
+ const PassInfo *PI = findAnalysisPassInfo(ID);
+
+ if (!PI) {
+ // Pass P is not in the global PassRegistry
+ dbgs() << "Pass '" << P->getPassName() << "' is not initialized."
+ << "\n";
+ dbgs() << "Verify if there is a pass dependency cycle." << "\n";
+ dbgs() << "Required Passes:" << "\n";
+ for (const AnalysisID ID2 : RequiredSet) {
+ if (ID == ID2)
+ break;
+ Pass *AnalysisPass2 = findAnalysisPass(ID2);
+ if (AnalysisPass2) {
+ dbgs() << "\t" << AnalysisPass2->getPassName() << "\n";
+ } else {
+ dbgs() << "\t"
+ << "Error: Required pass not found! Possible causes:"
+ << "\n";
+ dbgs() << "\t\t"
+ << "- Pass misconfiguration (e.g.: missing macros)"
+ << "\n";
+ dbgs() << "\t\t" << "- Corruption of the global PassRegistry"
+ << "\n";
+ }
+ }
+ }
+
+ assert(PI && "Expected required passes to be initialized");
+ AnalysisPass = PI->createPass();
+ if (P->getPotentialPassManagerType() ==
+ AnalysisPass->getPotentialPassManagerType())
+ // Schedule analysis pass that is managed by the same pass manager.
+ schedulePass(AnalysisPass);
+ else if (P->getPotentialPassManagerType() >
+ AnalysisPass->getPotentialPassManagerType()) {
+ // Schedule analysis pass that is managed by a new manager.
+ schedulePass(AnalysisPass);
+ // Recheck analysis passes to ensure that required analyses that
+ // are already checked are still available.
+ checkAnalysis = true;
+ } else
+ // Do not schedule this analysis. Lower level analysis
+ // passes are run on the fly.
+ delete AnalysisPass;
+ }
+ }
+ }
+
+ // Now all required passes are available.
+ if (ImmutablePass *IP = P->getAsImmutablePass()) {
+ // P is a immutable pass and it will be managed by this
+ // top level manager. Set up analysis resolver to connect them.
+ PMDataManager *DM = getAsPMDataManager();
+ AnalysisResolver *AR = new AnalysisResolver(*DM);
+ P->setResolver(AR);
+ DM->initializeAnalysisImpl(P);
+ addImmutablePass(IP);
+ DM->recordAvailableAnalysis(IP);
+ return;
+ }
+
+ if (PI && !PI->isAnalysis() && shouldPrintBeforePass(PI->getPassArgument())) {
+ Pass *PP =
+ P->createPrinterPass(dbgs(), ("*** IR Dump Before " + P->getPassName() +
+ " (" + PI->getPassArgument() + ") ***")
+ .str());
+ PP->assignPassManager(activeStack, getTopLevelPassManagerType());
+ }
+
+ // Add the requested pass to the best available pass manager.
+ P->assignPassManager(activeStack, getTopLevelPassManagerType());
+
+ if (PI && !PI->isAnalysis() && shouldPrintAfterPass(PI->getPassArgument())) {
+ Pass *PP =
+ P->createPrinterPass(dbgs(), ("*** IR Dump After " + P->getPassName() +
+ " (" + PI->getPassArgument() + ") ***")
+ .str());
+ PP->assignPassManager(activeStack, getTopLevelPassManagerType());
+ }
+}
+
+/// Find the pass that implements Analysis AID. Search immutable
+/// passes and all pass managers. If desired pass is not found
+/// then return NULL.
+Pass *PMTopLevelManager::findAnalysisPass(AnalysisID AID) {
+ // For immutable passes we have a direct mapping from ID to pass, so check
+ // that first.
+ if (Pass *P = ImmutablePassMap.lookup(AID))
+ return P;
+
+ // Check pass managers
+ for (PMDataManager *PassManager : PassManagers)
+ if (Pass *P = PassManager->findAnalysisPass(AID, false))
+ return P;
+
+ // Check other pass managers
+ for (PMDataManager *IndirectPassManager : IndirectPassManagers)
+ if (Pass *P = IndirectPassManager->findAnalysisPass(AID, false))
+ return P;
+
+ return nullptr;
+}
+
+const PassInfo *PMTopLevelManager::findAnalysisPassInfo(AnalysisID AID) const {
+ const PassInfo *&PI = AnalysisPassInfos[AID];
+ if (!PI)
+ PI = PassRegistry::getPassRegistry()->getPassInfo(AID);
+ else
+ assert(PI == PassRegistry::getPassRegistry()->getPassInfo(AID) &&
+ "The pass info pointer changed for an analysis ID!");
+
+ return PI;
+}
+
+void PMTopLevelManager::addImmutablePass(ImmutablePass *P) {
+ P->initializePass();
+ ImmutablePasses.push_back(P);
+
+ // Add this pass to the map from its analysis ID. We clobber any prior runs
+ // of the pass in the map so that the last one added is the one found when
+ // doing lookups.
+ AnalysisID AID = P->getPassID();
+ ImmutablePassMap[AID] = P;
+}
+
+// Print passes managed by this top level manager.
+void PMTopLevelManager::dumpPasses() const {
+
+ if (PassDebugging < Structure)
+ return;
+
+ // Print out the immutable passes
+ for (ImmutablePass *Pass : ImmutablePasses)
+ Pass->dumpPassStructure(0);
+
+ // Every class that derives from PMDataManager also derives from Pass
+ // (sometimes indirectly), but there's no inheritance relationship
+ // between PMDataManager and Pass, so we have to getAsPass to get
+ // from a PMDataManager* to a Pass*.
+ for (PMDataManager *Manager : PassManagers)
+ Manager->getAsPass()->dumpPassStructure(1);
+}
+
+void PMTopLevelManager::dumpArguments() const {
+
+ if (PassDebugging < Arguments)
+ return;
+
+ dbgs() << "Pass Arguments: ";
+ for (ImmutablePass *P : ImmutablePasses)
+ if (const PassInfo *PI = findAnalysisPassInfo(P->getPassID())) {
+ assert(PI && "Expected all immutable passes to be initialized");
+ dbgs() << " -" << PI->getPassArgument();
+ }
+ for (PMDataManager *PM : PassManagers)
+ PM->dumpPassArguments();
+ dbgs() << "\n";
+}
+
+void PMTopLevelManager::initializeAllAnalysisInfo() {
+ for (PMDataManager *PM : PassManagers)
+ PM->initializeAnalysisInfo();
+
+ // Initailize other pass managers
+ for (PMDataManager *IPM : IndirectPassManagers)
+ IPM->initializeAnalysisInfo();
+}
+
+/// Destructor
+PMTopLevelManager::~PMTopLevelManager() {
+ for (PMDataManager *PM : PassManagers)
+ delete PM;
+
+ for (ImmutablePass *P : ImmutablePasses)
+ delete P;
+}
+
+//===----------------------------------------------------------------------===//
+// PMDataManager implementation
+
+/// Augement AvailableAnalysis by adding analysis made available by pass P.
+void PMDataManager::recordAvailableAnalysis(Pass *P) {
+ AnalysisID PI = P->getPassID();
+
+ AvailableAnalysis[PI] = P;
+}
+
+// Return true if P preserves high level analysis used by other
+// passes managed by this manager
+bool PMDataManager::preserveHigherLevelAnalysis(Pass *P) {
+ AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P);
+ if (AnUsage->getPreservesAll())
+ return true;
+
+ const AnalysisUsage::VectorType &PreservedSet = AnUsage->getPreservedSet();
+ for (Pass *P1 : HigherLevelAnalysis) {
+ if (P1->getAsImmutablePass() == nullptr &&
+ !is_contained(PreservedSet, P1->getPassID()))
+ return false;
+ }
+
+ return true;
+}
+
+/// verifyPreservedAnalysis -- Verify analysis preserved by pass P.
+void PMDataManager::verifyPreservedAnalysis(Pass *P) {
+ // Don't do this unless assertions are enabled.
+#ifdef NDEBUG
+ return;
+#endif
+ AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P);
+ const AnalysisUsage::VectorType &PreservedSet = AnUsage->getPreservedSet();
+
+ // Verify preserved analysis
+ for (AnalysisID AID : PreservedSet) {
+ if (Pass *AP = findAnalysisPass(AID, true)) {
+ TimeRegion PassTimer(getPassTimer(AP));
+ AP->verifyAnalysis();
+ }
+ }
+}
+
+/// Remove Analysis not preserved by Pass P
+void PMDataManager::removeNotPreservedAnalysis(Pass *P) {
+ AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P);
+ if (AnUsage->getPreservesAll())
+ return;
+
+ const AnalysisUsage::VectorType &PreservedSet = AnUsage->getPreservedSet();
+ for (DenseMap<AnalysisID, Pass *>::iterator I = AvailableAnalysis.begin(),
+ E = AvailableAnalysis.end();
+ I != E;) {
+ DenseMap<AnalysisID, Pass *>::iterator Info = I++;
+ if (Info->second->getAsImmutablePass() == nullptr &&
+ !is_contained(PreservedSet, Info->first)) {
+ // Remove this analysis
+ if (PassDebugging >= Details) {
+ Pass *S = Info->second;
+ dbgs() << " -- '" << P->getPassName() << "' is not preserving '";
+ dbgs() << S->getPassName() << "'\n";
+ }
+ AvailableAnalysis.erase(Info);
+ }
+ }
+
+ // Check inherited analysis also. If P is not preserving analysis
+ // provided by parent manager then remove it here.
+ for (DenseMap<AnalysisID, Pass *> *IA : InheritedAnalysis) {
+ if (!IA)
+ continue;
+
+ for (DenseMap<AnalysisID, Pass *>::iterator I = IA->begin(), E = IA->end();
+ I != E;) {
+ DenseMap<AnalysisID, Pass *>::iterator Info = I++;
+ if (Info->second->getAsImmutablePass() == nullptr &&
+ !is_contained(PreservedSet, Info->first)) {
+ // Remove this analysis
+ if (PassDebugging >= Details) {
+ Pass *S = Info->second;
+ dbgs() << " -- '" << P->getPassName() << "' is not preserving '";
+ dbgs() << S->getPassName() << "'\n";
+ }
+ IA->erase(Info);
+ }
+ }
+ }
+}
+
+/// Remove analysis passes that are not used any longer
+void PMDataManager::removeDeadPasses(Pass *P, StringRef Msg,
+ enum PassDebuggingString DBG_STR) {
+
+ SmallVector<Pass *, 12> DeadPasses;
+
+ // If this is a on the fly manager then it does not have TPM.
+ if (!TPM)
+ return;
+
+ TPM->collectLastUses(DeadPasses, P);
+
+ if (PassDebugging >= Details && !DeadPasses.empty()) {
+ dbgs() << " -*- '" << P->getPassName();
+ dbgs() << "' is the last user of following pass instances.";
+ dbgs() << " Free these instances\n";
+ }
+
+ for (Pass *P : DeadPasses)
+ freePass(P, Msg, DBG_STR);
+}
+
+void PMDataManager::freePass(Pass *P, StringRef Msg,
+ enum PassDebuggingString DBG_STR) {
+ dumpPassInfo(P, FREEING_MSG, DBG_STR, Msg);
+
+ {
+ // If the pass crashes releasing memory, remember this.
+ PassManagerPrettyStackEntry X(P);
+ TimeRegion PassTimer(getPassTimer(P));
+
+ P->releaseMemory();
+ }
+
+ // Remove the pass itself (if it is not already removed).
+ AvailableAnalysis.erase(P->getPassID());
+}
+
+/// Add pass P into the PassVector. Update
+/// AvailableAnalysis appropriately if ProcessAnalysis is true.
+void PMDataManager::add(Pass *P, bool ProcessAnalysis) {
+ // This manager is going to manage pass P. Set up analysis resolver
+ // to connect them.
+ AnalysisResolver *AR = new AnalysisResolver(*this);
+ P->setResolver(AR);
+
+ // If a FunctionPass F is the last user of ModulePass info M
+ // then the F's manager, not F, records itself as a last user of M.
+ SmallVector<Pass *, 12> TransferLastUses;
+
+ if (!ProcessAnalysis) {
+ // Add pass
+ PassVector.push_back(P);
+ return;
+ }
+
+ // At the moment, this pass is the last user of all required passes.
+ SmallVector<Pass *, 12> LastUses;
+ SmallVector<Pass *, 8> UsedPasses;
+ SmallVector<AnalysisID, 8> ReqAnalysisNotAvailable;
+
+ unsigned PDepth = this->getDepth();
+
+ collectRequiredAndUsedAnalyses(UsedPasses, ReqAnalysisNotAvailable, P);
+ for (Pass *PUsed : UsedPasses) {
+ unsigned RDepth = 0;
+
+ assert(PUsed->getResolver() && "Analysis Resolver is not set");
+ PMDataManager &DM = PUsed->getResolver()->getPMDataManager();
+ RDepth = DM.getDepth();
+
+ if (PDepth == RDepth)
+ LastUses.push_back(PUsed);
+ else if (PDepth > RDepth) {
+ // Let the parent claim responsibility of last use
+ TransferLastUses.push_back(PUsed);
+ // Keep track of higher level analysis used by this manager.
+ HigherLevelAnalysis.push_back(PUsed);
+ } else
+ llvm_unreachable("Unable to accommodate Used Pass");
+ }
+
+ // Set P as P's last user until someone starts using P.
+ // However, if P is a Pass Manager then it does not need
+ // to record its last user.
+ if (!P->getAsPMDataManager())
+ LastUses.push_back(P);
+ TPM->setLastUser(LastUses, P);
+
+ if (!TransferLastUses.empty()) {
+ Pass *My_PM = getAsPass();
+ TPM->setLastUser(TransferLastUses, My_PM);
+ TransferLastUses.clear();
+ }
+
+ // Now, take care of required analyses that are not available.
+ for (AnalysisID ID : ReqAnalysisNotAvailable) {
+ const PassInfo *PI = TPM->findAnalysisPassInfo(ID);
+ Pass *AnalysisPass = PI->createPass();
+ this->addLowerLevelRequiredPass(P, AnalysisPass);
+ }
+
+ // Take a note of analysis required and made available by this pass.
+ // Remove the analysis not preserved by this pass
+ removeNotPreservedAnalysis(P);
+ recordAvailableAnalysis(P);
+
+ // Add pass
+ PassVector.push_back(P);
+}
+
+/// Populate UP with analysis pass that are used or required by
+/// pass P and are available. Populate RP_NotAvail with analysis
+/// pass that are required by pass P but are not available.
+void PMDataManager::collectRequiredAndUsedAnalyses(
+ SmallVectorImpl<Pass *> &UP, SmallVectorImpl<AnalysisID> &RP_NotAvail,
+ Pass *P) {
+ AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P);
+
+ for (const auto &UsedID : AnUsage->getUsedSet())
+ if (Pass *AnalysisPass = findAnalysisPass(UsedID, true))
+ UP.push_back(AnalysisPass);
+
+ for (const auto &RequiredID : AnUsage->getRequiredSet())
+ if (Pass *AnalysisPass = findAnalysisPass(RequiredID, true))
+ UP.push_back(AnalysisPass);
+ else
+ RP_NotAvail.push_back(RequiredID);
+}
+
+// All Required analyses should be available to the pass as it runs! Here
+// we fill in the AnalysisImpls member of the pass so that it can
+// successfully use the getAnalysis() method to retrieve the
+// implementations it needs.
+//
+void PMDataManager::initializeAnalysisImpl(Pass *P) {
+ AnalysisUsage *AnUsage = TPM->findAnalysisUsage(P);
+
+ for (const AnalysisID ID : AnUsage->getRequiredSet()) {
+ Pass *Impl = findAnalysisPass(ID, true);
+ if (!Impl)
+ // This may be analysis pass that is initialized on the fly.
+ // If that is not the case then it will raise an assert when it is used.
+ continue;
+ AnalysisResolver *AR = P->getResolver();
+ assert(AR && "Analysis Resolver is not set");
+ AR->addAnalysisImplsPair(ID, Impl);
+ }
+}
+
+/// Find the pass that implements Analysis AID. If desired pass is not found
+/// then return NULL.
+Pass *PMDataManager::findAnalysisPass(AnalysisID AID, bool SearchParent) {
+
+ // Check if AvailableAnalysis map has one entry.
+ DenseMap<AnalysisID, Pass *>::const_iterator I = AvailableAnalysis.find(AID);
+
+ if (I != AvailableAnalysis.end())
+ return I->second;
+
+ // Search Parents through TopLevelManager
+ if (SearchParent)
+ return TPM->findAnalysisPass(AID);
+
+ return nullptr;
+}
+
+// Print list of passes that are last used by P.
+void PMDataManager::dumpLastUses(Pass *P, unsigned Offset) const {
+ if (PassDebugging < Details)
+ return;
+
+ SmallVector<Pass *, 12> LUses;
+
+ // If this is a on the fly manager then it does not have TPM.
+ if (!TPM)
+ return;
+
+ TPM->collectLastUses(LUses, P);
+
+ for (Pass *P : LUses) {
+ dbgs() << "--" << std::string(Offset * 2, ' ');
+ P->dumpPassStructure(0);
+ }
+}
+
+void PMDataManager::dumpPassArguments() const {
+ for (Pass *P : PassVector) {
+ if (PMDataManager *PMD = P->getAsPMDataManager())
+ PMD->dumpPassArguments();
+ else if (const PassInfo *PI = TPM->findAnalysisPassInfo(P->getPassID()))
+ dbgs() << " -" << PI->getPassArgument();
+ }
+}
+
+void PMDataManager::dumpPassInfo(Pass *P, enum PassDebuggingString S1,
+ enum PassDebuggingString S2, StringRef Msg) {
+ if (PassDebugging < Executions)
+ return;
+ dbgs() << "[" << std::chrono::system_clock::now() << "] " << (void *)this
+ << std::string(getDepth() * 2 + 1, ' ');
+ switch (S1) {
+ case EXECUTION_MSG:
+ dbgs() << "Executing Pass '" << P->getPassName();
+ break;
+ case MODIFICATION_MSG:
+ dbgs() << "Made Modification '" << P->getPassName();
+ break;
+ case FREEING_MSG:
+ dbgs() << " Freeing Pass '" << P->getPassName();
+ break;
+ default:
+ break;
+ }
+ switch (S2) {
+ case ON_FUNCTION_MSG:
+ dbgs() << "' on Function '" << Msg << "'...\n";
+ break;
+ case ON_MODULE_MSG:
+ dbgs() << "' on Module '" << Msg << "'...\n";
+ break;
+ case ON_REGION_MSG:
+ dbgs() << "' on Region '" << Msg << "'...\n";
+ break;
+ case ON_LOOP_MSG:
+ dbgs() << "' on Loop '" << Msg << "'...\n";
+ break;
+ case ON_CG_MSG:
+ dbgs() << "' on Call Graph Nodes '" << Msg << "'...\n";
+ break;
+ default:
+ break;
+ }
+}
+
+void PMDataManager::dumpRequiredSet(const Pass *P) const {
+ if (PassDebugging < Details)
+ return;
+
+ AnalysisUsage analysisUsage;
+ P->getAnalysisUsage(analysisUsage);
+ dumpAnalysisUsage("Required", P, analysisUsage.getRequiredSet());
+}
+
+void PMDataManager::dumpPreservedSet(const Pass *P) const {
+ if (PassDebugging < Details)
+ return;
+
+ AnalysisUsage analysisUsage;
+ P->getAnalysisUsage(analysisUsage);
+ dumpAnalysisUsage("Preserved", P, analysisUsage.getPreservedSet());
+}
+
+void PMDataManager::dumpUsedSet(const Pass *P) const {
+ if (PassDebugging < Details)
+ return;
+
+ AnalysisUsage analysisUsage;
+ P->getAnalysisUsage(analysisUsage);
+ dumpAnalysisUsage("Used", P, analysisUsage.getUsedSet());
+}
+
+void PMDataManager::dumpAnalysisUsage(
+ StringRef Msg, const Pass *P, const AnalysisUsage::VectorType &Set) const {
+ assert(PassDebugging >= Details);
+ if (Set.empty())
+ return;
+ dbgs() << (const void *)P << std::string(getDepth() * 2 + 3, ' ') << Msg
+ << " Analyses:";
+ for (unsigned i = 0; i != Set.size(); ++i) {
+ if (i)
+ dbgs() << ',';
+ const PassInfo *PInf = TPM->findAnalysisPassInfo(Set[i]);
+ if (!PInf) {
+ // Some preserved passes, such as AliasAnalysis, may not be initialized by
+ // all drivers.
+ dbgs() << " Uninitialized Pass";
+ continue;
+ }
+ dbgs() << ' ' << PInf->getPassName();
+ }
+ dbgs() << '\n';
+}
+
+/// Add RequiredPass into list of lower level passes required by pass P.
+/// RequiredPass is run on the fly by Pass Manager when P requests it
+/// through getAnalysis interface.
+/// This should be handled by specific pass manager.
+void PMDataManager::addLowerLevelRequiredPass(Pass *P, Pass *RequiredPass) {
+ if (TPM) {
+ TPM->dumpArguments();
+ TPM->dumpPasses();
+ }
+
+ // Module Level pass may required Function Level analysis info
+ // (e.g. dominator info). Pass manager uses on the fly function pass manager
+ // to provide this on demand. In that case, in Pass manager terminology,
+ // module level pass is requiring lower level analysis info managed by
+ // lower level pass manager.
+
+ // When Pass manager is not able to order required analysis info, Pass manager
+ // checks whether any lower level manager will be able to provide this
+ // analysis info on demand or not.
+#ifndef NDEBUG
+ dbgs() << "Unable to schedule '" << RequiredPass->getPassName();
+ dbgs() << "' required by '" << P->getPassName() << "'\n";
+#endif
+ llvm_unreachable("Unable to schedule pass");
+}
+
+std::tuple<Pass *, bool> PMDataManager::getOnTheFlyPass(Pass *P, AnalysisID PI,
+ Function &F) {
+ llvm_unreachable("Unable to find on the fly pass");
+}
+
+// Destructor
+PMDataManager::~PMDataManager() {
+ for (Pass *P : PassVector)
+ delete P;
+}
+
+//===----------------------------------------------------------------------===//
+// NOTE: Is this the right place to define this method ?
+// getAnalysisIfAvailable - Return analysis result or null if it doesn't exist.
+Pass *AnalysisResolver::getAnalysisIfAvailable(AnalysisID ID) const {
+ return PM.findAnalysisPass(ID, true);
+}
+
+std::tuple<Pass *, bool>
+AnalysisResolver::findImplPass(Pass *P, AnalysisID AnalysisPI, Function &F) {
+ return PM.getOnTheFlyPass(P, AnalysisPI, F);
+}
+
+namespace llvm {
+namespace legacy {
+
+//===----------------------------------------------------------------------===//
+// FunctionPassManager implementation
+
+/// Create new Function pass manager
+FunctionPassManager::FunctionPassManager(Module *m) : M(m) {
+ FPM = new legacy::FunctionPassManagerImpl();
+ // FPM is the top level manager.
+ FPM->setTopLevelManager(FPM);
+
+ AnalysisResolver *AR = new AnalysisResolver(*FPM);
+ FPM->setResolver(AR);
+}
+
+FunctionPassManager::~FunctionPassManager() { delete FPM; }
+
+void FunctionPassManager::add(Pass *P) { FPM->add(P); }
+
+/// run - Execute all of the passes scheduled for execution. Keep
+/// track of whether any of the passes modifies the function, and if
+/// so, return true.
+///
+bool FunctionPassManager::run(Function &F) {
+ handleAllErrors(F.materialize(), [&](ErrorInfoBase &EIB) {
+ report_fatal_error(Twine("Error reading bitcode file: ") + EIB.message());
+ });
+ return FPM->run(F);
+}
+
+/// doInitialization - Run all of the initializers for the function passes.
+///
+bool FunctionPassManager::doInitialization() {
+ return FPM->doInitialization(*M);
+}
+
+/// doFinalization - Run all of the finalizers for the function passes.
+///
+bool FunctionPassManager::doFinalization() { return FPM->doFinalization(*M); }
+} // namespace legacy
+} // namespace llvm
+
+/// cleanup - After running all passes, clean up pass manager cache.
+void FPPassManager::cleanup() {
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ FunctionPass *FP = getContainedPass(Index);
+ AnalysisResolver *AR = FP->getResolver();
+ assert(AR && "Analysis Resolver is not set");
+ AR->clearAnalysisImpls();
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// FPPassManager implementation
+
+char FPPassManager::ID = 0;
+/// Print passes managed by this manager
+void FPPassManager::dumpPassStructure(unsigned Offset) {
+ dbgs().indent(Offset * 2) << "FunctionPass Manager\n";
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ FunctionPass *FP = getContainedPass(Index);
+ FP->dumpPassStructure(Offset + 1);
+ dumpLastUses(FP, Offset + 1);
+ }
+}
+
+/// Execute all of the passes scheduled for execution by invoking
+/// runOnFunction method. Keep track of whether any of the passes modifies
+/// the function, and if so, return true.
+bool FPPassManager::runOnFunction(Function &F) {
+ if (F.isDeclaration())
+ return false;
+
+ bool Changed = false;
+ Module &M = *F.getParent();
+ // Collect inherited analysis from Module level pass manager.
+ populateInheritedAnalysis(TPM->activeStack);
+
+ unsigned InstrCount, FunctionSize = 0;
+ StringMap<std::pair<unsigned, unsigned>> FunctionToInstrCount;
+ bool EmitICRemark = M.shouldEmitInstrCountChangedRemark();
+ // Collect the initial size of the module.
+ if (EmitICRemark) {
+ InstrCount = initSizeRemarkInfo(M, FunctionToInstrCount);
+ FunctionSize = F.getInstructionCount();
+ }
+
+ // Store name outside of loop to avoid redundant calls.
+ const StringRef Name = F.getName();
+ llvm::TimeTraceScope FunctionScope("OptFunction", Name);
+
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ FunctionPass *FP = getContainedPass(Index);
+ bool LocalChanged = false;
+
+ // Call getPassName only when required. The call itself is fairly cheap, but
+ // still virtual and repeated calling adds unnecessary overhead.
+ llvm::TimeTraceScope PassScope(
+ "RunPass", [FP]() { return std::string(FP->getPassName()); });
+
+ // Log the pass name if PassDebugging is set to List
+ if (PassDebugging == List) {
+ errs() << "Running pass: " << FP->getPassName() << "\n";
+ }
+
+ dumpPassInfo(FP, EXECUTION_MSG, ON_FUNCTION_MSG, Name);
+ dumpRequiredSet(FP);
+
+ initializeAnalysisImpl(FP);
+
+ {
+ PassManagerPrettyStackEntry X(FP, F);
+ TimeRegion PassTimer(getPassTimer(FP));
+#ifdef EXPENSIVE_CHECKS
+ uint64_t RefHash = FP->structuralHash(F);
+#endif
+ LocalChanged |= FP->runOnFunction(F);
+
+#if defined(EXPENSIVE_CHECKS) && !defined(NDEBUG)
+ if (!LocalChanged && (RefHash != FP->structuralHash(F))) {
+ llvm::errs() << "Pass modifies its input and doesn't report it: "
+ << FP->getPassName() << "\n";
+ llvm_unreachable("Pass modifies its input and doesn't report it");
+ }
+#endif
+
+ if (EmitICRemark) {
+ unsigned NewSize = F.getInstructionCount();
+
+ // Update the size of the function, emit a remark, and update the size
+ // of the module.
+ if (NewSize != FunctionSize) {
+ int64_t Delta = static_cast<int64_t>(NewSize) -
+ static_cast<int64_t>(FunctionSize);
+ emitInstrCountChangedRemark(FP, M, Delta, InstrCount,
+ FunctionToInstrCount, &F);
+ InstrCount = static_cast<int64_t>(InstrCount) + Delta;
+ FunctionSize = NewSize;
+ }
+ }
+ }
+
+ Changed |= LocalChanged;
+ if (LocalChanged)
+ dumpPassInfo(FP, MODIFICATION_MSG, ON_FUNCTION_MSG, Name);
+ dumpPreservedSet(FP);
+ dumpUsedSet(FP);
+
+ verifyPreservedAnalysis(FP);
+ if (LocalChanged)
+ removeNotPreservedAnalysis(FP);
+ recordAvailableAnalysis(FP);
+ removeDeadPasses(FP, Name, ON_FUNCTION_MSG);
+ }
+
+ return Changed;
+}
+
+bool FPPassManager::runOnModule(Module &M) {
+ bool Changed = false;
+
+ for (Function &F : M)
+ Changed |= runOnFunction(F);
+
+ return Changed;
+}
+
+bool FPPassManager::doInitialization(Module &M) {
+ bool Changed = false;
+
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index)
+ Changed |= getContainedPass(Index)->doInitialization(M);
+
+ return Changed;
+}
+
+bool FPPassManager::doFinalization(Module &M) {
+ bool Changed = false;
+
+ for (int Index = getNumContainedPasses() - 1; Index >= 0; --Index)
+ Changed |= getContainedPass(Index)->doFinalization(M);
+
+ return Changed;
+}
+
+//===----------------------------------------------------------------------===//
+// MPPassManager implementation
+
+/// Execute all of the passes scheduled for execution by invoking
+/// runOnModule method. Keep track of whether any of the passes modifies
+/// the module, and if so, return true.
+bool MPPassManager::runOnModule(Module &M) {
+ llvm::TimeTraceScope TimeScope("OptModule", M.getName());
+
+ bool Changed = false;
+
+ // Initialize on-the-fly passes
+ for (auto &OnTheFlyManager : OnTheFlyManagers) {
+ legacy::FunctionPassManagerImpl *FPP = OnTheFlyManager.second;
+ Changed |= FPP->doInitialization(M);
+ }
+
+ // Initialize module passes
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index)
+ Changed |= getContainedPass(Index)->doInitialization(M);
+
+ unsigned InstrCount;
+ StringMap<std::pair<unsigned, unsigned>> FunctionToInstrCount;
+ bool EmitICRemark = M.shouldEmitInstrCountChangedRemark();
+ // Collect the initial size of the module.
+ if (EmitICRemark)
+ InstrCount = initSizeRemarkInfo(M, FunctionToInstrCount);
+
+ for (unsigned Index = 0; Index < getNumContainedPasses(); ++Index) {
+ ModulePass *MP = getContainedPass(Index);
+ bool LocalChanged = false;
+
+ // Log the pass name if PassDebugging is set to List
+ if (PassDebugging == List) {
+ errs() << "Running pass: " << MP->getPassName() << "\n";
+ }
+
+ dumpPassInfo(MP, EXECUTION_MSG, ON_MODULE_MSG, M.getModuleIdentifier());
+ dumpRequiredSet(MP);
+
+ initializeAnalysisImpl(MP);
+
+ {
+ PassManagerPrettyStackEntry X(MP, M);
+ TimeRegion PassTimer(getPassTimer(MP));
+
+#ifdef EXPENSIVE_CHECKS
+ uint64_t RefHash = MP->structuralHash(M);
+#endif
+
+ LocalChanged |= MP->runOnModule(M);
+
+#ifdef EXPENSIVE_CHECKS
+ assert((LocalChanged || (RefHash == MP->structuralHash(M))) &&
+ "Pass modifies its input and doesn't report it.");
+#endif
+
+ if (EmitICRemark) {
+ // Update the size of the module.
+ unsigned ModuleCount = M.getInstructionCount();
+ if (ModuleCount != InstrCount) {
+ int64_t Delta = static_cast<int64_t>(ModuleCount) -
+ static_cast<int64_t>(InstrCount);
+ emitInstrCountChangedRemark(MP, M, Delta, InstrCount,
+ FunctionToInstrCount);
+ InstrCount = ModuleCount;
+ }
+ }
+ }
+
+ Changed |= LocalChanged;
+ if (LocalChanged)
+ dumpPassInfo(MP, MODIFICATION_MSG, ON_MODULE_MSG,
+ M.getModuleIdentifier());
+ dumpPreservedSet(MP);
+ dumpUsedSet(MP);
+
+ verifyPreservedAnalysis(MP);
+ if (LocalChanged)
+ removeNotPreservedAnalysis(MP);
+ recordAvailableAnalysis(MP);
+ removeDeadPasses(MP, M.getModuleIdentifier(), ON_MODULE_MSG);
+ }
+
+ // Finalize module passes
+ for (int Index = getNumContainedPasses() - 1; Index >= 0; --Index)
+ Changed |= getContainedPass(Index)->doFinalization(M);
+
+ // Finalize on-the-fly passes
+ for (auto &OnTheFlyManager : OnTheFlyManagers) {
+ legacy::FunctionPassManagerImpl *FPP = OnTheFlyManager.second;
+ // We don't know when is the last time an on-the-fly pass is run,
+ // so we need to releaseMemory / finalize here
+ FPP->releaseMemoryOnTheFly();
+ Changed |= FPP->doFinalization(M);
+ }
+
+ return Changed;
+}
+
+/// Add RequiredPass into list of lower level passes required by pass P.
+/// RequiredPass is run on the fly by Pass Manager when P requests it
+/// through getAnalysis interface.
+void MPPassManager::addLowerLevelRequiredPass(Pass *P, Pass *RequiredPass) {
+ assert(RequiredPass && "No required pass?");
+ assert(P->getPotentialPassManagerType() == PMT_ModulePassManager &&
+ "Unable to handle Pass that requires lower level Analysis pass");
+ assert((P->getPotentialPassManagerType() <
+ RequiredPass->getPotentialPassManagerType()) &&
+ "Unable to handle Pass that requires lower level Analysis pass");
+
+ legacy::FunctionPassManagerImpl *FPP = OnTheFlyManagers[P];
+ if (!FPP) {
+ FPP = new legacy::FunctionPassManagerImpl();
+ // FPP is the top level manager.
+ FPP->setTopLevelManager(FPP);
+
+ OnTheFlyManagers[P] = FPP;
+ }
+ const PassInfo *RequiredPassPI =
+ TPM->findAnalysisPassInfo(RequiredPass->getPassID());
+
+ Pass *FoundPass = nullptr;
+ if (RequiredPassPI && RequiredPassPI->isAnalysis()) {
+ FoundPass =
+ ((PMTopLevelManager *)FPP)->findAnalysisPass(RequiredPass->getPassID());
+ }
+ if (!FoundPass) {
+ FoundPass = RequiredPass;
+ // This should be guaranteed to add RequiredPass to the passmanager given
+ // that we checked for an available analysis above.
+ FPP->add(RequiredPass);
+ }
+ // Register P as the last user of FoundPass or RequiredPass.
+ SmallVector<Pass *, 1> LU;
+ LU.push_back(FoundPass);
+ FPP->setLastUser(LU, P);
+}
+
+/// Return function pass corresponding to PassInfo PI, that is
+/// required by module pass MP. Instantiate analysis pass, by using
+/// its runOnFunction() for function F.
+std::tuple<Pass *, bool> MPPassManager::getOnTheFlyPass(Pass *MP, AnalysisID PI,
+ Function &F) {
+ legacy::FunctionPassManagerImpl *FPP = OnTheFlyManagers[MP];
+ assert(FPP && "Unable to find on the fly pass");
+
+ FPP->releaseMemoryOnTheFly();
+ bool Changed = FPP->run(F);
+ return std::make_tuple(((PMTopLevelManager *)FPP)->findAnalysisPass(PI),
+ Changed);
+}
+
+namespace llvm {
+namespace legacy {
+
+//===----------------------------------------------------------------------===//
+// PassManager implementation
+
+/// Create new pass manager
+PassManager::PassManager() {
+ PM = new PassManagerImpl();
+ // PM is the top level manager
+ PM->setTopLevelManager(PM);
+}
+
+PassManager::~PassManager() { delete PM; }
+
+void PassManager::add(Pass *P) { PM->add(P); }
+
+/// run - Execute all of the passes scheduled for execution. Keep track of
+/// whether any of the passes modifies the module, and if so, return true.
+bool PassManager::run(Module &M) { return PM->run(M); }
+} // namespace legacy
+} // namespace llvm
+
+//===----------------------------------------------------------------------===//
+// PMStack implementation
+//
+
+// Pop Pass Manager from the stack and clear its analysis info.
+void PMStack::pop() {
+
+ PMDataManager *Top = this->top();
+ Top->initializeAnalysisInfo();
+
+ S.pop_back();
+}
+
+// Push PM on the stack and set its top level manager.
+void PMStack::push(PMDataManager *PM) {
+ assert(PM && "Unable to push. Pass Manager expected");
+ assert(PM->getDepth() == 0 && "Pass Manager depth set too early");
+
+ if (!this->empty()) {
+ assert(PM->getPassManagerType() > this->top()->getPassManagerType() &&
+ "pushing bad pass manager to PMStack");
+ PMTopLevelManager *TPM = this->top()->getTopLevelManager();
+
+ assert(TPM && "Unable to find top level manager");
+ TPM->addIndirectPassManager(PM);
+ PM->setTopLevelManager(TPM);
+ PM->setDepth(this->top()->getDepth() + 1);
+ } else {
+ assert((PM->getPassManagerType() == PMT_ModulePassManager ||
+ PM->getPassManagerType() == PMT_FunctionPassManager) &&
+ "pushing bad pass manager to PMStack");
+ PM->setDepth(1);
+ }
+
+ S.push_back(PM);
+}
+
+// Dump content of the pass manager stack.
+LLVM_DUMP_METHOD void PMStack::dump() const {
+ for (PMDataManager *Manager : S)
+ dbgs() << Manager->getAsPass()->getPassName() << ' ';
+
+ if (!S.empty())
+ dbgs() << '\n';
+}
+
+/// Find appropriate Module Pass Manager in the PM Stack and
+/// add self into that manager.
+void ModulePass::assignPassManager(PMStack &PMS,
+ PassManagerType PreferredType) {
+ // Find Module Pass Manager
+ PassManagerType T;
+ while ((T = PMS.top()->getPassManagerType()) > PMT_ModulePassManager &&
+ T != PreferredType)
+ PMS.pop();
+ PMS.top()->add(this);
+}
+
+/// Find appropriate Function Pass Manager or Call Graph Pass Manager
+/// in the PM Stack and add self into that manager.
+void FunctionPass::assignPassManager(PMStack &PMS,
+ PassManagerType /*PreferredType*/) {
+ // Find Function Pass Manager
+ PMDataManager *PM;
+ while (PM = PMS.top(), PM->getPassManagerType() > PMT_FunctionPassManager)
+ PMS.pop();
+
+ // Create new Function Pass Manager if needed.
+ if (PM->getPassManagerType() != PMT_FunctionPassManager) {
+ // [1] Create new Function Pass Manager
+ auto *FPP = new FPPassManager;
+ FPP->populateInheritedAnalysis(PMS);
+
+ // [2] Set up new manager's top level manager
+ PM->getTopLevelManager()->addIndirectPassManager(FPP);
+
+ // [3] Assign manager to manage this new manager. This may create
+ // and push new managers into PMS
+ FPP->assignPassManager(PMS, PM->getPassManagerType());
+
+ // [4] Push new manager into PMS
+ PMS.push(FPP);
+ PM = FPP;
+ }
+
+ // Assign FPP as the manager of this pass.
+ PM->add(this);
+}
+
+legacy::PassManagerBase::~PassManagerBase() = default;
\ No newline at end of file
diff --git a/O2_vs_O3_comparison_report.txt b/O2_vs_O3_comparison_report.txt
new file mode 100644
index 0000000000000..fbdd170d486eb
--- /dev/null
+++ b/O2_vs_O3_comparison_report.txt
@@ -0,0 +1,566 @@
+╔══════════════════════════════════════════════════════════════════════════════╗
+║ LLVM O2 vs O3 OPTIMIZATION COMPARISON ║
+║ Pass Analysis Report ║
+╚══════════════════════════════════════════════════════════════════════════════╝
+
+Report Generated: Wed 18 Jun 2025 01:10:01 IST
+LLVM Version: clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)
+Test File: test.c
+
+═══════════════════════════════════════════════════════════════════════════════
+ EXECUTIVE SUMMARY
+═══════════════════════════════════════════════════════════════════════════════
+
+• O2 Optimization Level: 210 total passes
+• O3 Optimization Level: 220 total passes
+• Additional passes in O3: 10
+• Common passes: 210
+• O2-only passes: 0
+• O3-only passes: 10
+
+Key Finding: O3 adds 4.7% more optimization passes compared to O2
+
+
+═══════════════════════════════════════════════════════════════════════════════
+ DETAILED ANALYSIS
+═══════════════════════════════════════════════════════════════════════════════
+
+┌─ PASSES UNIQUE TO O3 (Additional Optimizations) ──────────────────────────┐
+│ These passes run only at O3 level, providing more aggressive optimization │
+│ │
+│ 1 AArch64 load / store optimization pass
+│ 2 Block Frequency Analysis
+│ 3 Branch Probability Analysis
+│ 4 Lazy Block Frequency Analysis
+│ 5 Lazy Branch Probability Analysis
+│ 6 Machine Copy Propagation Pass
+│ 7 Natural Loop Information
+│ 8 Optimization Remark Emitter
+│ 9 Optimize selects
+│ 10 Post-Dominator Tree Construction
+└────────────────────────────────────────────────────────────────────────────┘
+
+┌─ PASS FREQUENCY ANALYSIS ─────────────────────────────────────────────────┐
+│ How many times each pass runs (some passes may run multiple times) │
+│ │
+│ O2 Pass Frequencies: │
+│ Lazy 7 times
+│ Dominator 7 times
+│ Natural 6 times
+│ MachineDominator 6 times
+│ Function 6 times
+│ Machine 5 times
+│ Lazy 5 times
+│ Lazy 5 times
+│ Function 5 times
+│ Basic 5 times
+│ │
+│ O3 Pass Frequencies: │
+│ Natural 7 times
+│ Lazy 7 times
+│ Dominator 7 times
+│ MachineDominator 6 times
+│ Lazy 6 times
+│ Lazy 6 times
+│ Function 6 times
+│ Machine 5 times
+│ Function 5 times
+│ Basic 5 times
+└────────────────────────────────────────────────────────────────────────────┘
+
+┌─ PASS CATEGORIZATION (O3-only passes) ────────────────────────────────────┐
+│ Categorizing O3-specific passes by optimization type │
+│ │
+│ Loop Optimizations:
+│ Natural Loop Information
+│
+│ Memory Optimizations:
+│ AArch64 load / store optimization pass
+│
+└────────────────────────────────────────────────────────────────────────────┘
+
+┌─ COMPLETE PASS EXECUTION ORDER ───────────────────────────────────────────┐
+│ Side-by-side comparison of pass execution order │
+│ │
+│ O2 Passes (in execution order): │
+│ ════════════════════════════════ │
+│ 1 Pre-ISel Intrinsic Lowering
+│ 2 Function Pass Manager
+│ 3 Expand large div/rem
+│ 4 Expand fp
+│ 5 Expand Atomic instructions
+│ 6 SVE intrinsics optimizations
+│ 7 Function Pass Manager
+│ 8 Simplify the CFG
+│ 9 Dominator Tree Construction
+│ 10 Natural Loop Information
+│ 11 Canonicalize natural loops
+│ 12 Lazy Branch Probability Analysis
+│ 13 Lazy Block Frequency Analysis
+│ 14 Optimization Remark Emitter
+│ 15 Scalar Evolution Analysis
+│ 16 Loop Data Prefetch
+│ 17 Falkor HW Prefetch Fix
+│ 18 Basic Alias Analysis (stateless AA impl)
+│ 19 Canonicalize natural loops
+│ 20 Loop Pass Manager
+│ 21 Basic Alias Analysis (stateless AA impl)
+│ 22 Function Alias Analysis Results
+│ 23 Merge contiguous icmps into a memcmp
+│ 24 Natural Loop Information
+│ 25 Lazy Branch Probability Analysis
+│ 26 Lazy Block Frequency Analysis
+│ 27 Expand memcmp() to load/stores
+│ 28 Lower Garbage Collection Instructions
+│ 29 Shadow Stack GC Lowering
+│ 30 Lower @llvm.global_dtors via `__cxa_atexit`
+│ 31 Function Pass Manager
+│ 32 Remove unreachable blocks from the CFG
+│ 33 Dominator Tree Construction
+│ 34 Natural Loop Information
+│ 35 Post-Dominator Tree Construction
+│ 36 Branch Probability Analysis
+│ 37 Block Frequency Analysis
+│ 38 Constant Hoisting
+│ 39 Replace intrinsics with calls to vector library
+│ 40 Lazy Branch Probability Analysis
+│ 41 Lazy Block Frequency Analysis
+│ 42 Optimization Remark Emitter
+│ 43 Partially inline calls to library functions
+│ 44 Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+│ 45 Scalarize Masked Memory Intrinsics
+│ 46 Expand reduction intrinsics
+│ 47 Stack Safety Analysis
+│ 48 Function Pass Manager
+│ 49 Dominator Tree Construction
+│ 50 Basic Alias Analysis (stateless AA impl)
+│ 51 Function Alias Analysis Results
+│ 52 Natural Loop Information
+│ 53 Lazy Branch Probability Analysis
+│ 54 Lazy Block Frequency Analysis
+│ 55 Optimization Remark Emitter
+│ 56 AArch64 Stack Tagging
+│ 57 Complex Deinterleaving Pass
+│ 58 Function Alias Analysis Results
+│ 59 Memory SSA
+│ 60 Interleaved Load Combine Pass
+│ 61 Dominator Tree Construction
+│ 62 Interleaved Access Pass
+│ 63 SME ABI Pass
+│ 64 Dominator Tree Construction
+│ 65 Natural Loop Information
+│ 66 Type Promotion
+│ 67 CodeGen Prepare
+│ 68 Dominator Tree Construction
+│ 69 Exception handling preparation
+│ 70 AArch64 Promote Constant
+│ 71 Function Pass Manager
+│ 72 Merge internal globals
+│ 73 Dominator Tree Construction
+│ 74 Basic Alias Analysis (stateless AA impl)
+│ 75 Function Alias Analysis Results
+│ 76 ObjC ARC contraction
+│ 77 Prepare callbr
+│ 78 Safe Stack instrumentation pass
+│ 79 Insert stack protectors
+│ 80 Basic Alias Analysis (stateless AA impl)
+│ 81 Function Alias Analysis Results
+│ 82 Natural Loop Information
+│ 83 Post-Dominator Tree Construction
+│ 84 Branch Probability Analysis
+│ 85 Assignment Tracking Analysis
+│ 86 Lazy Branch Probability Analysis
+│ 87 Lazy Block Frequency Analysis
+│ 88 AArch64 Instruction Selection
+│ 89 Finalize ISel and expand pseudo-instructions
+│ 90 SME Peephole Optimization pass
+│ 91 Lazy Machine Block Frequency Analysis
+│ 92 Early Tail Duplication
+│ 93 Optimize machine instruction PHIs
+│ 94 Slot index numbering
+│ 95 Merge disjoint stack slots
+│ 96 Local Stack Slot Allocation
+│ 97 Remove dead machine instructions
+│ 98 MachineDominator Tree Construction
+│ 99 AArch64 Condition Optimizer
+│ 100 Machine Natural Loop Construction
+│ 101 Machine Trace Metrics
+│ 102 AArch64 Conditional Compares
+│ 103 Lazy Machine Block Frequency Analysis
+│ 104 Machine InstCombiner
+│ 105 AArch64 Conditional Branch Tuning
+│ 106 Machine Trace Metrics
+│ 107 Early If-Conversion
+│ 108 AArch64 Store Pair Suppression
+│ 109 AArch64 SIMD instructions optimization pass
+│ 110 AArch64 Stack Tagging PreRA
+│ 111 MachineDominator Tree Construction
+│ 112 Machine Natural Loop Construction
+│ 113 Machine Block Frequency Analysis
+│ 114 Early Machine Loop Invariant Code Motion
+│ 115 MachineDominator Tree Construction
+│ 116 Machine Block Frequency Analysis
+│ 117 Machine Common Subexpression Elimination
+│ 118 MachinePostDominator Tree Construction
+│ 119 Machine Cycle Info Analysis
+│ 120 Machine code sinking
+│ 121 Peephole Optimizations
+│ 122 Remove dead machine instructions
+│ 123 AArch64 MI Peephole Optimization pass
+│ 124 AArch64 Dead register definitions
+│ 125 Detect Dead Lanes
+│ 126 Init Undef Pass
+│ 127 Process Implicit Definitions
+│ 128 Remove unreachable machine basic blocks
+│ 129 Live Variable Analysis
+│ 130 Eliminate PHI nodes for register allocation
+│ 131 Two-Address instruction pass
+│ 132 MachineDominator Tree Construction
+│ 133 Slot index numbering
+│ 134 Live Interval Analysis
+│ 135 Register Coalescer
+│ 136 Rename Disconnected Subregister Components
+│ 137 Machine Instruction Scheduler
+│ 138 AArch64 Post Coalescer pass
+│ 139 Machine Block Frequency Analysis
+│ 140 Debug Variable Analysis
+│ 141 Live Stack Slot Analysis
+│ 142 Virtual Register Map
+│ 143 Live Register Matrix
+│ 144 Bundle Machine CFG Edges
+│ 145 Spill Code Placement Analysis
+│ 146 Lazy Machine Block Frequency Analysis
+│ 147 Machine Optimization Remark Emitter
+│ 148 Greedy Register Allocator
+│ 149 Virtual Register Rewriter
+│ 150 Register Allocation Pass Scoring
+│ 151 Stack Slot Coloring
+│ 152 Machine Copy Propagation Pass
+│ 153 Machine Loop Invariant Code Motion
+│ 154 AArch64 Redundant Copy Elimination
+│ 155 A57 FP Anti-dependency breaker
+│ 156 Remove Redundant DEBUG_VALUE analysis
+│ 157 Fixup Statepoint Caller Saved
+│ 158 PostRA Machine Sink
+│ 159 MachineDominator Tree Construction
+│ 160 Machine Natural Loop Construction
+│ 161 Machine Block Frequency Analysis
+│ 162 MachinePostDominator Tree Construction
+│ 163 Lazy Machine Block Frequency Analysis
+│ 164 Machine Optimization Remark Emitter
+│ 165 Shrink Wrapping analysis
+│ 166 Prologue/Epilogue Insertion & Frame Finalization
+│ 167 Machine Late Instructions Cleanup Pass
+│ 168 Control Flow Optimizer
+│ 169 Lazy Machine Block Frequency Analysis
+│ 170 Tail Duplication
+│ 171 Machine Copy Propagation Pass
+│ 172 Post-RA pseudo instruction expansion pass
+│ 173 AArch64 pseudo instruction expansion pass
+│ 174 AArch64 load / store optimization pass
+│ 175 Insert KCFI indirect call checks
+│ 176 AArch64 speculation hardening pass
+│ 177 MachineDominator Tree Construction
+│ 178 Machine Natural Loop Construction
+│ 179 Falkor HW Prefetch Fix Late Phase
+│ 180 PostRA Machine Instruction Scheduler
+│ 181 Analyze Machine Code For Garbage Collection
+│ 182 Machine Block Frequency Analysis
+│ 183 MachinePostDominator Tree Construction
+│ 184 Branch Probability Basic Block Placement
+│ 185 Insert fentry calls
+│ 186 Insert XRay ops
+│ 187 Implement the 'patchable-function' attribute
+│ 188 Workaround A53 erratum 835769 pass
+│ 189 AArch64 Collect Linker Optimization Hint (LOH)
+│ 190 Contiguously Lay Out Funclets
+│ 191 Remove Loads Into Fake Uses
+│ 192 StackMap Liveness Analysis
+│ 193 Live DEBUG_VALUE analysis
+│ 194 Machine Sanitizer Binary Metadata
+│ 195 Machine Outliner
+│ 196 Function Pass Manager
+│ 197 AArch64 sls hardening pass
+│ 198 AArch64 Pointer Authentication
+│ 199 AArch64 Branch Targets
+│ 200 Branch relaxation pass
+│ 201 AArch64 Compress Jump Tables
+│ 202 Insert CFI remember/restore state instructions
+│ 203 Lazy Machine Block Frequency Analysis
+│ 204 Machine Optimization Remark Emitter
+│ 205 Stack Frame Layout Analysis
+│ 206 Unpack machine instruction bundles
+│ 207 Lazy Machine Block Frequency Analysis
+│ 208 Machine Optimization Remark Emitter
+│ 209 AArch64 Assembly Printer
+│ 210 Free MachineFunction
+│ │
+│ O3 Passes (in execution order): │
+│ ════════════════════════════════ │
+│ 1 Pre-ISel Intrinsic Lowering
+│ 2 Function Pass Manager
+│ 3 Expand large div/rem
+│ 4 Expand fp
+│ 5 Expand Atomic instructions
+│ 6 SVE intrinsics optimizations
+│ 7 Function Pass Manager
+│ 8 Simplify the CFG
+│ 9 Dominator Tree Construction
+│ 10 Natural Loop Information
+│ 11 Canonicalize natural loops
+│ 12 Lazy Branch Probability Analysis
+│ 13 Lazy Block Frequency Analysis
+│ 14 Optimization Remark Emitter
+│ 15 Scalar Evolution Analysis
+│ 16 Loop Data Prefetch
+│ 17 Falkor HW Prefetch Fix
+│ 18 Basic Alias Analysis (stateless AA impl)
+│ 19 Canonicalize natural loops
+│ 20 Loop Pass Manager
+│ 21 Basic Alias Analysis (stateless AA impl)
+│ 22 Function Alias Analysis Results
+│ 23 Merge contiguous icmps into a memcmp
+│ 24 Natural Loop Information
+│ 25 Lazy Branch Probability Analysis
+│ 26 Lazy Block Frequency Analysis
+│ 27 Expand memcmp() to load/stores
+│ 28 Lower Garbage Collection Instructions
+│ 29 Shadow Stack GC Lowering
+│ 30 Lower @llvm.global_dtors via `__cxa_atexit`
+│ 31 Function Pass Manager
+│ 32 Remove unreachable blocks from the CFG
+│ 33 Dominator Tree Construction
+│ 34 Natural Loop Information
+│ 35 Post-Dominator Tree Construction
+│ 36 Branch Probability Analysis
+│ 37 Block Frequency Analysis
+│ 38 Constant Hoisting
+│ 39 Replace intrinsics with calls to vector library
+│ 40 Lazy Branch Probability Analysis
+│ 41 Lazy Block Frequency Analysis
+│ 42 Optimization Remark Emitter
+│ 43 Partially inline calls to library functions
+│ 44 Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+│ 45 Scalarize Masked Memory Intrinsics
+│ 46 Expand reduction intrinsics
+│ 47 Natural Loop Information
+│ 48 Post-Dominator Tree Construction
+│ 49 Branch Probability Analysis
+│ 50 Block Frequency Analysis
+│ 51 Lazy Branch Probability Analysis
+│ 52 Lazy Block Frequency Analysis
+│ 53 Optimization Remark Emitter
+│ 54 Optimize selects
+│ 55 Stack Safety Analysis
+│ 56 Function Pass Manager
+│ 57 Dominator Tree Construction
+│ 58 Basic Alias Analysis (stateless AA impl)
+│ 59 Function Alias Analysis Results
+│ 60 Natural Loop Information
+│ 61 Lazy Branch Probability Analysis
+│ 62 Lazy Block Frequency Analysis
+│ 63 Optimization Remark Emitter
+│ 64 AArch64 Stack Tagging
+│ 65 Complex Deinterleaving Pass
+│ 66 Function Alias Analysis Results
+│ 67 Memory SSA
+│ 68 Interleaved Load Combine Pass
+│ 69 Dominator Tree Construction
+│ 70 Interleaved Access Pass
+│ 71 SME ABI Pass
+│ 72 Dominator Tree Construction
+│ 73 Natural Loop Information
+│ 74 Type Promotion
+│ 75 CodeGen Prepare
+│ 76 Dominator Tree Construction
+│ 77 Exception handling preparation
+│ 78 AArch64 Promote Constant
+│ 79 Function Pass Manager
+│ 80 Merge internal globals
+│ 81 Dominator Tree Construction
+│ 82 Basic Alias Analysis (stateless AA impl)
+│ 83 Function Alias Analysis Results
+│ 84 ObjC ARC contraction
+│ 85 Prepare callbr
+│ 86 Safe Stack instrumentation pass
+│ 87 Insert stack protectors
+│ 88 Basic Alias Analysis (stateless AA impl)
+│ 89 Function Alias Analysis Results
+│ 90 Natural Loop Information
+│ 91 Post-Dominator Tree Construction
+│ 92 Branch Probability Analysis
+│ 93 Assignment Tracking Analysis
+│ 94 Lazy Branch Probability Analysis
+│ 95 Lazy Block Frequency Analysis
+│ 96 AArch64 Instruction Selection
+│ 97 Finalize ISel and expand pseudo-instructions
+│ 98 SME Peephole Optimization pass
+│ 99 Lazy Machine Block Frequency Analysis
+│ 100 Early Tail Duplication
+│ 101 Optimize machine instruction PHIs
+│ 102 Slot index numbering
+│ 103 Merge disjoint stack slots
+│ 104 Local Stack Slot Allocation
+│ 105 Remove dead machine instructions
+│ 106 MachineDominator Tree Construction
+│ 107 AArch64 Condition Optimizer
+│ 108 Machine Natural Loop Construction
+│ 109 Machine Trace Metrics
+│ 110 AArch64 Conditional Compares
+│ 111 Lazy Machine Block Frequency Analysis
+│ 112 Machine InstCombiner
+│ 113 AArch64 Conditional Branch Tuning
+│ 114 Machine Trace Metrics
+│ 115 Early If-Conversion
+│ 116 AArch64 Store Pair Suppression
+│ 117 AArch64 SIMD instructions optimization pass
+│ 118 AArch64 Stack Tagging PreRA
+│ 119 MachineDominator Tree Construction
+│ 120 Machine Natural Loop Construction
+│ 121 Machine Block Frequency Analysis
+│ 122 Early Machine Loop Invariant Code Motion
+│ 123 MachineDominator Tree Construction
+│ 124 Machine Block Frequency Analysis
+│ 125 Machine Common Subexpression Elimination
+│ 126 MachinePostDominator Tree Construction
+│ 127 Machine Cycle Info Analysis
+│ 128 Machine code sinking
+│ 129 Peephole Optimizations
+│ 130 Remove dead machine instructions
+│ 131 AArch64 MI Peephole Optimization pass
+│ 132 AArch64 Dead register definitions
+│ 133 Detect Dead Lanes
+│ 134 Init Undef Pass
+│ 135 Process Implicit Definitions
+│ 136 Remove unreachable machine basic blocks
+│ 137 Live Variable Analysis
+│ 138 Eliminate PHI nodes for register allocation
+│ 139 Two-Address instruction pass
+│ 140 MachineDominator Tree Construction
+│ 141 Slot index numbering
+│ 142 Live Interval Analysis
+│ 143 Register Coalescer
+│ 144 Rename Disconnected Subregister Components
+│ 145 Machine Instruction Scheduler
+│ 146 AArch64 Post Coalescer pass
+│ 147 Machine Block Frequency Analysis
+│ 148 Debug Variable Analysis
+│ 149 Live Stack Slot Analysis
+│ 150 Virtual Register Map
+│ 151 Live Register Matrix
+│ 152 Bundle Machine CFG Edges
+│ 153 Spill Code Placement Analysis
+│ 154 Lazy Machine Block Frequency Analysis
+│ 155 Machine Optimization Remark Emitter
+│ 156 Greedy Register Allocator
+│ 157 Virtual Register Rewriter
+│ 158 Register Allocation Pass Scoring
+│ 159 Stack Slot Coloring
+│ 160 Machine Copy Propagation Pass
+│ 161 Machine Loop Invariant Code Motion
+│ 162 AArch64 Redundant Copy Elimination
+│ 163 A57 FP Anti-dependency breaker
+│ 164 Remove Redundant DEBUG_VALUE analysis
+│ 165 Fixup Statepoint Caller Saved
+│ 166 PostRA Machine Sink
+│ 167 MachineDominator Tree Construction
+│ 168 Machine Natural Loop Construction
+│ 169 Machine Block Frequency Analysis
+│ 170 MachinePostDominator Tree Construction
+│ 171 Lazy Machine Block Frequency Analysis
+│ 172 Machine Optimization Remark Emitter
+│ 173 Shrink Wrapping analysis
+│ 174 Prologue/Epilogue Insertion & Frame Finalization
+│ 175 Machine Late Instructions Cleanup Pass
+│ 176 Control Flow Optimizer
+│ 177 Lazy Machine Block Frequency Analysis
+│ 178 Tail Duplication
+│ 179 Machine Copy Propagation Pass
+│ 180 Post-RA pseudo instruction expansion pass
+│ 181 AArch64 pseudo instruction expansion pass
+│ 182 AArch64 load / store optimization pass
+│ 183 Insert KCFI indirect call checks
+│ 184 AArch64 speculation hardening pass
+│ 185 MachineDominator Tree Construction
+│ 186 Machine Natural Loop Construction
+│ 187 Falkor HW Prefetch Fix Late Phase
+│ 188 PostRA Machine Instruction Scheduler
+│ 189 Analyze Machine Code For Garbage Collection
+│ 190 Machine Block Frequency Analysis
+│ 191 MachinePostDominator Tree Construction
+│ 192 Branch Probability Basic Block Placement
+│ 193 Insert fentry calls
+│ 194 Insert XRay ops
+│ 195 Implement the 'patchable-function' attribute
+│ 196 AArch64 load / store optimization pass
+│ 197 Machine Copy Propagation Pass
+│ 198 Workaround A53 erratum 835769 pass
+│ 199 AArch64 Collect Linker Optimization Hint (LOH)
+│ 200 Contiguously Lay Out Funclets
+│ 201 Remove Loads Into Fake Uses
+│ 202 StackMap Liveness Analysis
+│ 203 Live DEBUG_VALUE analysis
+│ 204 Machine Sanitizer Binary Metadata
+│ 205 Machine Outliner
+│ 206 Function Pass Manager
+│ 207 AArch64 sls hardening pass
+│ 208 AArch64 Pointer Authentication
+│ 209 AArch64 Branch Targets
+│ 210 Branch relaxation pass
+│ 211 AArch64 Compress Jump Tables
+│ 212 Insert CFI remember/restore state instructions
+│ 213 Lazy Machine Block Frequency Analysis
+│ 214 Machine Optimization Remark Emitter
+│ 215 Stack Frame Layout Analysis
+│ 216 Unpack machine instruction bundles
+│ 217 Lazy Machine Block Frequency Analysis
+│ 218 Machine Optimization Remark Emitter
+│ 219 AArch64 Assembly Printer
+│ 220 Free MachineFunction
+└────────────────────────────────────────────────────────────────────────────┘
+
+═══════════════════════════════════════════════════════════════════════════════
+ PERFORMANCE IMPLICATIONS
+═══════════════════════════════════════════════════════════════════════════════
+
+Based on the pass analysis:
+
+COMPILATION TIME:
+• O3 requires more compilation time due to additional optimization passes
+• The extra passes in O3 perform more complex analysis and transformations
+
+RUNTIME PERFORMANCE:
+• O3's additional passes typically result in better runtime performance
+• Common O3 improvements include:
+ - More aggressive function inlining
+ - Better loop optimizations (unrolling, vectorization)
+ - More sophisticated dead code elimination
+ - Enhanced constant propagation and folding
+
+TRADE-OFFS:
+• O2: Balanced optimization (good performance, reasonable compile time)
+• O3: Maximum optimization (best performance, longer compile time)
+
+
+═══════════════════════════════════════════════════════════════════════════════
+ RECOMMENDATIONS
+═══════════════════════════════════════════════════════════════════════════════
+
+FOR DEVELOPMENT:
+• Use O2 for faster compilation during development cycles
+• Switch to O3 for production builds where runtime performance is critical
+
+FOR PRODUCTION:
+• Use O3 when maximum runtime performance is required
+• Consider O2 if compilation time is a constraint in CI/CD pipelines
+
+FOR DEBUGGING:
+• Use this report to understand which optimizations are applied
+• Compare with -O0 and -O1 to see the full optimization progression
+
+
+═══════════════════════════════════════════════════════════════════════════════
+ END OF REPORT
+═══════════════════════════════════════════════════════════════════════════════
+
+Generated by LLVM Pass Analysis Tool
diff --git a/generate_o2_o3_report.sh b/generate_o2_o3_report.sh
new file mode 100644
index 0000000000000..360993313327b
--- /dev/null
+++ b/generate_o2_o3_report.sh
@@ -0,0 +1,284 @@
+#!/bin/bash
+
+# O2 vs O3 Pass Comparison Report Generator
+# Generates a detailed report comparing optimization passes between O2 and O3
+
+REPORT_FILE="O2_vs_O3_comparison_report.txt"
+TEST_FILE="test.c"
+
+echo "Generating O2 vs O3 Pass Comparison Report..."
+
+# Check if test file exists
+if [ ! -f "$TEST_FILE" ]; then
+ echo "Warning: $TEST_FILE not found. Creating a sample test file..."
+ cat > "$TEST_FILE" << 'EOF'
+int main() {
+ int a = 5;
+ int b = 10;
+ int c = a + b;
+
+ // Dead code that should be eliminated
+ int dead1 = 100;
+ int dead2 = 200;
+ int dead3 = dead1 + dead2; // This is never used
+
+ // Redundant calculations
+ int x = a + b; // Same as c
+ int y = 5 + 10; // Constant folding opportunity
+
+ // Unused loop
+ for (int i = 0; i < 10; i++) {
+ int temp = i * 2; // Dead code in loop
+ }
+
+ return c;
+}
+EOF
+fi
+
+# Generate pass lists for O2 and O3
+echo "Collecting O2 pass information..."
+./bin/clang -O2 -mllvm -debug-pass=List "$TEST_FILE" 2>&1 | grep "^Running pass:" > o2_passes_raw.txt
+
+echo "Collecting O3 pass information..."
+./bin/clang -O3 -mllvm -debug-pass=List "$TEST_FILE" 2>&1 | grep "^Running pass:" > o3_passes_raw.txt
+
+# Clean the pass names (remove "Running pass: " prefix)
+sed 's/Running pass: //' o2_passes_raw.txt | sort > o2_passes_clean.txt
+sed 's/Running pass: //' o3_passes_raw.txt | sort > o3_passes_clean.txt
+
+# Start generating the report
+cat > "$REPORT_FILE" << 'EOF'
+╔══════════════════════════════════════════════════════════════════════════════╗
+║ LLVM O2 vs O3 OPTIMIZATION COMPARISON ║
+║ Pass Analysis Report ║
+╚══════════════════════════════════════════════════════════════════════════════╝
+
+EOF
+
+# Add metadata
+echo "Report Generated: $(date)" >> "$REPORT_FILE"
+echo "LLVM Version: $(./bin/clang --version | head -1)" >> "$REPORT_FILE"
+echo "Test File: $TEST_FILE" >> "$REPORT_FILE"
+echo "" >> "$REPORT_FILE"
+
+# Calculate statistics
+O2_COUNT=$(wc -l < o2_passes_raw.txt)
+O3_COUNT=$(wc -l < o3_passes_raw.txt)
+COMMON_COUNT=$(comm -12 o2_passes_clean.txt o3_passes_clean.txt | wc -l)
+O2_ONLY_COUNT=$(comm -23 o2_passes_clean.txt o3_passes_clean.txt | wc -l)
+O3_ONLY_COUNT=$(comm -13 o2_passes_clean.txt o3_passes_clean.txt | wc -l)
+
+# Add executive summary
+cat >> "$REPORT_FILE" << EOF
+═══════════════════════════════════════════════════════════════════════════════
+ EXECUTIVE SUMMARY
+═══════════════════════════════════════════════════════════════════════════════
+
+• O2 Optimization Level: $O2_COUNT total passes
+• O3 Optimization Level: $O3_COUNT total passes
+• Additional passes in O3: $(($O3_COUNT - $O2_COUNT))
+• Common passes: $COMMON_COUNT
+• O2-only passes: $O2_ONLY_COUNT
+• O3-only passes: $O3_ONLY_COUNT
+
+Key Finding: O3 adds $(echo "scale=1; (($O3_COUNT - $O2_COUNT) * 100.0) / $O2_COUNT" | bc -l)% more optimization passes compared to O2
+
+EOF
+
+# Detailed analysis section
+cat >> "$REPORT_FILE" << 'EOF'
+
+═══════════════════════════════════════════════════════════════════════════════
+ DETAILED ANALYSIS
+═══════════════════════════════════════════════════════════════════════════════
+
+EOF
+
+# O3-only passes (what's NEW in O3)
+echo "┌─ PASSES UNIQUE TO O3 (Additional Optimizations) ──────────────────────────┐" >> "$REPORT_FILE"
+echo "│ These passes run only at O3 level, providing more aggressive optimization │" >> "$REPORT_FILE"
+echo "│ │" >> "$REPORT_FILE"
+
+if [ $O3_ONLY_COUNT -gt 0 ]; then
+ comm -13 o2_passes_clean.txt o3_passes_clean.txt | nl -nln | sed 's/^/│ /' >> "$REPORT_FILE"
+else
+ echo "│ No O3-specific passes found │" >> "$REPORT_FILE"
+fi
+
+echo "└────────────────────────────────────────────────────────────────────────────┘" >> "$REPORT_FILE"
+echo "" >> "$REPORT_FILE"
+
+# O2-only passes (if any)
+if [ $O2_ONLY_COUNT -gt 0 ]; then
+ echo "┌─ PASSES UNIQUE TO O2 (Not in O3) ─────────────────────────────────────────┐" >> "$REPORT_FILE"
+ echo "│ These passes run in O2 but not O3 (unusual, may indicate pass reordering) │" >> "$REPORT_FILE"
+ echo "│ │" >> "$REPORT_FILE"
+ comm -23 o2_passes_clean.txt o3_passes_clean.txt | nl -nln | sed 's/^/│ /' >> "$REPORT_FILE"
+ echo "└────────────────────────────────────────────────────────────────────────────┘" >> "$REPORT_FILE"
+ echo "" >> "$REPORT_FILE"
+fi
+
+# Pass frequency analysis
+echo "┌─ PASS FREQUENCY ANALYSIS ─────────────────────────────────────────────────┐" >> "$REPORT_FILE"
+echo "│ How many times each pass runs (some passes may run multiple times) │" >> "$REPORT_FILE"
+echo "│ │" >> "$REPORT_FILE"
+
+# Count pass frequencies for O2
+echo "│ O2 Pass Frequencies: │" >> "$REPORT_FILE"
+sed 's/Running pass: //' o2_passes_raw.txt | sort | uniq -c | sort -nr | head -10 | \
+ awk '{printf "│ %-50s %s times\n", $2, $1}' >> "$REPORT_FILE"
+
+echo "│ │" >> "$REPORT_FILE"
+echo "│ O3 Pass Frequencies: │" >> "$REPORT_FILE"
+sed 's/Running pass: //' o3_passes_raw.txt | sort | uniq -c | sort -nr | head -10 | \
+ awk '{printf "│ %-50s %s times\n", $2, $1}' >> "$REPORT_FILE"
+
+echo "└────────────────────────────────────────────────────────────────────────────┘" >> "$REPORT_FILE"
+echo "" >> "$REPORT_FILE"
+
+# Categorize passes by type
+echo "┌─ PASS CATEGORIZATION (O3-only passes) ────────────────────────────────────┐" >> "$REPORT_FILE"
+echo "│ Categorizing O3-specific passes by optimization type │" >> "$REPORT_FILE"
+echo "│ │" >> "$REPORT_FILE"
+
+# Function to categorize passes
+categorize_passes() {
+ local file=$1
+ local prefix=$2
+
+ # Loop optimizations
+ local loop_passes=$(grep -i "loop\|unroll\|vectoriz\|licm" "$file" || true)
+ if [ -n "$loop_passes" ]; then
+ echo "${prefix} Loop Optimizations:" >> "$REPORT_FILE"
+ echo "$loop_passes" | sed "s/^/${prefix} /" >> "$REPORT_FILE"
+ echo "${prefix}" >> "$REPORT_FILE"
+ fi
+
+ # Function optimizations
+ local function_passes=$(grep -i "inline\|function\|call" "$file" || true)
+ if [ -n "$function_passes" ]; then
+ echo "${prefix} Function/Inlining Optimizations:" >> "$REPORT_FILE"
+ echo "$function_passes" | sed "s/^/${prefix} /" >> "$REPORT_FILE"
+ echo "${prefix}" >> "$REPORT_FILE"
+ fi
+
+ # Memory optimizations
+ local memory_passes=$(grep -i "mem\|alias\|gvn\|load\|store" "$file" || true)
+ if [ -n "$memory_passes" ]; then
+ echo "${prefix} Memory Optimizations:" >> "$REPORT_FILE"
+ echo "$memory_passes" | sed "s/^/${prefix} /" >> "$REPORT_FILE"
+ echo "${prefix}" >> "$REPORT_FILE"
+ fi
+
+ # Dead code elimination
+ local dce_passes=$(grep -i "dce\|dead\|unused\|eliminate" "$file" || true)
+ if [ -n "$dce_passes" ]; then
+ echo "${prefix} Dead Code Elimination:" >> "$REPORT_FILE"
+ echo "$dce_passes" | sed "s/^/${prefix} /" >> "$REPORT_FILE"
+ echo "${prefix}" >> "$REPORT_FILE"
+ fi
+}
+
+# Create temporary file with O3-only passes
+comm -13 o2_passes_clean.txt o3_passes_clean.txt > o3_only_passes.txt
+categorize_passes "o3_only_passes.txt" "│"
+
+echo "└────────────────────────────────────────────────────────────────────────────┘" >> "$REPORT_FILE"
+echo "" >> "$REPORT_FILE"
+
+# Complete pass execution order comparison
+echo "┌─ COMPLETE PASS EXECUTION ORDER ───────────────────────────────────────────┐" >> "$REPORT_FILE"
+echo "│ Side-by-side comparison of pass execution order │" >> "$REPORT_FILE"
+echo "│ │" >> "$REPORT_FILE"
+
+echo "│ O2 Passes (in execution order): │" >> "$REPORT_FILE"
+echo "│ ════════════════════════════════ │" >> "$REPORT_FILE"
+sed 's/Running pass: //' o2_passes_raw.txt | nl -nln | sed 's/^/│ /' >> "$REPORT_FILE"
+
+echo "│ │" >> "$REPORT_FILE"
+echo "│ O3 Passes (in execution order): │" >> "$REPORT_FILE"
+echo "│ ════════════════════════════════ │" >> "$REPORT_FILE"
+sed 's/Running pass: //' o3_passes_raw.txt | nl -nln | sed 's/^/│ /' >> "$REPORT_FILE"
+
+echo "└────────────────────────────────────────────────────────────────────────────┘" >> "$REPORT_FILE"
+
+# Performance implications
+cat >> "$REPORT_FILE" << 'EOF'
+
+═══════════════════════════════════════════════════════════════════════════════
+ PERFORMANCE IMPLICATIONS
+═══════════════════════════════════════════════════════════════════════════════
+
+Based on the pass analysis:
+
+COMPILATION TIME:
+• O3 requires more compilation time due to additional optimization passes
+• The extra passes in O3 perform more complex analysis and transformations
+
+RUNTIME PERFORMANCE:
+• O3's additional passes typically result in better runtime performance
+• Common O3 improvements include:
+ - More aggressive function inlining
+ - Better loop optimizations (unrolling, vectorization)
+ - More sophisticated dead code elimination
+ - Enhanced constant propagation and folding
+
+TRADE-OFFS:
+• O2: Balanced optimization (good performance, reasonable compile time)
+• O3: Maximum optimization (best performance, longer compile time)
+
+EOF
+
+# Add recommendations
+cat >> "$REPORT_FILE" << 'EOF'
+
+═══════════════════════════════════════════════════════════════════════════════
+ RECOMMENDATIONS
+═══════════════════════════════════════════════════════════════════════════════
+
+FOR DEVELOPMENT:
+• Use O2 for faster compilation during development cycles
+• Switch to O3 for production builds where runtime performance is critical
+
+FOR PRODUCTION:
+• Use O3 when maximum runtime performance is required
+• Consider O2 if compilation time is a constraint in CI/CD pipelines
+
+FOR DEBUGGING:
+• Use this report to understand which optimizations are applied
+• Compare with -O0 and -O1 to see the full optimization progression
+
+EOF
+
+# Footer
+cat >> "$REPORT_FILE" << 'EOF'
+
+═══════════════════════════════════════════════════════════════════════════════
+ END OF REPORT
+═══════════════════════════════════════════════════════════════════════════════
+
+Generated by LLVM Pass Analysis Tool
+EOF
+
+# Cleanup temporary files
+rm -f o2_passes_raw.txt o3_passes_raw.txt o2_passes_clean.txt o3_passes_clean.txt o3_only_passes.txt
+
+# Report completion
+echo ""
+echo "╔════════════════════════════════════════════════════════════════╗"
+echo "║ REPORT GENERATED SUCCESSFULLY ║"
+echo "╚════════════════════════════════════════════════════════════════╝"
+echo ""
+echo "Report saved to: $REPORT_FILE"
+echo ""
+echo "Summary:"
+echo " • O2 passes: $O2_COUNT"
+echo " • O3 passes: $O3_COUNT"
+echo " • Additional in O3: $(($O3_COUNT - $O2_COUNT))"
+echo " • O3-only passes: $O3_ONLY_COUNT"
+echo ""
+echo "To view the report:"
+echo " cat $REPORT_FILE"
+echo " # or"
+echo " less $REPORT_FILE"
\ No newline at end of file
diff --git a/optimization_0_new.txt b/optimization_0_new.txt
new file mode 100644
index 0000000000000..d9da35543690b
--- /dev/null
+++ b/optimization_0_new.txt
@@ -0,0 +1,676 @@
+ -- 'Expand large div/rem' is not preserving 'Pre-ISel Intrinsic Lowering'
+ -- 'Expand large div/rem' is not preserving 'Function Pass Manager'
+ -- 'Expand fp' is not preserving 'Expand large div/rem'
+ -- 'Expand Atomic instructions' is not preserving 'Expand fp'
+ -- 'Lower Garbage Collection Instructions' is not preserving 'Expand Atomic instructions'
+ -- 'Shadow Stack GC Lowering' is not preserving 'Lower Garbage Collection Instructions'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Lower @llvm.global_dtors via `__cxa_atexit`'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Function Pass Manager'
+ -- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is not preserving 'Remove unreachable blocks from the CFG'
+ -- 'Scalarize Masked Memory Intrinsics' is not preserving 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)'
+ -- 'Expand reduction intrinsics' is not preserving 'Scalarize Masked Memory Intrinsics'
+ -- 'AArch64 Stack Tagging' is not preserving 'Expand reduction intrinsics'
+ -- 'AArch64 Stack Tagging' is not preserving 'Optimization Remark Emitter'
+ -- 'SME ABI Pass' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'SME ABI Pass' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'SME ABI Pass' is not preserving 'Natural Loop Information'
+ -- 'SME ABI Pass' is not preserving 'AArch64 Stack Tagging'
+ -- 'SME ABI Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Exception handling preparation' is not preserving 'SME ABI Pass'
+ -- 'Prepare callbr' is not preserving 'Exception handling preparation'
+ -- 'Safe Stack instrumentation pass' is not preserving 'Prepare callbr'
+ -- 'Insert stack protectors' is not preserving 'Safe Stack instrumentation pass'
+ -- 'IRTranslator' is not preserving 'Analysis containing CSE Info'
+ -- 'AArch64O0PreLegalizerCombiner' is not preserving 'IRTranslator'
+ -- 'Localizer' is not preserving 'AArch64O0PreLegalizerCombiner'
+ -- 'Localizer' is not preserving 'Analysis for ComputingKnownBits'
+ -- 'Legalizer' is not preserving 'Localizer'
+ -- 'AArch64PostLegalizerLowering' is not preserving 'Legalizer'
+ -- 'AArch64PostLegalizerLowering' is not preserving 'Analysis containing CSE Info'
+ -- 'AArch64PostLegalizerLowering' is not preserving 'Analysis for ComputingKnownBits'
+ -- 'RegBankSelect' is not preserving 'AArch64PostLegalizerLowering'
+ -- 'InstructionSelect' is not preserving 'RegBankSelect'
+ -- 'ResetMachineFunction' is not preserving 'InstructionSelect'
+ -- 'ResetMachineFunction' is not preserving 'Analysis for ComputingKnownBits'
+ -- 'AArch64 Instruction Selection' is not preserving 'ResetMachineFunction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'Assignment Tracking Analysis'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'AArch64 Instruction Selection'
+ -- 'Local Stack Slot Allocation' is not preserving 'Finalize ISel and expand pseudo-instructions'
+ -- 'Eliminate PHI nodes for register allocation' is not preserving 'Local Stack Slot Allocation'
+ -- 'Two-Address instruction pass' is not preserving 'Eliminate PHI nodes for register allocation'
+ -- 'Fast Register Allocator' is not preserving 'Two-Address instruction pass'
+ -- 'Remove Redundant DEBUG_VALUE analysis' is not preserving 'Fast Register Allocator'
+ -- 'Fixup Statepoint Caller Saved' is not preserving 'Remove Redundant DEBUG_VALUE analysis'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'Fixup Statepoint Caller Saved'
+ -- 'Post-RA pseudo instruction expansion pass' is not preserving 'Prologue/Epilogue Insertion & Frame Finalization'
+ -- 'AArch64 pseudo instruction expansion pass' is not preserving 'Post-RA pseudo instruction expansion pass'
+ -- 'AArch64 pseudo instruction expansion pass' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'AArch64 pseudo instruction expansion pass' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Insert KCFI indirect call checks' is not preserving 'AArch64 pseudo instruction expansion pass'
+ -- 'AArch64 speculation hardening pass' is not preserving 'Insert KCFI indirect call checks'
+ -- 'Insert fentry calls' is not preserving 'Analyze Machine Code For Garbage Collection'
+ -- 'Insert fentry calls' is not preserving 'AArch64 speculation hardening pass'
+ -- 'Insert XRay ops' is not preserving 'Insert fentry calls'
+ -- 'Implement the 'patchable-function' attribute' is not preserving 'Insert XRay ops'
+ -- 'Workaround A53 erratum 835769 pass' is not preserving 'Implement the 'patchable-function' attribute'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'Workaround A53 erratum 835769 pass'
+ -- 'Remove Loads Into Fake Uses' is not preserving 'Contiguously Lay Out Funclets'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'StackMap Liveness Analysis'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'Remove Loads Into Fake Uses'
+ -- 'Machine Sanitizer Binary Metadata' is not preserving 'Live DEBUG_VALUE analysis'
+ -- 'AArch64 sls hardening pass' is not preserving 'Machine Sanitizer Binary Metadata'
+ -- 'AArch64 Pointer Authentication' is not preserving 'AArch64 sls hardening pass'
+ -- 'AArch64 Branch Targets' is not preserving 'AArch64 Pointer Authentication'
+ -- 'Branch relaxation pass' is not preserving 'AArch64 Branch Targets'
+ -- 'Unpack machine instruction bundles' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Unpack machine instruction bundles' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Stack Frame Layout Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Insert CFI remember/restore state instructions'
+ -- 'Unpack machine instruction bundles' is not preserving 'Branch relaxation pass'
+ -- 'Free MachineFunction' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Free MachineFunction' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Free MachineFunction' is not preserving 'AArch64 Assembly Printer'
+ -- 'Free MachineFunction' is not preserving 'Unpack machine instruction bundles'
+Pass Arguments: -tti -targetlibinfo -targetpassconfig -machinemoduleinfo -collector-metadata -profile-summary-info -assumption-cache-tracker -machine-branch-prob -pre-isel-intrinsic-lowering -expand-large-div-rem -expand-fp -atomic-expand -gc-lowering -shadow-stack-gc-lowering -lower-global-dtors -unreachableblockelim -post-inline-ee-instrument -scalarize-masked-mem-intrin -expand-reductions -domtree -loops -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -aarch64-stack-tagging -aarch64-sme-abi -dwarf-eh-prepare -callbrprepare -safe-stack -stack-protector -cseinfo -irtranslator -gisel-known-bits -aarch64-O0-prelegalizer-combiner -localizer -cseinfo -gisel-known-bits -legalizer -aarch64-postlegalizer-lowering -regbankselect -gisel-known-bits -instruction-select -debug-ata -aarch64-isel -finalize-isel -localstackalloc -phi-node-elimination -twoaddressinstruction -regallocfast -removeredundantdebugvalues -fixup-statepoint-caller-saved -lazy-machine-block-freq -machine-opt-remark-emitter -prologepilog -postrapseudos -aarch64-expand-pseudo -kcfi -aarch64-speculation-hardening -gc-analysis -fentry-insert -xray-instrumentation -patchable-function -aarch64-fix-cortex-a53-835769-pass -funclet-layout -remove-loads-into-fake-uses -stackmap-liveness -livedebugvalues -machine-sanmd -aarch64-sls-hardening -aarch64-ptrauth -aarch64-branch-targets -branch-relaxation -cfi-fixup -lazy-machine-block-freq -machine-opt-remark-emitter -stack-frame-layout -unpack-mi-bundles -lazy-machine-block-freq -machine-opt-remark-emitter -aarch64-asm-printer
+Target Transform Information
+Target Library Information
+Target Pass Configuration
+Machine Module Information
+Create Garbage Collector Module Metadata
+Profile summary info
+Assumption Cache Tracker
+Machine Branch Probability Analysis
+ ModulePass Manager
+ Pre-ISel Intrinsic Lowering
+-- Pre-ISel Intrinsic Lowering
+ FunctionPass Manager
+ Expand large div/rem
+-- Expand large div/rem
+ Expand fp
+-- Expand fp
+ Expand Atomic instructions
+-- Expand Atomic instructions
+ Lower Garbage Collection Instructions
+-- Lower Garbage Collection Instructions
+ Shadow Stack GC Lowering
+-- Shadow Stack GC Lowering
+ Lower @llvm.global_dtors via `__cxa_atexit`
+-- Lower @llvm.global_dtors via `__cxa_atexit`
+ FunctionPass Manager
+ Remove unreachable blocks from the CFG
+-- Remove unreachable blocks from the CFG
+ Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+-- Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+ Scalarize Masked Memory Intrinsics
+-- Scalarize Masked Memory Intrinsics
+ Expand reduction intrinsics
+-- Expand reduction intrinsics
+ Dominator Tree Construction
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ AArch64 Stack Tagging
+-- Optimization Remark Emitter
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Dominator Tree Construction
+-- AArch64 Stack Tagging
+ SME ABI Pass
+-- SME ABI Pass
+ Exception handling preparation
+-- Exception handling preparation
+ Prepare callbr
+-- Prepare callbr
+ Safe Stack instrumentation pass
+-- Safe Stack instrumentation pass
+ Insert stack protectors
+ Analysis containing CSE Info
+ IRTranslator
+-- IRTranslator
+-- Analysis containing CSE Info
+ Analysis for ComputingKnownBits
+ AArch64O0PreLegalizerCombiner
+-- Analysis for ComputingKnownBits
+-- AArch64O0PreLegalizerCombiner
+ Localizer
+-- Localizer
+ Analysis containing CSE Info
+ Analysis for ComputingKnownBits
+ Legalizer
+-- Analysis containing CSE Info
+-- Analysis for ComputingKnownBits
+-- Legalizer
+ AArch64PostLegalizerLowering
+-- AArch64PostLegalizerLowering
+ RegBankSelect
+-- RegBankSelect
+ Analysis for ComputingKnownBits
+ InstructionSelect
+-- Analysis for ComputingKnownBits
+-- InstructionSelect
+ ResetMachineFunction
+-- ResetMachineFunction
+ Assignment Tracking Analysis
+ AArch64 Instruction Selection
+-- Insert stack protectors
+-- Assignment Tracking Analysis
+-- AArch64 Instruction Selection
+ Finalize ISel and expand pseudo-instructions
+-- Finalize ISel and expand pseudo-instructions
+ Local Stack Slot Allocation
+-- Local Stack Slot Allocation
+ Eliminate PHI nodes for register allocation
+-- Eliminate PHI nodes for register allocation
+ Two-Address instruction pass
+-- Two-Address instruction pass
+ Fast Register Allocator
+-- Fast Register Allocator
+ Remove Redundant DEBUG_VALUE analysis
+-- Remove Redundant DEBUG_VALUE analysis
+ Fixup Statepoint Caller Saved
+-- Fixup Statepoint Caller Saved
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Prologue/Epilogue Insertion & Frame Finalization
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Prologue/Epilogue Insertion & Frame Finalization
+ Post-RA pseudo instruction expansion pass
+-- Post-RA pseudo instruction expansion pass
+ AArch64 pseudo instruction expansion pass
+-- AArch64 pseudo instruction expansion pass
+ Insert KCFI indirect call checks
+-- Insert KCFI indirect call checks
+ AArch64 speculation hardening pass
+-- AArch64 speculation hardening pass
+ Analyze Machine Code For Garbage Collection
+-- Analyze Machine Code For Garbage Collection
+ Insert fentry calls
+-- Insert fentry calls
+ Insert XRay ops
+-- Insert XRay ops
+ Implement the 'patchable-function' attribute
+-- Implement the 'patchable-function' attribute
+ Workaround A53 erratum 835769 pass
+-- Workaround A53 erratum 835769 pass
+ Contiguously Lay Out Funclets
+-- Contiguously Lay Out Funclets
+ Remove Loads Into Fake Uses
+-- Remove Loads Into Fake Uses
+ StackMap Liveness Analysis
+-- StackMap Liveness Analysis
+ Live DEBUG_VALUE analysis
+-- Live DEBUG_VALUE analysis
+ Machine Sanitizer Binary Metadata
+-- Machine Sanitizer Binary Metadata
+ AArch64 sls hardening pass
+-- AArch64 sls hardening pass
+ AArch64 Pointer Authentication
+-- AArch64 Pointer Authentication
+ AArch64 Branch Targets
+-- AArch64 Branch Targets
+ Branch relaxation pass
+-- Branch relaxation pass
+ Insert CFI remember/restore state instructions
+-- Insert CFI remember/restore state instructions
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Stack Frame Layout Analysis
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Stack Frame Layout Analysis
+ Unpack machine instruction bundles
+-- Unpack machine instruction bundles
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ AArch64 Assembly Printer
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- AArch64 Assembly Printer
+ Free MachineFunction
+-- Free MachineFunction
+-- Target Transform Information
+-- Assumption Cache Tracker
+-- Target Pass Configuration
+-- Target Library Information
+-- Machine Branch Probability Analysis
+-- Profile summary info
+-- Create Garbage Collector Module Metadata
+-- Machine Module Information
+Running pass: Pre-ISel Intrinsic Lowering
+[2025-06-18 00:55:38.083744000] 0x1496492b0 Executing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+0x149659060 Required Analyses: Target Transform Information, Target Library Information, Target Pass Configuration
+ -*- 'Pre-ISel Intrinsic Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.084290000] 0x1496492b0 Freeing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:55:38.084343000] 0x1496492b0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Expand large div/rem
+[2025-06-18 00:55:38.084395000] 0x1496590e0 Executing Pass 'Expand large div/rem' on Function 'main'...
+0x1496590a0 Required Analyses: Target Pass Configuration
+0x1496590a0 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand large div/rem' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.084520000] 0x1496590e0 Freeing Pass 'Expand large div/rem' on Function 'main'...
+Running pass: Expand fp
+[2025-06-18 00:55:38.084571000] 0x1496590e0 Executing Pass 'Expand fp' on Function 'main'...
+0x149659030 Required Analyses: Target Pass Configuration
+0x149659030 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand fp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.084684000] 0x1496590e0 Freeing Pass 'Expand fp' on Function 'main'...
+Running pass: Expand Atomic instructions
+[2025-06-18 00:55:38.084735000] 0x1496590e0 Executing Pass 'Expand Atomic instructions' on Function 'main'...
+ -*- 'Expand Atomic instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.084792000] 0x1496590e0 Freeing Pass 'Expand Atomic instructions' on Function 'main'...
+Running pass: Lower Garbage Collection Instructions
+[2025-06-18 00:55:38.084845000] 0x1496590e0 Executing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+0x1496592e0 Required Analyses: Create Garbage Collector Module Metadata
+0x1496592e0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Lower Garbage Collection Instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.084946000] 0x1496590e0 Freeing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+Running pass: Shadow Stack GC Lowering
+[2025-06-18 00:55:38.085017000] 0x1496590e0 Executing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+0x1496593c0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Shadow Stack GC Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.085095000] 0x1496590e0 Freeing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+Running pass: Lower @llvm.global_dtors via `__cxa_atexit`
+[2025-06-18 00:55:38.085147000] 0x1496492b0 Executing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+0x149659430 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information
+ -*- 'Lower @llvm.global_dtors via `__cxa_atexit`' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.085520000] 0x1496492b0 Freeing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:55:38.085571000] 0x1496492b0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Remove unreachable blocks from the CFG
+[2025-06-18 00:55:38.085622000] 0x1496594b0 Executing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+0x149659470 Preserved Analyses: Dominator Tree Construction
+ -*- 'Remove unreachable blocks from the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.085702000] 0x1496594b0 Freeing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+Running pass: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+[2025-06-18 00:55:38.085753000] 0x1496594b0 Executing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+0x149659670 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.085843000] 0x1496594b0 Freeing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+Running pass: Scalarize Masked Memory Intrinsics
+[2025-06-18 00:55:38.085894000] 0x1496594b0 Executing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+0x149659720 Required Analyses: Target Transform Information
+0x149659720 Preserved Analyses: Dominator Tree Construction
+ -*- 'Scalarize Masked Memory Intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.086515000] 0x1496594b0 Freeing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+Running pass: Expand reduction intrinsics
+[2025-06-18 00:55:38.086569000] 0x1496594b0 Executing Pass 'Expand reduction intrinsics' on Function 'main'...
+0x1496598d0 Required Analyses: Target Transform Information
+0x1496598d0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information
+ -*- 'Expand reduction intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.086975000] 0x1496594b0 Freeing Pass 'Expand reduction intrinsics' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:55:38.087026000] 0x1496594b0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:55:38.087080000] 0x1496594b0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x149659de0 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:55:38.087159000] 0x1496594b0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x149659c70 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:55:38.087256000] 0x1496594b0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x149659e90 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:55:38.087369000] 0x1496594b0 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x149659c40 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: AArch64 Stack Tagging
+[2025-06-18 00:55:38.087487000] 0x1496594b0 Executing Pass 'AArch64 Stack Tagging' on Function 'main'...
+0x149659980 Required Analyses: Optimization Remark Emitter
+0x149659980 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information
+ -*- 'AArch64 Stack Tagging' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.087870000] 0x1496594b0 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:55:38.087912000] 0x1496594b0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:55:38.087952000] 0x1496594b0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:55:38.087996000] 0x1496594b0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:55:38.088417000] 0x1496594b0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:55:38.088481000] 0x1496594b0 Freeing Pass 'AArch64 Stack Tagging' on Function 'main'...
+Running pass: SME ABI Pass
+[2025-06-18 00:55:38.088539000] 0x1496594b0 Executing Pass 'SME ABI Pass' on Function 'main'...
+ -*- 'SME ABI Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.088598000] 0x1496594b0 Freeing Pass 'SME ABI Pass' on Function 'main'...
+Running pass: Exception handling preparation
+[2025-06-18 00:55:38.088649000] 0x1496594b0 Executing Pass 'Exception handling preparation' on Function 'main'...
+0x149659fa0 Required Analyses: Target Pass Configuration, Target Transform Information
+0x149659fa0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Exception handling preparation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.088771000] 0x1496594b0 Freeing Pass 'Exception handling preparation' on Function 'main'...
+Running pass: Prepare callbr
+[2025-06-18 00:55:38.088822000] 0x1496594b0 Executing Pass 'Prepare callbr' on Function 'main'...
+0x149659ff0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Prepare callbr' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.088900000] 0x1496594b0 Freeing Pass 'Prepare callbr' on Function 'main'...
+Running pass: Safe Stack instrumentation pass
+[2025-06-18 00:55:38.088950000] 0x1496594b0 Executing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+0x14965a030 Required Analyses: Target Pass Configuration, Target Library Information, Assumption Cache Tracker
+0x14965a030 Preserved Analyses: Dominator Tree Construction
+ -*- 'Safe Stack instrumentation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.089071000] 0x1496594b0 Freeing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+Running pass: Insert stack protectors
+[2025-06-18 00:55:38.089122000] 0x1496594b0 Executing Pass 'Insert stack protectors' on Function 'main'...
+0x14965a0e0 Required Analyses: Target Pass Configuration
+0x14965a0e0 Preserved Analyses: Dominator Tree Construction
+Running pass: Analysis containing CSE Info
+[2025-06-18 00:55:38.089222000] 0x1496594b0 Executing Pass 'Analysis containing CSE Info' on Function 'main'...
+0x14965a670 Required Analyses: Machine Module Information
+0x14965a670 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: IRTranslator
+[2025-06-18 00:55:38.089442000] 0x1496594b0 Executing Pass 'IRTranslator' on Function 'main'...
+0x14991ce00 Required Analyses: Insert stack protectors, Target Pass Configuration, Analysis containing CSE Info, Assumption Cache Tracker, Target Library Information, Machine Module Information
+0x14991ce00 Preserved Analyses: Target Library Information, Insert stack protectors, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'IRTranslator' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.097224000] 0x1496594b0 Freeing Pass 'IRTranslator' on Function 'main'...
+[2025-06-18 00:55:38.097268000] 0x1496594b0 Freeing Pass 'Analysis containing CSE Info' on Function 'main'...
+Running pass: Analysis for ComputingKnownBits
+[2025-06-18 00:55:38.097320000] 0x1496594b0 Executing Pass 'Analysis for ComputingKnownBits' on Function 'main'...
+0x14965ace0 Required Analyses: Machine Module Information
+0x14965ace0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64O0PreLegalizerCombiner
+[2025-06-18 00:55:38.097534000] 0x1496594b0 Executing Pass 'AArch64O0PreLegalizerCombiner' on Function 'main'...
+0x14965aa30 Required Analyses: Target Pass Configuration, Analysis for ComputingKnownBits, Machine Module Information
+[2025-06-18 00:55:38.099214000] 0x1496594b0 Made Modification 'AArch64O0PreLegalizerCombiner' on Function 'main'...
+0x14965aa30 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Insert stack protectors, Analysis for ComputingKnownBits, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'AArch64O0PreLegalizerCombiner' is not preserving 'Function Pass Manager'
+ -*- 'AArch64O0PreLegalizerCombiner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.099679000] 0x1496594b0 Freeing Pass 'Analysis for ComputingKnownBits' on Function 'main'...
+[2025-06-18 00:55:38.100005000] 0x1496594b0 Freeing Pass 'AArch64O0PreLegalizerCombiner' on Function 'main'...
+Running pass: Localizer
+[2025-06-18 00:55:38.100057000] 0x1496594b0 Executing Pass 'Localizer' on Function 'main'...
+0x14965ad20 Required Analyses: Target Transform Information, Machine Module Information
+[2025-06-18 00:55:38.100298000] 0x1496594b0 Made Modification 'Localizer' on Function 'main'...
+0x14965ad20 Preserved Analyses: Insert stack protectors, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Localizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.100480000] 0x1496594b0 Freeing Pass 'Localizer' on Function 'main'...
+Running pass: Analysis containing CSE Info
+[2025-06-18 00:55:38.100531000] 0x1496594b0 Executing Pass 'Analysis containing CSE Info' on Function 'main'...
+0x14965b220 Required Analyses: Machine Module Information
+0x14965b220 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Analysis for ComputingKnownBits
+[2025-06-18 00:55:38.100720000] 0x1496594b0 Executing Pass 'Analysis for ComputingKnownBits' on Function 'main'...
+0x14965adb0 Required Analyses: Machine Module Information
+0x14965adb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Legalizer
+[2025-06-18 00:55:38.100935000] 0x1496594b0 Executing Pass 'Legalizer' on Function 'main'...
+0x14965afc0 Required Analyses: Target Pass Configuration, Analysis containing CSE Info, Analysis for ComputingKnownBits, Machine Module Information
+[2025-06-18 00:55:38.103362000] 0x1496594b0 Made Modification 'Legalizer' on Function 'main'...
+0x14965afc0 Preserved Analyses: Analysis containing CSE Info, Analysis for ComputingKnownBits, Insert stack protectors, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Legalizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.103598000] 0x1496594b0 Freeing Pass 'Analysis containing CSE Info' on Function 'main'...
+[2025-06-18 00:55:38.103650000] 0x1496594b0 Freeing Pass 'Analysis for ComputingKnownBits' on Function 'main'...
+[2025-06-18 00:55:38.103692000] 0x1496594b0 Freeing Pass 'Legalizer' on Function 'main'...
+Running pass: AArch64PostLegalizerLowering
+[2025-06-18 00:55:38.103752000] 0x1496594b0 Executing Pass 'AArch64PostLegalizerLowering' on Function 'main'...
+0x14965adf0 Required Analyses: Target Pass Configuration, Machine Module Information
+0x14965adf0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Insert stack protectors, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64PostLegalizerLowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.104866000] 0x1496594b0 Freeing Pass 'AArch64PostLegalizerLowering' on Function 'main'...
+Running pass: RegBankSelect
+[2025-06-18 00:55:38.104918000] 0x1496594b0 Executing Pass 'RegBankSelect' on Function 'main'...
+0x14965b610 Required Analyses: Target Pass Configuration, Machine Module Information
+0x14965b610 Preserved Analyses: Insert stack protectors, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'RegBankSelect' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.106041000] 0x1496594b0 Freeing Pass 'RegBankSelect' on Function 'main'...
+Running pass: Analysis for ComputingKnownBits
+[2025-06-18 00:55:38.106114000] 0x1496594b0 Executing Pass 'Analysis for ComputingKnownBits' on Function 'main'...
+0x14965b9b0 Required Analyses: Machine Module Information
+0x14965b9b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: InstructionSelect
+[2025-06-18 00:55:38.106310000] 0x1496594b0 Executing Pass 'InstructionSelect' on Function 'main'...
+0x14965b920 Required Analyses: Target Pass Configuration, Analysis for ComputingKnownBits, Machine Module Information
+[2025-06-18 00:55:38.110598000] 0x1496594b0 Made Modification 'InstructionSelect' on Function 'main'...
+0x14965b920 Preserved Analyses: Analysis for ComputingKnownBits, Insert stack protectors, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'InstructionSelect' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.110798000] 0x1496594b0 Freeing Pass 'Analysis for ComputingKnownBits' on Function 'main'...
+[2025-06-18 00:55:38.110841000] 0x1496594b0 Freeing Pass 'InstructionSelect' on Function 'main'...
+Running pass: ResetMachineFunction
+[2025-06-18 00:55:38.110892000] 0x1496594b0 Executing Pass 'ResetMachineFunction' on Function 'main'...
+0x14965b830 Required Analyses: Machine Module Information
+0x14965b830 Preserved Analyses: Insert stack protectors, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'ResetMachineFunction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.111102000] 0x1496594b0 Freeing Pass 'ResetMachineFunction' on Function 'main'...
+Running pass: Assignment Tracking Analysis
+[2025-06-18 00:55:38.111154000] 0x1496594b0 Executing Pass 'Assignment Tracking Analysis' on Function 'main'...
+Running pass: AArch64 Instruction Selection
+[2025-06-18 00:55:38.111555000] 0x1496594b0 Executing Pass 'AArch64 Instruction Selection' on Function 'main'...
+0x14965b870 Required Analyses: Create Garbage Collector Module Metadata, Insert stack protectors, Target Library Information, Assumption Cache Tracker, Profile summary info, Assignment Tracking Analysis, Machine Module Information
+0x14965b870 Preserved Analyses: Create Garbage Collector Module Metadata, Assignment Tracking Analysis, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Instruction Selection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.111853000] 0x1496594b0 Freeing Pass 'Insert stack protectors' on Function 'main'...
+[2025-06-18 00:55:38.111896000] 0x1496594b0 Freeing Pass 'Assignment Tracking Analysis' on Function 'main'...
+[2025-06-18 00:55:38.111939000] 0x1496594b0 Freeing Pass 'AArch64 Instruction Selection' on Function 'main'...
+Running pass: Finalize ISel and expand pseudo-instructions
+[2025-06-18 00:55:38.111993000] 0x1496594b0 Executing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+0x14965d0c0 Required Analyses: Machine Module Information
+0x14965d0c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Finalize ISel and expand pseudo-instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.112224000] 0x1496594b0 Freeing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+Running pass: Local Stack Slot Allocation
+[2025-06-18 00:55:38.112281000] 0x1496594b0 Executing Pass 'Local Stack Slot Allocation' on Function 'main'...
+0x14965d100 Required Analyses: Machine Module Information
+[2025-06-18 00:55:38.113098000] 0x1496594b0 Made Modification 'Local Stack Slot Allocation' on Function 'main'...
+0x14965d100 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Local Stack Slot Allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.113543000] 0x1496594b0 Freeing Pass 'Local Stack Slot Allocation' on Function 'main'...
+Running pass: Eliminate PHI nodes for register allocation
+[2025-06-18 00:55:38.113595000] 0x1496594b0 Executing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+0x14965d010 Required Analyses: Machine Module Information
+0x14965d010 Preserved Analyses: Live Variable Analysis, Slot index numbering, Live Interval Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x14965d010 Used Analyses: Live Variable Analysis
+ -*- 'Eliminate PHI nodes for register allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.113876000] 0x1496594b0 Freeing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+Running pass: Two-Address instruction pass
+[2025-06-18 00:55:38.113928000] 0x1496594b0 Executing Pass 'Two-Address instruction pass' on Function 'main'...
+0x14965d200 Required Analyses: Machine Module Information
+0x14965d200 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Live Variable Analysis, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x14965d200 Used Analyses: Function Alias Analysis Results, Live Variable Analysis
+ -*- 'Two-Address instruction pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.114514000] 0x1496594b0 Freeing Pass 'Two-Address instruction pass' on Function 'main'...
+Running pass: Fast Register Allocator
+[2025-06-18 00:55:38.114567000] 0x1496594b0 Executing Pass 'Fast Register Allocator' on Function 'main'...
+0x14991be00 Required Analyses: Machine Module Information
+[2025-06-18 00:55:38.115747000] 0x1496594b0 Made Modification 'Fast Register Allocator' on Function 'main'...
+0x14991be00 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Fast Register Allocator' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.116188000] 0x1496594b0 Freeing Pass 'Fast Register Allocator' on Function 'main'...
+Running pass: Remove Redundant DEBUG_VALUE analysis
+[2025-06-18 00:55:38.116239000] 0x1496594b0 Executing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+0x14965aba0 Required Analyses: Machine Module Information
+0x14965aba0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Redundant DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.116719000] 0x1496594b0 Freeing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Fixup Statepoint Caller Saved
+[2025-06-18 00:55:38.116771000] 0x1496594b0 Executing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+0x14965abe0 Required Analyses: Machine Module Information
+0x14965abe0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Fixup Statepoint Caller Saved' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.117241000] 0x1496594b0 Freeing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:55:38.117292000] 0x1496594b0 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x14965ded0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x14965ded0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:55:38.117499000] 0x1496594b0 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x14965d280 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x14965d280 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Prologue/Epilogue Insertion & Frame Finalization
+[2025-06-18 00:55:38.117703000] 0x1496594b0 Executing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x14965d240 Required Analyses: Machine Optimization Remark Emitter, Machine Module Information
+[2025-06-18 00:55:38.118257000] 0x1496594b0 Made Modification 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x14965d240 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Prologue/Epilogue Insertion & Frame Finalization' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.119138000] 0x1496594b0 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:55:38.119180000] 0x1496594b0 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:55:38.119382000] 0x1496594b0 Freeing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+Running pass: Post-RA pseudo instruction expansion pass
+[2025-06-18 00:55:38.119435000] 0x1496594b0 Executing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+0x14965d2c0 Required Analyses: Machine Module Information
+0x14965d2c0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Post-RA pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.119896000] 0x1496594b0 Freeing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 pseudo instruction expansion pass
+[2025-06-18 00:55:38.119947000] 0x1496594b0 Executing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x14965d520 Required Analyses: Machine Module Information
+[2025-06-18 00:55:38.120514000] 0x1496594b0 Made Modification 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x14965d520 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.120688000] 0x1496594b0 Freeing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+Running pass: Insert KCFI indirect call checks
+[2025-06-18 00:55:38.120755000] 0x1496594b0 Executing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+0x14965d560 Required Analyses: Machine Module Information
+0x14965d560 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert KCFI indirect call checks' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.120950000] 0x1496594b0 Freeing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+Running pass: AArch64 speculation hardening pass
+[2025-06-18 00:55:38.121001000] 0x1496594b0 Executing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+0x14965d5e0 Required Analyses: Machine Module Information
+0x14965d5e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 speculation hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.121197000] 0x1496594b0 Freeing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+Running pass: Analyze Machine Code For Garbage Collection
+[2025-06-18 00:55:38.121249000] 0x1496594b0 Executing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+0x14965d830 Required Analyses: Machine Module Information, Create Garbage Collector Module Metadata
+0x14965d830 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Analyze Machine Code For Garbage Collection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.121587000] 0x1496594b0 Freeing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+Running pass: Insert fentry calls
+[2025-06-18 00:55:38.121638000] 0x1496594b0 Executing Pass 'Insert fentry calls' on Function 'main'...
+0x14965d880 Required Analyses: Machine Module Information
+0x14965d880 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert fentry calls' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.121833000] 0x1496594b0 Freeing Pass 'Insert fentry calls' on Function 'main'...
+Running pass: Insert XRay ops
+[2025-06-18 00:55:38.121884000] 0x1496594b0 Executing Pass 'Insert XRay ops' on Function 'main'...
+0x14965d8f0 Required Analyses: Machine Module Information
+0x14965d8f0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert XRay ops' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.122362000] 0x1496594b0 Freeing Pass 'Insert XRay ops' on Function 'main'...
+Running pass: Implement the 'patchable-function' attribute
+[2025-06-18 00:55:38.122415000] 0x1496594b0 Executing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+0x14965e010 Required Analyses: Machine Module Information
+0x14965e010 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Implement the 'patchable-function' attribute' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.122614000] 0x1496594b0 Freeing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+Running pass: Workaround A53 erratum 835769 pass
+[2025-06-18 00:55:38.122666000] 0x1496594b0 Executing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+0x14965e050 Required Analyses: Machine Module Information
+0x14965e050 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Workaround A53 erratum 835769 pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.123132000] 0x1496594b0 Freeing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+Running pass: Contiguously Lay Out Funclets
+[2025-06-18 00:55:38.123185000] 0x1496594b0 Executing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+0x14965d9d0 Required Analyses: Machine Module Information
+0x14965d9d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Contiguously Lay Out Funclets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.123385000] 0x1496594b0 Freeing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+Running pass: Remove Loads Into Fake Uses
+[2025-06-18 00:55:38.123456000] 0x1496594b0 Executing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+0x14965e090 Required Analyses: Machine Module Information
+0x14965e090 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Loads Into Fake Uses' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.123923000] 0x1496594b0 Freeing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+Running pass: StackMap Liveness Analysis
+[2025-06-18 00:55:38.123976000] 0x1496594b0 Executing Pass 'StackMap Liveness Analysis' on Function 'main'...
+0x14965e0f0 Required Analyses: Machine Module Information
+0x14965e0f0 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'StackMap Liveness Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.124442000] 0x1496594b0 Freeing Pass 'StackMap Liveness Analysis' on Function 'main'...
+Running pass: Live DEBUG_VALUE analysis
+[2025-06-18 00:55:38.124493000] 0x1496594b0 Executing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+0x14965e650 Required Analyses: Target Pass Configuration, Machine Module Information
+0x14965e650 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Live DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.125773000] 0x1496594b0 Freeing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Machine Sanitizer Binary Metadata
+[2025-06-18 00:55:38.125824000] 0x1496594b0 Executing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+0x14965e6b0 Required Analyses: Machine Module Information
+0x14965e6b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Sanitizer Binary Metadata' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.126020000] 0x1496594b0 Freeing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+Running pass: AArch64 sls hardening pass
+[2025-06-18 00:55:38.126071000] 0x1496594b0 Executing Pass 'AArch64 sls hardening pass' on Function 'main'...
+0x14965e190 Required Analyses: Machine Module Information
+0x14965e190 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 sls hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.126265000] 0x1496594b0 Freeing Pass 'AArch64 sls hardening pass' on Function 'main'...
+Running pass: AArch64 Pointer Authentication
+[2025-06-18 00:55:38.126315000] 0x1496594b0 Executing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+0x14965e720 Required Analyses: Machine Module Information
+0x14965e720 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Pointer Authentication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.126509000] 0x1496594b0 Freeing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+Running pass: AArch64 Branch Targets
+[2025-06-18 00:55:38.126559000] 0x1496594b0 Executing Pass 'AArch64 Branch Targets' on Function 'main'...
+0x14965e790 Required Analyses: Machine Module Information
+0x14965e790 Preserved Analyses: Spill Code Placement Analysis, Dominator Tree Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Dominance Frontier Construction, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, WebAssembly Exception Information, Assign reference type allocas to local address space, SPIRV module analysis, Cycle Info Analysis, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Print Machine Uniformity Info Analysis, Analysis if a function is memory bound, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Branch Targets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.127033000] 0x1496594b0 Freeing Pass 'AArch64 Branch Targets' on Function 'main'...
+Running pass: Branch relaxation pass
+[2025-06-18 00:55:38.127086000] 0x1496594b0 Executing Pass 'Branch relaxation pass' on Function 'main'...
+0x14965e920 Required Analyses: Machine Module Information
+0x14965e920 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch relaxation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.127285000] 0x1496594b0 Freeing Pass 'Branch relaxation pass' on Function 'main'...
+Running pass: Insert CFI remember/restore state instructions
+[2025-06-18 00:55:38.127336000] 0x1496594b0 Executing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+0x14965e960 Required Analyses: Machine Module Information
+0x14965e960 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert CFI remember/restore state instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.127534000] 0x1496594b0 Freeing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:55:38.127586000] 0x1496594b0 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x14965ea20 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x14965ea20 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:55:38.127791000] 0x1496594b0 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x14965eae0 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x14965eae0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Stack Frame Layout Analysis
+[2025-06-18 00:55:38.127991000] 0x1496594b0 Executing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+0x14965e9e0 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter
+0x14965e9e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Frame Layout Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.128217000] 0x1496594b0 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:55:38.128260000] 0x1496594b0 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:55:38.128303000] 0x1496594b0 Freeing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+Running pass: Unpack machine instruction bundles
+[2025-06-18 00:55:38.128356000] 0x1496594b0 Executing Pass 'Unpack machine instruction bundles' on Function 'main'...
+0x14965bbb0 Required Analyses: Machine Module Information
+0x14965bbb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Unpack machine instruction bundles' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.128557000] 0x1496594b0 Freeing Pass 'Unpack machine instruction bundles' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:55:38.128609000] 0x1496594b0 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x149707d40 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x149707d40 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:55:38.128816000] 0x1496594b0 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x149707d00 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x149707d00 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Assembly Printer
+[2025-06-18 00:55:38.129025000] 0x1496594b0 Executing Pass 'AArch64 Assembly Printer' on Function 'main'...
+0x14965ed40 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter, Create Garbage Collector Module Metadata, Lazy Machine Block Frequency Analysis, Machine Branch Probability Analysis
+0x14965ed40 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Uninitialized Pass, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Assembly Printer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.132362000] 0x1496594b0 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:55:38.132404000] 0x1496594b0 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:55:38.132447000] 0x1496594b0 Freeing Pass 'AArch64 Assembly Printer' on Function 'main'...
+Running pass: Free MachineFunction
+[2025-06-18 00:55:38.132499000] 0x1496594b0 Executing Pass 'Free MachineFunction' on Function 'main'...
+0x149707e70 Required Analyses: Machine Module Information
+[2025-06-18 00:55:38.132587000] 0x1496594b0 Made Modification 'Free MachineFunction' on Function 'main'...
+0x149707e70 Preserved Analyses: Machine Module Information
+ -*- 'Free MachineFunction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.132666000] 0x1496594b0 Freeing Pass 'Free MachineFunction' on Function 'main'...
+[2025-06-18 00:55:38.132708000] 0x1496492b0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:55:38.132764000] 0x1496492b0 Freeing Pass 'Target Transform Information' on Module 'test.c'...
+[2025-06-18 00:55:38.132806000] 0x1496492b0 Freeing Pass 'Assumption Cache Tracker' on Module 'test.c'...
+[2025-06-18 00:55:38.132849000] 0x1496492b0 Freeing Pass 'Target Pass Configuration' on Module 'test.c'...
+[2025-06-18 00:55:38.132890000] 0x1496492b0 Freeing Pass 'Target Library Information' on Module 'test.c'...
+[2025-06-18 00:55:38.132931000] 0x1496492b0 Freeing Pass 'Machine Branch Probability Analysis' on Module 'test.c'...
+[2025-06-18 00:55:38.132973000] 0x1496492b0 Freeing Pass 'Profile summary info' on Module 'test.c'...
+[2025-06-18 00:55:38.133016000] 0x1496492b0 Freeing Pass 'Create Garbage Collector Module Metadata' on Module 'test.c'...
+[2025-06-18 00:55:38.133058000] 0x1496492b0 Freeing Pass 'Machine Module Information' on Module 'test.c'...
diff --git a/optimization_1_new.txt b/optimization_1_new.txt
new file mode 100644
index 0000000000000..3cdb91f4d6ef1
--- /dev/null
+++ b/optimization_1_new.txt
@@ -0,0 +1,1781 @@
+ -- 'Expand large div/rem' is not preserving 'Pre-ISel Intrinsic Lowering'
+ -- 'Expand large div/rem' is not preserving 'Function Pass Manager'
+ -- 'Expand fp' is not preserving 'Expand large div/rem'
+ -- 'Expand Atomic instructions' is not preserving 'Expand fp'
+ -- 'Simplify the CFG' is not preserving 'SVE intrinsics optimizations'
+ -- 'Simplify the CFG' is not preserving 'Function Pass Manager'
+ -- 'Canonicalize natural loops' is not preserving 'Simplify the CFG'
+ -- 'Loop Data Prefetch' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Loop Data Prefetch' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Loop Data Prefetch' is not preserving 'Optimization Remark Emitter'
+ -- 'Falkor HW Prefetch Fix' is not preserving 'Canonicalize natural loops'
+ -- 'Falkor HW Prefetch Fix' is not preserving 'Loop Data Prefetch'
+ -- 'Canonicalize natural loops' is not preserving 'Falkor HW Prefetch Fix'
+ -- 'Canonicalize Freeze Instructions in Loops' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Canonicalize Freeze Instructions in Loops' is not preserving 'Loop Pass Manager'
+ -- 'Loop Strength Reduction' is not preserving 'Canonicalize Freeze Instructions in Loops'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Function Alias Analysis Results'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Natural Loop Information'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Scalar Evolution Analysis'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Canonicalize natural loops'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Merge contiguous icmps into a memcmp'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Natural Loop Information'
+ -- 'Lower Garbage Collection Instructions' is not preserving 'Expand memcmp() to load/stores'
+ -- 'Shadow Stack GC Lowering' is not preserving 'Lower Garbage Collection Instructions'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Lower @llvm.global_dtors via `__cxa_atexit`'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Function Pass Manager'
+ -- 'Constant Hoisting' is not preserving 'Branch Probability Analysis'
+ -- 'Constant Hoisting' is not preserving 'Remove unreachable blocks from the CFG'
+ -- 'Replace intrinsics with calls to vector library' is not preserving 'Constant Hoisting'
+ -- 'Partially inline calls to library functions' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Post-Dominator Tree Construction'
+ -- 'Partially inline calls to library functions' is not preserving 'Optimization Remark Emitter'
+ -- 'Partially inline calls to library functions' is not preserving 'Natural Loop Information'
+ -- 'Partially inline calls to library functions' is not preserving 'Block Frequency Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Replace intrinsics with calls to vector library'
+ -- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is not preserving 'Partially inline calls to library functions'
+ -- 'Scalarize Masked Memory Intrinsics' is not preserving 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)'
+ -- 'Expand reduction intrinsics' is not preserving 'Scalarize Masked Memory Intrinsics'
+ -- 'AArch64 Stack Tagging' is not preserving 'Function Alias Analysis Results'
+ -- 'AArch64 Stack Tagging' is not preserving 'Optimization Remark Emitter'
+ -- 'AArch64 Stack Tagging' is not preserving 'Stack Safety Analysis'
+ -- 'AArch64 Stack Tagging' is not preserving 'Function Pass Manager'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Function Alias Analysis Results'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Memory SSA'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Natural Loop Information'
+ -- 'Interleaved Load Combine Pass' is not preserving 'AArch64 Stack Tagging'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Interleaved Access Pass' is not preserving 'Interleaved Load Combine Pass'
+ -- 'SME ABI Pass' is not preserving 'Interleaved Access Pass'
+ -- 'SME ABI Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Type Promotion' is not preserving 'SME ABI Pass'
+ -- 'CodeGen Prepare' is not preserving 'Natural Loop Information'
+ -- 'CodeGen Prepare' is not preserving 'Type Promotion'
+ -- 'CodeGen Prepare' is not preserving 'Dominator Tree Construction'
+ -- 'Exception handling preparation' is not preserving 'CodeGen Prepare'
+ -- 'Merge internal globals' is not preserving 'AArch64 Promote Constant'
+ -- 'Merge internal globals' is not preserving 'Function Pass Manager'
+ -- 'ObjC ARC contraction' is not preserving 'Merge internal globals'
+ -- 'Prepare callbr' is not preserving 'Function Alias Analysis Results'
+ -- 'Prepare callbr' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Prepare callbr' is not preserving 'ObjC ARC contraction'
+ -- 'Safe Stack instrumentation pass' is not preserving 'Prepare callbr'
+ -- 'Insert stack protectors' is not preserving 'Safe Stack instrumentation pass'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Post-Dominator Tree Construction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'Assignment Tracking Analysis'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'AArch64 Instruction Selection'
+ -- 'SME Peephole Optimization pass' is not preserving 'Finalize ISel and expand pseudo-instructions'
+ -- 'Early Tail Duplication' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Early Tail Duplication' is not preserving 'SME Peephole Optimization pass'
+ -- 'Optimize machine instruction PHIs' is not preserving 'Early Tail Duplication'
+ -- 'Merge disjoint stack slots' is not preserving 'Slot index numbering'
+ -- 'Merge disjoint stack slots' is not preserving 'Optimize machine instruction PHIs'
+ -- 'Local Stack Slot Allocation' is not preserving 'Merge disjoint stack slots'
+ -- 'Remove dead machine instructions' is not preserving 'Local Stack Slot Allocation'
+ -- 'AArch64 Condition Optimizer' is not preserving 'Remove dead machine instructions'
+ -- 'AArch64 Conditional Compares' is not preserving 'AArch64 Condition Optimizer'
+ -- 'Machine InstCombiner' is not preserving 'AArch64 Conditional Compares'
+ -- 'AArch64 Conditional Branch Tuning' is not preserving 'Machine InstCombiner'
+ -- 'AArch64 Conditional Branch Tuning' is not preserving 'Machine Trace Metrics'
+ -- 'Early If-Conversion' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Early If-Conversion' is not preserving 'AArch64 Conditional Branch Tuning'
+ -- 'AArch64 Store Pair Suppression' is not preserving 'Early If-Conversion'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'MachineDominator Tree Construction'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'Machine Natural Loop Construction'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'Machine Trace Metrics'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'AArch64 Store Pair Suppression'
+ -- 'AArch64 Stack Tagging PreRA' is not preserving 'AArch64 SIMD instructions optimization pass'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'AArch64 Stack Tagging PreRA'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'MachineDominator Tree Construction'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine Common Subexpression Elimination' is not preserving 'Early Machine Loop Invariant Code Motion'
+ -- 'Machine code sinking' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'Machine Common Subexpression Elimination'
+ -- 'Machine code sinking' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine code sinking' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Peephole Optimizations' is not preserving 'Machine code sinking'
+ -- 'Remove dead machine instructions' is not preserving 'Peephole Optimizations'
+ -- 'AArch64 MI Peephole Optimization pass' is not preserving 'Remove dead machine instructions'
+ -- 'AArch64 Dead register definitions' is not preserving 'AArch64 MI Peephole Optimization pass'
+ -- 'Detect Dead Lanes' is not preserving 'AArch64 Dead register definitions'
+ -- 'Init Undef Pass' is not preserving 'Detect Dead Lanes'
+ -- 'Process Implicit Definitions' is not preserving 'Init Undef Pass'
+ -- 'Remove unreachable machine basic blocks' is not preserving 'Machine Cycle Info Analysis'
+ -- 'Remove unreachable machine basic blocks' is not preserving 'Process Implicit Definitions'
+ -- 'Eliminate PHI nodes for register allocation' is not preserving 'Remove unreachable machine basic blocks'
+ -- 'Two-Address instruction pass' is not preserving 'Eliminate PHI nodes for register allocation'
+ -- 'Live Interval Analysis' is not preserving 'Two-Address instruction pass'
+ -- 'Register Coalescer' is not preserving 'Live Variable Analysis'
+ -- 'Rename Disconnected Subregister Components' is not preserving 'Register Coalescer'
+ -- 'Machine Instruction Scheduler' is not preserving 'Rename Disconnected Subregister Components'
+ -- 'Greedy Register Allocator' is not preserving 'AArch64 Post Coalescer pass'
+ -- 'Greedy Register Allocator' is not preserving 'Machine Instruction Scheduler'
+ -- 'Virtual Register Rewriter' is not preserving 'Live Register Matrix'
+ -- 'Virtual Register Rewriter' is not preserving 'Debug Variable Analysis'
+ -- 'Virtual Register Rewriter' is not preserving 'Virtual Register Map'
+ -- 'Virtual Register Rewriter' is not preserving 'Greedy Register Allocator'
+ -- 'Stack Slot Coloring' is not preserving 'Live Stack Slot Analysis'
+ -- 'Stack Slot Coloring' is not preserving 'Virtual Register Rewriter'
+ -- 'Stack Slot Coloring' is not preserving 'Register Allocation Pass Scoring'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Live Interval Analysis'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Slot index numbering'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Stack Slot Coloring'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Copy Propagation Pass'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Spill Code Placement Analysis'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Bundle Machine CFG Edges'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Block Frequency Analysis'
+ -- 'AArch64 Redundant Copy Elimination' is not preserving 'Machine Natural Loop Construction'
+ -- 'AArch64 Redundant Copy Elimination' is not preserving 'Machine Loop Invariant Code Motion'
+ -- 'A57 FP Anti-dependency breaker' is not preserving 'AArch64 Redundant Copy Elimination'
+ -- 'Remove Redundant DEBUG_VALUE analysis' is not preserving 'A57 FP Anti-dependency breaker'
+ -- 'Fixup Statepoint Caller Saved' is not preserving 'Remove Redundant DEBUG_VALUE analysis'
+ -- 'PostRA Machine Sink' is not preserving 'Fixup Statepoint Caller Saved'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'Shrink Wrapping analysis'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'PostRA Machine Sink'
+ -- 'Machine Late Instructions Cleanup Pass' is not preserving 'Prologue/Epilogue Insertion & Frame Finalization'
+ -- 'Control Flow Optimizer' is not preserving 'MachineDominator Tree Construction'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Natural Loop Construction'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Control Flow Optimizer' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Late Instructions Cleanup Pass'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Control Flow Optimizer' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Tail Duplication' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Tail Duplication' is not preserving 'Control Flow Optimizer'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Tail Duplication'
+ -- 'Post-RA pseudo instruction expansion pass' is not preserving 'Machine Copy Propagation Pass'
+ -- 'AArch64 pseudo instruction expansion pass' is not preserving 'Post-RA pseudo instruction expansion pass'
+ -- 'AArch64 load / store optimization pass' is not preserving 'AArch64 pseudo instruction expansion pass'
+ -- 'Insert KCFI indirect call checks' is not preserving 'AArch64 load / store optimization pass'
+ -- 'AArch64 speculation hardening pass' is not preserving 'Insert KCFI indirect call checks'
+ -- 'Falkor HW Prefetch Fix Late Phase' is not preserving 'AArch64 speculation hardening pass'
+ -- 'PostRA Machine Instruction Scheduler' is not preserving 'Falkor HW Prefetch Fix Late Phase'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'MachineDominator Tree Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Machine Natural Loop Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Analyze Machine Code For Garbage Collection'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'PostRA Machine Instruction Scheduler'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Insert fentry calls' is not preserving 'Branch Probability Basic Block Placement'
+ -- 'Insert XRay ops' is not preserving 'Insert fentry calls'
+ -- 'Implement the 'patchable-function' attribute' is not preserving 'Insert XRay ops'
+ -- 'Workaround A53 erratum 835769 pass' is not preserving 'Implement the 'patchable-function' attribute'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'Workaround A53 erratum 835769 pass'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'AArch64 Collect Linker Optimization Hint (LOH)'
+ -- 'Remove Loads Into Fake Uses' is not preserving 'Contiguously Lay Out Funclets'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'StackMap Liveness Analysis'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'Remove Loads Into Fake Uses'
+ -- 'Machine Sanitizer Binary Metadata' is not preserving 'Live DEBUG_VALUE analysis'
+ -- 'AArch64 sls hardening pass' is not preserving 'Machine Outliner'
+ -- 'AArch64 sls hardening pass' is not preserving 'Function Pass Manager'
+ -- 'AArch64 Pointer Authentication' is not preserving 'AArch64 sls hardening pass'
+ -- 'AArch64 Branch Targets' is not preserving 'AArch64 Pointer Authentication'
+ -- 'Branch relaxation pass' is not preserving 'AArch64 Branch Targets'
+ -- 'AArch64 Compress Jump Tables' is not preserving 'Branch relaxation pass'
+ -- 'Unpack machine instruction bundles' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Unpack machine instruction bundles' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Stack Frame Layout Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Insert CFI remember/restore state instructions'
+ -- 'Unpack machine instruction bundles' is not preserving 'AArch64 Compress Jump Tables'
+ -- 'Free MachineFunction' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Free MachineFunction' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Free MachineFunction' is not preserving 'AArch64 Assembly Printer'
+ -- 'Free MachineFunction' is not preserving 'Unpack machine instruction bundles'
+Pass Arguments: -tti -targetlibinfo -targetpassconfig -machinemoduleinfo -assumption-cache-tracker -profile-summary-info -tbaa -scoped-noalias-aa -collector-metadata -machine-branch-prob -regalloc-evict -regalloc-priority -pre-isel-intrinsic-lowering -expand-large-div-rem -expand-fp -atomic-expand -aarch64-sve-intrinsic-opts -simplifycfg -domtree -loops -loop-simplify -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -scalar-evolution -loop-data-prefetch -aarch64-falkor-hwpf-fix -basic-aa -loop-simplify -canon-freeze -iv-users -loop-reduce -basic-aa -aa -mergeicmps -loops -lazy-branch-prob -lazy-block-freq -expand-memcmp -gc-lowering -shadow-stack-gc-lowering -lower-global-dtors -unreachableblockelim -domtree -loops -postdomtree -branch-prob -block-freq -consthoist -replace-with-veclib -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -partially-inline-libcalls -post-inline-ee-instrument -scalarize-masked-mem-intrin -expand-reductions -stack-safety -domtree -basic-aa -aa -loops -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -aarch64-stack-tagging -aa -memoryssa -interleaved-load-combine -domtree -interleaved-access -aarch64-sme-abi -domtree -loops -type-promotion -codegenprepare -domtree -dwarf-eh-prepare -aarch64-promote-const -global-merge -domtree -basic-aa -aa -objc-arc-contract -callbrprepare -safe-stack -stack-protector -basic-aa -aa -loops -postdomtree -branch-prob -debug-ata -lazy-branch-prob -lazy-block-freq -aarch64-isel -finalize-isel -aarch64-sme-peephole-opt -lazy-machine-block-freq -early-tailduplication -opt-phis -slotindexes -stack-coloring -localstackalloc -dead-mi-elimination -machinedomtree -aarch64-condopt -machine-loops -machine-trace-metrics -aarch64-ccmp -lazy-machine-block-freq -machine-combiner -aarch64-cond-br-tuning -machine-trace-metrics -early-ifcvt -aarch64-stp-suppress -aarch64-simdinstr-opt -aarch64-stack-tagging-pre-ra -machinedomtree -machine-loops -machine-block-freq -early-machinelicm -machinedomtree -machine-block-freq -machine-cse -machinepostdomtree -machine-cycles -machine-sink -peephole-opt -dead-mi-elimination -aarch64-mi-peephole-opt -aarch64-dead-defs -detect-dead-lanes -init-undef -processimpdefs -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -machinedomtree -slotindexes -liveintervals -register-coalescer -rename-independent-subregs -machine-scheduler -aarch64-post-coalescer-pass -machine-block-freq -livedebugvars -livestacks -virtregmap -liveregmatrix -edge-bundles -spill-code-placement -lazy-machine-block-freq -machine-opt-remark-emitter -greedy -virtregrewriter -regallocscoringpass -stack-slot-coloring -machine-cp -machinelicm -aarch64-copyelim -aarch64-a57-fp-load-balancing -removeredundantdebugvalues -fixup-statepoint-caller-saved -postra-machine-sink -machinedomtree -machine-loops -machine-block-freq -machinepostdomtree -lazy-machine-block-freq -machine-opt-remark-emitter -shrink-wrap -prologepilog -machine-latecleanup -branch-folder -lazy-machine-block-freq -tailduplication -machine-cp -postrapseudos -aarch64-expand-pseudo -aarch64-ldst-opt -kcfi -aarch64-speculation-hardening -machinedomtree -machine-loops -aarch64-falkor-hwpf-fix-late -postmisched -gc-analysis -machine-block-freq -machinepostdomtree -block-placement -fentry-insert -xray-instrumentation -patchable-function -aarch64-fix-cortex-a53-835769-pass -aarch64-collect-loh -funclet-layout -remove-loads-into-fake-uses -stackmap-liveness -livedebugvalues -machine-sanmd -machine-outliner -aarch64-sls-hardening -aarch64-ptrauth -aarch64-branch-targets -branch-relaxation -aarch64-jump-tables -cfi-fixup -lazy-machine-block-freq -machine-opt-remark-emitter -stack-frame-layout -unpack-mi-bundles -lazy-machine-block-freq -machine-opt-remark-emitter -aarch64-asm-printer
+Target Transform Information
+Target Library Information
+Target Pass Configuration
+Machine Module Information
+Assumption Cache Tracker
+Profile summary info
+Type-Based Alias Analysis
+Scoped NoAlias Alias Analysis
+Create Garbage Collector Module Metadata
+Machine Branch Probability Analysis
+Default Regalloc Eviction Advisor
+Default Regalloc Priority Advisor
+ ModulePass Manager
+ Pre-ISel Intrinsic Lowering
+-- Pre-ISel Intrinsic Lowering
+ FunctionPass Manager
+ Expand large div/rem
+-- Expand large div/rem
+ Expand fp
+-- Expand fp
+ Expand Atomic instructions
+-- Expand Atomic instructions
+ SVE intrinsics optimizations
+ FunctionPass Manager
+ Dominator Tree Construction
+-- SVE intrinsics optimizations
+ FunctionPass Manager
+ Simplify the CFG
+-- Simplify the CFG
+ Dominator Tree Construction
+ Natural Loop Information
+ Canonicalize natural loops
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Scalar Evolution Analysis
+ Loop Data Prefetch
+-- Loop Data Prefetch
+-- Lazy Block Frequency Analysis
+-- Canonicalize natural loops
+-- Optimization Remark Emitter
+-- Lazy Branch Probability Analysis
+ Falkor HW Prefetch Fix
+-- Falkor HW Prefetch Fix
+ Basic Alias Analysis (stateless AA impl)
+-- Basic Alias Analysis (stateless AA impl)
+ Canonicalize natural loops
+ Loop Pass Manager
+ Canonicalize Freeze Instructions in Loops
+-- Canonicalize Freeze Instructions in Loops
+ Induction Variable Users
+ Loop Strength Reduction
+-- Induction Variable Users
+-- Loop Strength Reduction
+-- Natural Loop Information
+-- Scalar Evolution Analysis
+-- Canonicalize natural loops
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Merge contiguous icmps into a memcmp
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- Merge contiguous icmps into a memcmp
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Expand memcmp() to load/stores
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Dominator Tree Construction
+-- Expand memcmp() to load/stores
+ Lower Garbage Collection Instructions
+-- Lower Garbage Collection Instructions
+ Shadow Stack GC Lowering
+-- Shadow Stack GC Lowering
+ Lower @llvm.global_dtors via `__cxa_atexit`
+-- Lower @llvm.global_dtors via `__cxa_atexit`
+ FunctionPass Manager
+ Remove unreachable blocks from the CFG
+-- Remove unreachable blocks from the CFG
+ Dominator Tree Construction
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Block Frequency Analysis
+ Constant Hoisting
+-- Block Frequency Analysis
+-- Branch Probability Analysis
+-- Post-Dominator Tree Construction
+-- Constant Hoisting
+ Replace intrinsics with calls to vector library
+-- Replace intrinsics with calls to vector library
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Partially inline calls to library functions
+-- Optimization Remark Emitter
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Dominator Tree Construction
+-- Partially inline calls to library functions
+ Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+-- Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+ Scalarize Masked Memory Intrinsics
+-- Scalarize Masked Memory Intrinsics
+ Expand reduction intrinsics
+-- Expand reduction intrinsics
+ Stack Safety Analysis
+ FunctionPass Manager
+ Dominator Tree Construction
+ Natural Loop Information
+ Scalar Evolution Analysis
+ Stack Safety Local Analysis
+ FunctionPass Manager
+ Dominator Tree Construction
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ AArch64 Stack Tagging
+-- Function Alias Analysis Results
+-- AArch64 Stack Tagging
+-- Lazy Block Frequency Analysis
+-- Optimization Remark Emitter
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+ Function Alias Analysis Results
+ Memory SSA
+ Interleaved Load Combine Pass
+-- Memory SSA
+-- Basic Alias Analysis (stateless AA impl)
+-- Function Alias Analysis Results
+-- Dominator Tree Construction
+-- Interleaved Load Combine Pass
+ Dominator Tree Construction
+ Interleaved Access Pass
+-- Dominator Tree Construction
+-- Interleaved Access Pass
+ SME ABI Pass
+-- SME ABI Pass
+ Dominator Tree Construction
+ Natural Loop Information
+ Type Promotion
+-- Type Promotion
+ CodeGen Prepare
+-- Natural Loop Information
+-- Dominator Tree Construction
+-- CodeGen Prepare
+ Dominator Tree Construction
+ Exception handling preparation
+-- Dominator Tree Construction
+-- Exception handling preparation
+-- Stack Safety Analysis
+-- Target Transform Information
+ AArch64 Promote Constant
+ FunctionPass Manager
+ Dominator Tree Construction
+-- AArch64 Promote Constant
+ FunctionPass Manager
+ Merge internal globals
+-- Merge internal globals
+ Dominator Tree Construction
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ ObjC ARC contraction
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- ObjC ARC contraction
+ Prepare callbr
+-- Prepare callbr
+ Safe Stack instrumentation pass
+-- Safe Stack instrumentation pass
+ Insert stack protectors
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Assignment Tracking Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ AArch64 Instruction Selection
+-- Insert stack protectors
+-- Post-Dominator Tree Construction
+-- AArch64 Instruction Selection
+-- Lazy Branch Probability Analysis
+-- Lazy Block Frequency Analysis
+-- Assignment Tracking Analysis
+-- Branch Probability Analysis
+-- Natural Loop Information
+ Finalize ISel and expand pseudo-instructions
+-- Finalize ISel and expand pseudo-instructions
+ SME Peephole Optimization pass
+-- SME Peephole Optimization pass
+ Lazy Machine Block Frequency Analysis
+ Early Tail Duplication
+-- Lazy Machine Block Frequency Analysis
+-- Early Tail Duplication
+ Optimize machine instruction PHIs
+-- Optimize machine instruction PHIs
+ Slot index numbering
+ Merge disjoint stack slots
+-- Slot index numbering
+-- Merge disjoint stack slots
+ Local Stack Slot Allocation
+-- Local Stack Slot Allocation
+ Remove dead machine instructions
+-- Remove dead machine instructions
+ MachineDominator Tree Construction
+ AArch64 Condition Optimizer
+-- AArch64 Condition Optimizer
+ Machine Natural Loop Construction
+ Machine Trace Metrics
+ AArch64 Conditional Compares
+-- AArch64 Conditional Compares
+ Lazy Machine Block Frequency Analysis
+ Machine InstCombiner
+-- Machine InstCombiner
+-- Machine Trace Metrics
+-- Lazy Machine Block Frequency Analysis
+ AArch64 Conditional Branch Tuning
+-- AArch64 Conditional Branch Tuning
+ Machine Trace Metrics
+ Early If-Conversion
+-- MachineDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Early If-Conversion
+ AArch64 Store Pair Suppression
+-- Machine Trace Metrics
+-- AArch64 Store Pair Suppression
+ AArch64 SIMD instructions optimization pass
+-- AArch64 SIMD instructions optimization pass
+ AArch64 Stack Tagging PreRA
+-- AArch64 Stack Tagging PreRA
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Machine Block Frequency Analysis
+ Early Machine Loop Invariant Code Motion
+-- Early Machine Loop Invariant Code Motion
+-- Machine Block Frequency Analysis
+-- MachineDominator Tree Construction
+ MachineDominator Tree Construction
+ Machine Block Frequency Analysis
+ Machine Common Subexpression Elimination
+-- Machine Common Subexpression Elimination
+ MachinePostDominator Tree Construction
+ Machine Cycle Info Analysis
+ Machine code sinking
+-- Machine code sinking
+-- Machine Block Frequency Analysis
+-- Machine Cycle Info Analysis
+-- MachineDominator Tree Construction
+-- MachinePostDominator Tree Construction
+ Peephole Optimizations
+-- Peephole Optimizations
+ Remove dead machine instructions
+-- Remove dead machine instructions
+ AArch64 MI Peephole Optimization pass
+-- AArch64 MI Peephole Optimization pass
+ AArch64 Dead register definitions
+-- AArch64 Dead register definitions
+ Detect Dead Lanes
+-- Detect Dead Lanes
+ Init Undef Pass
+-- Init Undef Pass
+ Process Implicit Definitions
+-- Process Implicit Definitions
+ Remove unreachable machine basic blocks
+ Live Variable Analysis
+ Eliminate PHI nodes for register allocation
+-- Eliminate PHI nodes for register allocation
+-- Remove unreachable machine basic blocks
+ Two-Address instruction pass
+-- Two-Address instruction pass
+-- Live Variable Analysis
+ MachineDominator Tree Construction
+ Slot index numbering
+ Live Interval Analysis
+ Register Coalescer
+-- Register Coalescer
+ Rename Disconnected Subregister Components
+-- Rename Disconnected Subregister Components
+ Machine Instruction Scheduler
+-- Machine Instruction Scheduler
+ AArch64 Post Coalescer pass
+-- AArch64 Post Coalescer pass
+ Machine Block Frequency Analysis
+ Debug Variable Analysis
+ Live Stack Slot Analysis
+ Virtual Register Map
+ Live Register Matrix
+ Bundle Machine CFG Edges
+ Spill Code Placement Analysis
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Greedy Register Allocator
+-- Lazy Machine Block Frequency Analysis
+-- Spill Code Placement Analysis
+-- Greedy Register Allocator
+-- Machine Optimization Remark Emitter
+-- Bundle Machine CFG Edges
+ Virtual Register Rewriter
+-- Debug Variable Analysis
+-- Live Register Matrix
+-- Live Interval Analysis
+-- Virtual Register Map
+-- Virtual Register Rewriter
+ Register Allocation Pass Scoring
+-- Register Allocation Pass Scoring
+ Stack Slot Coloring
+-- Live Stack Slot Analysis
+-- Slot index numbering
+-- Stack Slot Coloring
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Machine Loop Invariant Code Motion
+-- Machine Natural Loop Construction
+-- Machine Block Frequency Analysis
+-- MachineDominator Tree Construction
+-- Machine Loop Invariant Code Motion
+ AArch64 Redundant Copy Elimination
+-- AArch64 Redundant Copy Elimination
+ A57 FP Anti-dependency breaker
+-- A57 FP Anti-dependency breaker
+ Remove Redundant DEBUG_VALUE analysis
+-- Remove Redundant DEBUG_VALUE analysis
+ Fixup Statepoint Caller Saved
+-- Fixup Statepoint Caller Saved
+ PostRA Machine Sink
+-- PostRA Machine Sink
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Machine Block Frequency Analysis
+ MachinePostDominator Tree Construction
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Shrink Wrapping analysis
+-- Lazy Machine Block Frequency Analysis
+-- MachinePostDominator Tree Construction
+-- MachineDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Shrink Wrapping analysis
+ Prologue/Epilogue Insertion & Frame Finalization
+-- Machine Optimization Remark Emitter
+-- Prologue/Epilogue Insertion & Frame Finalization
+ Machine Late Instructions Cleanup Pass
+-- Machine Late Instructions Cleanup Pass
+ Control Flow Optimizer
+-- Machine Block Frequency Analysis
+-- Control Flow Optimizer
+ Lazy Machine Block Frequency Analysis
+ Tail Duplication
+-- Lazy Machine Block Frequency Analysis
+-- Tail Duplication
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Post-RA pseudo instruction expansion pass
+-- Post-RA pseudo instruction expansion pass
+ AArch64 pseudo instruction expansion pass
+-- AArch64 pseudo instruction expansion pass
+ AArch64 load / store optimization pass
+-- AArch64 load / store optimization pass
+ Insert KCFI indirect call checks
+-- Insert KCFI indirect call checks
+ AArch64 speculation hardening pass
+-- AArch64 speculation hardening pass
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Falkor HW Prefetch Fix Late Phase
+-- Falkor HW Prefetch Fix Late Phase
+ PostRA Machine Instruction Scheduler
+-- MachineDominator Tree Construction
+-- PostRA Machine Instruction Scheduler
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- Dominator Tree Construction
+ Analyze Machine Code For Garbage Collection
+-- Analyze Machine Code For Garbage Collection
+ Machine Block Frequency Analysis
+ MachinePostDominator Tree Construction
+ Branch Probability Basic Block Placement
+-- Machine Block Frequency Analysis
+-- MachinePostDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Branch Probability Basic Block Placement
+ Insert fentry calls
+-- Insert fentry calls
+ Insert XRay ops
+-- Insert XRay ops
+ Implement the 'patchable-function' attribute
+-- Implement the 'patchable-function' attribute
+ Workaround A53 erratum 835769 pass
+-- Workaround A53 erratum 835769 pass
+ AArch64 Collect Linker Optimization Hint (LOH)
+-- AArch64 Collect Linker Optimization Hint (LOH)
+ Contiguously Lay Out Funclets
+-- Contiguously Lay Out Funclets
+ Remove Loads Into Fake Uses
+-- Remove Loads Into Fake Uses
+ StackMap Liveness Analysis
+-- StackMap Liveness Analysis
+ Live DEBUG_VALUE analysis
+-- Live DEBUG_VALUE analysis
+ Machine Sanitizer Binary Metadata
+-- Machine Sanitizer Binary Metadata
+-- Target Library Information
+-- Type-Based Alias Analysis
+-- Target Pass Configuration
+-- Profile summary info
+-- Assumption Cache Tracker
+-- Scoped NoAlias Alias Analysis
+-- Default Regalloc Priority Advisor
+-- Default Regalloc Eviction Advisor
+ Machine Outliner
+-- Machine Outliner
+ FunctionPass Manager
+ AArch64 sls hardening pass
+-- AArch64 sls hardening pass
+ AArch64 Pointer Authentication
+-- AArch64 Pointer Authentication
+ AArch64 Branch Targets
+-- AArch64 Branch Targets
+ Branch relaxation pass
+-- Branch relaxation pass
+ AArch64 Compress Jump Tables
+-- AArch64 Compress Jump Tables
+ Insert CFI remember/restore state instructions
+-- Insert CFI remember/restore state instructions
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Stack Frame Layout Analysis
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Stack Frame Layout Analysis
+ Unpack machine instruction bundles
+-- Unpack machine instruction bundles
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ AArch64 Assembly Printer
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- AArch64 Assembly Printer
+ Free MachineFunction
+-- Free MachineFunction
+-- Create Garbage Collector Module Metadata
+-- Machine Branch Probability Analysis
+-- Machine Module Information
+Pass Arguments: -domtree
+ FunctionPass Manager
+ Dominator Tree Construction
+Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution -stack-safety-local
+Assumption Cache Tracker
+Target Library Information
+ FunctionPass Manager
+ Dominator Tree Construction
+ Natural Loop Information
+ Scalar Evolution Analysis
+ Stack Safety Local Analysis
+Pass Arguments: -domtree
+ FunctionPass Manager
+ Dominator Tree Construction
+Running pass: Pre-ISel Intrinsic Lowering
+[2025-06-18 00:56:24.124536000] 0x1497153f0 Executing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+0x149719830 Required Analyses: Target Transform Information, Target Library Information, Target Pass Configuration
+ -*- 'Pre-ISel Intrinsic Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.125452000] 0x1497153f0 Freeing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:56:24.125504000] 0x1497153f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Expand large div/rem
+[2025-06-18 00:56:24.125557000] 0x1497198b0 Executing Pass 'Expand large div/rem' on Function 'main'...
+0x149719870 Required Analyses: Target Pass Configuration
+0x149719870 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand large div/rem' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.125677000] 0x1497198b0 Freeing Pass 'Expand large div/rem' on Function 'main'...
+Running pass: Expand fp
+[2025-06-18 00:56:24.125729000] 0x1497198b0 Executing Pass 'Expand fp' on Function 'main'...
+0x149719800 Required Analyses: Target Pass Configuration
+0x149719800 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand fp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.125847000] 0x1497198b0 Freeing Pass 'Expand fp' on Function 'main'...
+Running pass: Expand Atomic instructions
+[2025-06-18 00:56:24.125899000] 0x1497198b0 Executing Pass 'Expand Atomic instructions' on Function 'main'...
+ -*- 'Expand Atomic instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.125957000] 0x1497198b0 Freeing Pass 'Expand Atomic instructions' on Function 'main'...
+Running pass: SVE intrinsics optimizations
+[2025-06-18 00:56:24.126009000] 0x1497153f0 Executing Pass 'SVE intrinsics optimizations' on Module 'test.c'...
+0x149719ad0 Required Analyses: Dominator Tree Construction
+0x149719ad0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'SVE intrinsics optimizations' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.126437000] 0x1497153f0 Freeing Pass 'SVE intrinsics optimizations' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:56:24.126490000] 0x1497153f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Simplify the CFG
+[2025-06-18 00:56:24.126543000] 0x14971a1c0 Executing Pass 'Simplify the CFG' on Function 'main'...
+0x149719d70 Required Analyses: Assumption Cache Tracker, Target Transform Information
+0x149719d70 Preserved Analyses: Globals Alias Analysis
+ -*- 'Simplify the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.126664000] 0x14971a1c0 Freeing Pass 'Simplify the CFG' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.126716000] 0x14971a1c0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:56:24.126770000] 0x14971a1c0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x149714fe0 Required Analyses: Dominator Tree Construction
+Running pass: Canonicalize natural loops
+[2025-06-18 00:56:24.126848000] 0x14971a1c0 Executing Pass 'Canonicalize natural loops' on Function 'main'...
+0x1497150b0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information
+0x1497150b0 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Basic Alias Analysis (stateless AA impl), Function Alias Analysis Results, Globals Alias Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Loop-Closed SSA Form Pass, Uninitialized Pass, Branch Probability Analysis, Memory SSA
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:56:24.127069000] 0x14971a1c0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x1497152d0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:56:24.127166000] 0x14971a1c0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x1497150f0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:56:24.127273000] 0x14971a1c0 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x1497152a0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Scalar Evolution Analysis
+[2025-06-18 00:56:24.127390000] 0x14971a1c0 Executing Pass 'Scalar Evolution Analysis' on Function 'main'...
+0x1497151d0 Required Analyses: Assumption Cache Tracker, Natural Loop Information, Dominator Tree Construction, Target Library Information
+Running pass: Loop Data Prefetch
+[2025-06-18 00:56:24.127507000] 0x14971a1c0 Executing Pass 'Loop Data Prefetch' on Function 'main'...
+0x14971a380 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information, Canonicalize natural loops, Optimization Remark Emitter, Scalar Evolution Analysis, Target Transform Information
+0x14971a380 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Canonicalize natural loops, Scalar Evolution Analysis
+ -*- 'Loop Data Prefetch' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.127716000] 0x14971a1c0 Freeing Pass 'Loop Data Prefetch' on Function 'main'...
+[2025-06-18 00:56:24.127759000] 0x14971a1c0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.127800000] 0x14971a1c0 Freeing Pass 'Canonicalize natural loops' on Function 'main'...
+[2025-06-18 00:56:24.127842000] 0x14971a1c0 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.127908000] 0x14971a1c0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+Running pass: Falkor HW Prefetch Fix
+[2025-06-18 00:56:24.128093000] 0x14971a1c0 Executing Pass 'Falkor HW Prefetch Fix' on Function 'main'...
+0x149715650 Required Analyses: Target Pass Configuration, Natural Loop Information, Scalar Evolution Analysis
+0x149715650 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Scalar Evolution Analysis
+ -*- 'Falkor HW Prefetch Fix' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.128241000] 0x14971a1c0 Freeing Pass 'Falkor HW Prefetch Fix' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:56:24.128298000] 0x14971a1c0 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x149715730 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+ -*- 'Basic Alias Analysis (stateless AA impl)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.128398000] 0x14971a1c0 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+Running pass: Canonicalize natural loops
+[2025-06-18 00:56:24.128450000] 0x14971a1c0 Executing Pass 'Canonicalize natural loops' on Function 'main'...
+0x149715890 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information
+0x149715890 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Basic Alias Analysis (stateless AA impl), Function Alias Analysis Results, Globals Alias Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Loop-Closed SSA Form Pass, Uninitialized Pass, Branch Probability Analysis, Memory SSA
+Running pass: Loop Pass Manager
+[2025-06-18 00:56:24.128668000] 0x14971a1c0 Executing Pass 'Loop Pass Manager' on Function 'main'...
+0x149715910 Required Analyses: Natural Loop Information, Dominator Tree Construction
+ -*- 'Loop Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.128767000] 0x14971a1c0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:56:24.128809000] 0x14971a1c0 Freeing Pass 'Scalar Evolution Analysis' on Function 'main'...
+[2025-06-18 00:56:24.128853000] 0x14971a1c0 Freeing Pass 'Canonicalize natural loops' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:56:24.128905000] 0x14971a1c0 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x1496063c0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:56:24.129001000] 0x14971a1c0 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x1496064c0 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x1496064c0 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Merge contiguous icmps into a memcmp
+[2025-06-18 00:56:24.129158000] 0x14971a1c0 Executing Pass 'Merge contiguous icmps into a memcmp' on Function 'main'...
+0x149606440 Required Analyses: Target Library Information, Target Transform Information, Function Alias Analysis Results
+0x149606440 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Merge contiguous icmps into a memcmp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.129680000] 0x14971a1c0 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:56:24.129733000] 0x14971a1c0 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:56:24.129796000] 0x14971a1c0 Freeing Pass 'Merge contiguous icmps into a memcmp' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:56:24.129848000] 0x14971a1c0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x149606710 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:56:24.129933000] 0x14971a1c0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x149606530 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:56:24.130033000] 0x14971a1c0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x149606930 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Expand memcmp() to load/stores
+[2025-06-18 00:56:24.130141000] 0x14971a1c0 Executing Pass 'Expand memcmp() to load/stores' on Function 'main'...
+0x149606690 Required Analyses: Target Library Information, Target Transform Information, Profile summary info, Lazy Branch Probability Analysis, Natural Loop Information, Lazy Block Frequency Analysis
+0x149606690 Preserved Analyses: Dominator Tree Construction
+ -*- 'Expand memcmp() to load/stores' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.130301000] 0x14971a1c0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.130343000] 0x14971a1c0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:56:24.130385000] 0x14971a1c0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:56:24.130427000] 0x14971a1c0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.130468000] 0x14971a1c0 Freeing Pass 'Expand memcmp() to load/stores' on Function 'main'...
+Running pass: Lower Garbage Collection Instructions
+[2025-06-18 00:56:24.130520000] 0x14971a1c0 Executing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+0x1496069a0 Required Analyses: Create Garbage Collector Module Metadata
+0x1496069a0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Lower Garbage Collection Instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.130623000] 0x14971a1c0 Freeing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+Running pass: Shadow Stack GC Lowering
+[2025-06-18 00:56:24.130674000] 0x14971a1c0 Executing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+0x149606a80 Preserved Analyses: Dominator Tree Construction
+ -*- 'Shadow Stack GC Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.130754000] 0x14971a1c0 Freeing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+Running pass: Lower @llvm.global_dtors via `__cxa_atexit`
+[2025-06-18 00:56:24.130805000] 0x1497153f0 Executing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+0x149606af0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'Lower @llvm.global_dtors via `__cxa_atexit`' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.131195000] 0x1497153f0 Freeing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:56:24.131247000] 0x1497153f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Remove unreachable blocks from the CFG
+[2025-06-18 00:56:24.131299000] 0x149606b70 Executing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+0x149606b30 Preserved Analyses: Dominator Tree Construction
+ -*- 'Remove unreachable blocks from the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.131380000] 0x149606b70 Freeing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.131432000] 0x149606b70 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:56:24.131485000] 0x149606b70 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x149607150 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:56:24.131561000] 0x149606b70 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:56:24.131618000] 0x149606b70 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x149606f90 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Block Frequency Analysis
+[2025-06-18 00:56:24.132090000] 0x149606b70 Executing Pass 'Block Frequency Analysis' on Function 'main'...
+0x1496066e0 Required Analyses: Branch Probability Analysis, Natural Loop Information
+Running pass: Constant Hoisting
+[2025-06-18 00:56:24.133419000] 0x149606b70 Executing Pass 'Constant Hoisting' on Function 'main'...
+0x149827000 Required Analyses: Block Frequency Analysis, Dominator Tree Construction, Profile summary info, Target Transform Information
+0x149827000 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'Constant Hoisting' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.133870000] 0x149606b70 Freeing Pass 'Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.133913000] 0x149606b70 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:56:24.133956000] 0x149606b70 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.133997000] 0x149606b70 Freeing Pass 'Constant Hoisting' on Function 'main'...
+Running pass: Replace intrinsics with calls to vector library
+[2025-06-18 00:56:24.134049000] 0x149606b70 Executing Pass 'Replace intrinsics with calls to vector library' on Function 'main'...
+0x149607280 Required Analyses: Target Library Information
+0x149607280 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Target Library Information, Scalar Evolution Analysis, Function Alias Analysis Results, Optimization Remark Emitter, Globals Alias Analysis
+ -*- 'Replace intrinsics with calls to vector library' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.134519000] 0x149606b70 Freeing Pass 'Replace intrinsics with calls to vector library' on Function 'main'...
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:56:24.134571000] 0x149606b70 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x1496074f0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:56:24.134666000] 0x149606b70 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x149607570 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:56:24.134772000] 0x149606b70 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x1496074c0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Partially inline calls to library functions
+[2025-06-18 00:56:24.134888000] 0x149606b70 Executing Pass 'Partially inline calls to library functions' on Function 'main'...
+0x149607430 Required Analyses: Target Library Information, Target Transform Information, Optimization Remark Emitter
+0x149607430 Preserved Analyses: Dominator Tree Construction
+ -*- 'Partially inline calls to library functions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.135013000] 0x149606b70 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.135054000] 0x149606b70 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.135106000] 0x149606b70 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:56:24.135151000] 0x149606b70 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:56:24.135192000] 0x149606b70 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.135243000] 0x149606b70 Freeing Pass 'Partially inline calls to library functions' on Function 'main'...
+Running pass: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+[2025-06-18 00:56:24.135295000] 0x149606b70 Executing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+0x149607620 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.135403000] 0x149606b70 Freeing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+Running pass: Scalarize Masked Memory Intrinsics
+[2025-06-18 00:56:24.135454000] 0x149606b70 Executing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+0x1496076a0 Required Analyses: Target Transform Information
+0x1496076a0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Scalarize Masked Memory Intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.136713000] 0x149606b70 Freeing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+Running pass: Expand reduction intrinsics
+[2025-06-18 00:56:24.136766000] 0x149606b70 Executing Pass 'Expand reduction intrinsics' on Function 'main'...
+0x149607750 Required Analyses: Target Transform Information
+0x149607750 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'Expand reduction intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.137155000] 0x149606b70 Freeing Pass 'Expand reduction intrinsics' on Function 'main'...
+Running pass: Stack Safety Analysis
+[2025-06-18 00:56:24.137207000] 0x1497153f0 Executing Pass 'Stack Safety Analysis' on Module 'test.c'...
+0x149607bb0 Required Analyses: Stack Safety Local Analysis
+Running pass: Function Pass Manager
+[2025-06-18 00:56:24.137284000] 0x1497153f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.137336000] 0x1497295e0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:56:24.137388000] 0x1497295e0 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x1497294c0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:56:24.137485000] 0x1497295e0 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x149715d90 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x149715d90 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Natural Loop Information
+[2025-06-18 00:56:24.137636000] 0x1497295e0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x149729890 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:56:24.137712000] 0x1497295e0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x149729830 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:56:24.137808000] 0x1497295e0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x149729980 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:56:24.137960000] 0x1497295e0 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x1497294f0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: AArch64 Stack Tagging
+[2025-06-18 00:56:24.138077000] 0x1497295e0 Executing Pass 'AArch64 Stack Tagging' on Function 'main'...
+0x1496078f0 Required Analyses: Stack Safety Analysis, Function Alias Analysis Results, Optimization Remark Emitter
+0x1496078f0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'AArch64 Stack Tagging' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.138492000] 0x1497295e0 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:56:24.138534000] 0x1497295e0 Freeing Pass 'AArch64 Stack Tagging' on Function 'main'...
+[2025-06-18 00:56:24.138575000] 0x1497295e0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.138617000] 0x1497295e0 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.138659000] 0x1497295e0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:56:24.138700000] 0x1497295e0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:56:24.138762000] 0x1497295e0 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x149729a50 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x149729a50 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Memory SSA
+[2025-06-18 00:56:24.138916000] 0x1497295e0 Executing Pass 'Memory SSA' on Function 'main'...
+0x149729860 Required Analyses: Dominator Tree Construction, Function Alias Analysis Results
+Running pass: Interleaved Load Combine Pass
+[2025-06-18 00:56:24.139006000] 0x1497295e0 Executing Pass 'Interleaved Load Combine Pass' on Function 'main'...
+0x149729a30 Required Analyses: Memory SSA, Dominator Tree Construction, Target Transform Information
+ -*- 'Interleaved Load Combine Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.140598000] 0x1497295e0 Freeing Pass 'Memory SSA' on Function 'main'...
+[2025-06-18 00:56:24.140642000] 0x1497295e0 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:56:24.140684000] 0x1497295e0 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:56:24.140726000] 0x1497295e0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.140768000] 0x1497295e0 Freeing Pass 'Interleaved Load Combine Pass' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.140838000] 0x1497295e0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Interleaved Access Pass
+[2025-06-18 00:56:24.140891000] 0x1497295e0 Executing Pass 'Interleaved Access Pass' on Function 'main'...
+0x149729a80 Required Analyses: Dominator Tree Construction
+0x149729a80 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'Interleaved Access Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.141284000] 0x1497295e0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.141326000] 0x1497295e0 Freeing Pass 'Interleaved Access Pass' on Function 'main'...
+Running pass: SME ABI Pass
+[2025-06-18 00:56:24.141377000] 0x1497295e0 Executing Pass 'SME ABI Pass' on Function 'main'...
+ -*- 'SME ABI Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.141435000] 0x1497295e0 Freeing Pass 'SME ABI Pass' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.141487000] 0x1497295e0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:56:24.141540000] 0x1497295e0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x149729c60 Required Analyses: Dominator Tree Construction
+Running pass: Type Promotion
+[2025-06-18 00:56:24.141618000] 0x1497295e0 Executing Pass 'Type Promotion' on Function 'main'...
+0x149729c40 Required Analyses: Natural Loop Information, Target Transform Information, Target Pass Configuration
+0x149729c40 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'Type Promotion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.142831000] 0x1497295e0 Freeing Pass 'Type Promotion' on Function 'main'...
+Running pass: CodeGen Prepare
+[2025-06-18 00:56:24.142884000] 0x1497295e0 Executing Pass 'CodeGen Prepare' on Function 'main'...
+0x149729f20 Required Analyses: Profile summary info, Target Library Information, Target Pass Configuration, Target Transform Information, Natural Loop Information
+0x149729f20 Used Analyses: Reads and parses a basic block sections profile.
+ -*- 'CodeGen Prepare' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.144904000] 0x1497295e0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:56:24.144945000] 0x1497295e0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.144986000] 0x1497295e0 Freeing Pass 'CodeGen Prepare' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.145036000] 0x1497295e0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Exception handling preparation
+[2025-06-18 00:56:24.145088000] 0x1497295e0 Executing Pass 'Exception handling preparation' on Function 'main'...
+0x14972a070 Required Analyses: Target Pass Configuration, Target Transform Information, Dominator Tree Construction
+0x14972a070 Preserved Analyses: Dominator Tree Construction
+ -*- 'Exception handling preparation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.145211000] 0x1497295e0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.145252000] 0x1497295e0 Freeing Pass 'Exception handling preparation' on Function 'main'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.145306000] 0x1497153f0 Freeing Pass 'Stack Safety Analysis' on Module 'test.c'...
+[2025-06-18 00:56:24.145346000] 0x1497153f0 Freeing Pass 'Target Transform Information' on Module 'test.c'...
+Running pass: AArch64 Promote Constant
+[2025-06-18 00:56:24.145397000] 0x1497153f0 Executing Pass 'AArch64 Promote Constant' on Module 'test.c'...
+0x14972a270 Required Analyses: Dominator Tree Construction
+0x14972a270 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'AArch64 Promote Constant' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.145779000] 0x1497153f0 Freeing Pass 'AArch64 Promote Constant' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:56:24.145831000] 0x1497153f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Merge internal globals
+[2025-06-18 00:56:24.145882000] 0x14972a840 Executing Pass 'Merge internal globals' on Function 'main'...
+0x14972a720 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges
+ -*- 'Merge internal globals' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.146264000] 0x14972a840 Freeing Pass 'Merge internal globals' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:56:24.146314000] 0x14972a840 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:56:24.146366000] 0x14972a840 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x14972aa80 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:56:24.146460000] 0x14972a840 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x14972aa20 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x14972aa20 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: ObjC ARC contraction
+[2025-06-18 00:56:24.146609000] 0x14972a840 Executing Pass 'ObjC ARC contraction' on Function 'main'...
+0x14972aa00 Required Analyses: Function Alias Analysis Results, Dominator Tree Construction
+0x14972aa00 Preserved Analyses: Function Alias Analysis Results, Basic Alias Analysis (stateless AA impl), Dominator Tree Construction
+ -*- 'ObjC ARC contraction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.146762000] 0x14972a840 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:56:24.146805000] 0x14972a840 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:56:24.146845000] 0x14972a840 Freeing Pass 'ObjC ARC contraction' on Function 'main'...
+Running pass: Prepare callbr
+[2025-06-18 00:56:24.146897000] 0x14972a840 Executing Pass 'Prepare callbr' on Function 'main'...
+0x14972aba0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Prepare callbr' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.146979000] 0x14972a840 Freeing Pass 'Prepare callbr' on Function 'main'...
+Running pass: Safe Stack instrumentation pass
+[2025-06-18 00:56:24.147030000] 0x14972a840 Executing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+0x14972aab0 Required Analyses: Target Pass Configuration, Target Library Information, Assumption Cache Tracker
+0x14972aab0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Safe Stack instrumentation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.147150000] 0x14972a840 Freeing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+Running pass: Insert stack protectors
+[2025-06-18 00:56:24.147201000] 0x14972a840 Executing Pass 'Insert stack protectors' on Function 'main'...
+0x14972add0 Required Analyses: Target Pass Configuration
+0x14972add0 Preserved Analyses: Dominator Tree Construction
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:56:24.147300000] 0x14972a840 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x159639930 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:56:24.147394000] 0x14972a840 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x1596399c0 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x1596399c0 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Natural Loop Information
+[2025-06-18 00:56:24.147576000] 0x14972a840 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x159639b30 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:56:24.147660000] 0x14972a840 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:56:24.147712000] 0x14972a840 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x159639a10 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Assignment Tracking Analysis
+[2025-06-18 00:56:24.147822000] 0x14972a840 Executing Pass 'Assignment Tracking Analysis' on Function 'main'...
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:56:24.147874000] 0x14972a840 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x159639ee0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:56:24.147968000] 0x14972a840 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x159639f60 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: AArch64 Instruction Selection
+[2025-06-18 00:56:24.148075000] 0x14972a840 Executing Pass 'AArch64 Instruction Selection' on Function 'main'...
+0x14972ac20 Required Analyses: Function Alias Analysis Results, Create Garbage Collector Module Metadata, Insert stack protectors, Target Library Information, Assumption Cache Tracker, Branch Probability Analysis, Profile summary info, Assignment Tracking Analysis, Lazy Branch Probability Analysis, Natural Loop Information, Lazy Block Frequency Analysis, Machine Module Information
+[2025-06-18 00:56:24.174054000] 0x14972a840 Made Modification 'AArch64 Instruction Selection' on Function 'main'...
+0x14972ac20 Preserved Analyses: Create Garbage Collector Module Metadata, Assignment Tracking Analysis, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Post-Dominator Tree Construction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'AArch64 Instruction Selection' is not preserving 'Function Pass Manager'
+ -*- 'AArch64 Instruction Selection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.174377000] 0x14972a840 Freeing Pass 'Insert stack protectors' on Function 'main'...
+[2025-06-18 00:56:24.174422000] 0x14972a840 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.174464000] 0x14972a840 Freeing Pass 'AArch64 Instruction Selection' on Function 'main'...
+[2025-06-18 00:56:24.174506000] 0x14972a840 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:56:24.174547000] 0x14972a840 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.174589000] 0x14972a840 Freeing Pass 'Assignment Tracking Analysis' on Function 'main'...
+[2025-06-18 00:56:24.174630000] 0x14972a840 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:56:24.174671000] 0x14972a840 Freeing Pass 'Natural Loop Information' on Function 'main'...
+Running pass: Finalize ISel and expand pseudo-instructions
+[2025-06-18 00:56:24.174778000] 0x14972a840 Executing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+0x15963a2a0 Required Analyses: Machine Module Information
+0x15963a2a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Finalize ISel and expand pseudo-instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.176076000] 0x14972a840 Freeing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+Running pass: SME Peephole Optimization pass
+[2025-06-18 00:56:24.176131000] 0x14972a840 Executing Pass 'SME Peephole Optimization pass' on Function 'main'...
+0x15963a2e0 Required Analyses: Machine Module Information
+0x15963a2e0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'SME Peephole Optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.176621000] 0x14972a840 Freeing Pass 'SME Peephole Optimization pass' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.176675000] 0x14972a840 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15963a440 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15963a440 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early Tail Duplication
+[2025-06-18 00:56:24.176886000] 0x14972a840 Executing Pass 'Early Tail Duplication' on Function 'main'...
+0x15963a350 Required Analyses: Machine Branch Probability Analysis, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x15963a350 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early Tail Duplication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.177127000] 0x14972a840 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.177435000] 0x14972a840 Freeing Pass 'Early Tail Duplication' on Function 'main'...
+Running pass: Optimize machine instruction PHIs
+[2025-06-18 00:56:24.177490000] 0x14972a840 Executing Pass 'Optimize machine instruction PHIs' on Function 'main'...
+0x15963a4e0 Required Analyses: Machine Module Information
+0x15963a4e0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Optimize machine instruction PHIs' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.177977000] 0x14972a840 Freeing Pass 'Optimize machine instruction PHIs' on Function 'main'...
+Running pass: Slot index numbering
+[2025-06-18 00:56:24.178030000] 0x14972a840 Executing Pass 'Slot index numbering' on Function 'main'...
+0x14972bb80 Required Analyses: Machine Module Information
+0x14972bb80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Merge disjoint stack slots
+[2025-06-18 00:56:24.178234000] 0x14972a840 Executing Pass 'Merge disjoint stack slots' on Function 'main'...
+0x14972acf0 Required Analyses: Slot index numbering, Machine Module Information
+0x14972acf0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Merge disjoint stack slots' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.178453000] 0x14972a840 Freeing Pass 'Slot index numbering' on Function 'main'...
+[2025-06-18 00:56:24.178495000] 0x14972a840 Freeing Pass 'Merge disjoint stack slots' on Function 'main'...
+Running pass: Local Stack Slot Allocation
+[2025-06-18 00:56:24.178547000] 0x14972a840 Executing Pass 'Local Stack Slot Allocation' on Function 'main'...
+0x14972ba30 Required Analyses: Machine Module Information
+0x14972ba30 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Local Stack Slot Allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.179068000] 0x14972a840 Freeing Pass 'Local Stack Slot Allocation' on Function 'main'...
+Running pass: Remove dead machine instructions
+[2025-06-18 00:56:24.179120000] 0x14972a840 Executing Pass 'Remove dead machine instructions' on Function 'main'...
+0x14972ba70 Required Analyses: Machine Module Information
+0x14972ba70 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove dead machine instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.180076000] 0x14972a840 Freeing Pass 'Remove dead machine instructions' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:56:24.180129000] 0x14972a840 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x14972b800 Required Analyses: Machine Module Information
+0x14972b800 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Condition Optimizer
+[2025-06-18 00:56:24.180664000] 0x14972a840 Executing Pass 'AArch64 Condition Optimizer' on Function 'main'...
+0x14972bae0 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x14972bae0 Preserved Analyses: MachineDominator Tree Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Condition Optimizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.181809000] 0x14972a840 Freeing Pass 'AArch64 Condition Optimizer' on Function 'main'...
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:56:24.181867000] 0x14972a840 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x14972c300 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x14972c300 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Trace Metrics
+[2025-06-18 00:56:24.182118000] 0x14972a840 Executing Pass 'Machine Trace Metrics' on Function 'main'...
+0x14972c590 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x14972c590 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Conditional Compares
+[2025-06-18 00:56:24.182330000] 0x14972a840 Executing Pass 'AArch64 Conditional Compares' on Function 'main'...
+0x14972bf90 Required Analyses: Machine Branch Probability Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information
+0x14972bf90 Preserved Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Conditional Compares' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.182626000] 0x14972a840 Freeing Pass 'AArch64 Conditional Compares' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.182679000] 0x14972a840 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x14972c3f0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x14972c3f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine InstCombiner
+[2025-06-18 00:56:24.182912000] 0x14972a840 Executing Pass 'Machine InstCombiner' on Function 'main'...
+0x14972c760 Required Analyses: Machine Natural Loop Construction, Machine Trace Metrics, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x14972c760 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Trace Metrics, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine InstCombiner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.186300000] 0x14972a840 Freeing Pass 'Machine InstCombiner' on Function 'main'...
+[2025-06-18 00:56:24.186347000] 0x14972a840 Freeing Pass 'Machine Trace Metrics' on Function 'main'...
+[2025-06-18 00:56:24.186391000] 0x14972a840 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+Running pass: AArch64 Conditional Branch Tuning
+[2025-06-18 00:56:24.186444000] 0x14972a840 Executing Pass 'AArch64 Conditional Branch Tuning' on Function 'main'...
+0x14972c450 Required Analyses: Machine Module Information
+0x14972c450 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Conditional Branch Tuning' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.186921000] 0x14972a840 Freeing Pass 'AArch64 Conditional Branch Tuning' on Function 'main'...
+Running pass: Machine Trace Metrics
+[2025-06-18 00:56:24.186973000] 0x14972a840 Executing Pass 'Machine Trace Metrics' on Function 'main'...
+0x14972ca90 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x14972ca90 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early If-Conversion
+[2025-06-18 00:56:24.187186000] 0x14972a840 Executing Pass 'Early If-Conversion' on Function 'main'...
+0x14972c520 Required Analyses: Machine Branch Probability Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information
+0x14972c520 Preserved Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early If-Conversion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.187467000] 0x14972a840 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.187509000] 0x14972a840 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:56:24.187551000] 0x14972a840 Freeing Pass 'Early If-Conversion' on Function 'main'...
+Running pass: AArch64 Store Pair Suppression
+[2025-06-18 00:56:24.187624000] 0x14972a840 Executing Pass 'AArch64 Store Pair Suppression' on Function 'main'...
+0x14972d0b0 Required Analyses: Machine Trace Metrics, Machine Module Information
+0x14972d0b0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Trace Metrics, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Store Pair Suppression' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.188117000] 0x14972a840 Freeing Pass 'Machine Trace Metrics' on Function 'main'...
+[2025-06-18 00:56:24.188159000] 0x14972a840 Freeing Pass 'AArch64 Store Pair Suppression' on Function 'main'...
+Running pass: AArch64 SIMD instructions optimization pass
+[2025-06-18 00:56:24.188211000] 0x14972a840 Executing Pass 'AArch64 SIMD instructions optimization pass' on Function 'main'...
+0x14972d230 Required Analyses: Machine Module Information
+0x14972d230 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 SIMD instructions optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.190756000] 0x14972a840 Freeing Pass 'AArch64 SIMD instructions optimization pass' on Function 'main'...
+Running pass: AArch64 Stack Tagging PreRA
+[2025-06-18 00:56:24.190811000] 0x14972a840 Executing Pass 'AArch64 Stack Tagging PreRA' on Function 'main'...
+0x14972d750 Required Analyses: Machine Module Information
+0x14972d750 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Stack Tagging PreRA' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.191329000] 0x14972a840 Freeing Pass 'AArch64 Stack Tagging PreRA' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:56:24.191382000] 0x14972a840 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x14972cdd0 Required Analyses: Machine Module Information
+0x14972cdd0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:56:24.191597000] 0x14972a840 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x14972d850 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x14972d850 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:56:24.191819000] 0x14972a840 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x14972d920 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x14972d920 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early Machine Loop Invariant Code Motion
+[2025-06-18 00:56:24.192047000] 0x14972a840 Executing Pass 'Early Machine Loop Invariant Code Motion' on Function 'main'...
+0x14972d5c0 Required Analyses: Machine Natural Loop Construction, Machine Block Frequency Analysis, MachineDominator Tree Construction, Function Alias Analysis Results, Machine Module Information
+0x14972d5c0 Preserved Analyses: Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early Machine Loop Invariant Code Motion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.192692000] 0x14972a840 Freeing Pass 'Early Machine Loop Invariant Code Motion' on Function 'main'...
+[2025-06-18 00:56:24.192736000] 0x14972a840 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.192779000] 0x14972a840 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:56:24.192832000] 0x14972a840 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x14972daf0 Required Analyses: Machine Module Information
+0x14972daf0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:56:24.193033000] 0x14972a840 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x14972dc10 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x14972dc10 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Common Subexpression Elimination
+[2025-06-18 00:56:24.193292000] 0x14972a840 Executing Pass 'Machine Common Subexpression Elimination' on Function 'main'...
+0x14972da20 Required Analyses: Machine Module Information, MachineDominator Tree Construction, Machine Block Frequency Analysis
+0x14972da20 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Common Subexpression Elimination' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.195038000] 0x14972a840 Freeing Pass 'Machine Common Subexpression Elimination' on Function 'main'...
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:56:24.195092000] 0x14972a840 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x14972ddc0 Required Analyses: Machine Module Information
+0x14972ddc0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Cycle Info Analysis
+[2025-06-18 00:56:24.195591000] 0x14972a840 Executing Pass 'Machine Cycle Info Analysis' on Function 'main'...
+0x14972dc70 Required Analyses: Machine Module Information
+0x14972dc70 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine code sinking
+[2025-06-18 00:56:24.195792000] 0x14972a840 Executing Pass 'Machine code sinking' on Function 'main'...
+0x14972dbb0 Required Analyses: Machine Module Information, Function Alias Analysis Results, MachineDominator Tree Construction, MachinePostDominator Tree Construction, Machine Cycle Info Analysis, Machine Branch Probability Analysis, Profile summary info, Machine Block Frequency Analysis, Target Pass Configuration
+[2025-06-18 00:56:24.195957000] 0x14972a840 Made Modification 'Machine code sinking' on Function 'main'...
+0x14972dbb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Machine Cycle Info Analysis, Machine Natural Loop Construction
+ -- 'Machine code sinking' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine code sinking' is not preserving 'MachinePostDominator Tree Construction'
+ -*- 'Machine code sinking' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.196230000] 0x14972a840 Freeing Pass 'Machine code sinking' on Function 'main'...
+[2025-06-18 00:56:24.196272000] 0x14972a840 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.196314000] 0x14972a840 Freeing Pass 'Machine Cycle Info Analysis' on Function 'main'...
+[2025-06-18 00:56:24.196356000] 0x14972a840 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.196397000] 0x14972a840 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+Running pass: Peephole Optimizations
+[2025-06-18 00:56:24.196463000] 0x14972a840 Executing Pass 'Peephole Optimizations' on Function 'main'...
+0x14972dd00 Required Analyses: Machine Module Information, Machine Natural Loop Construction
+0x14972dd00 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Peephole Optimizations' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.197088000] 0x14972a840 Freeing Pass 'Peephole Optimizations' on Function 'main'...
+Running pass: Remove dead machine instructions
+[2025-06-18 00:56:24.197141000] 0x14972a840 Executing Pass 'Remove dead machine instructions' on Function 'main'...
+0x14972dea0 Required Analyses: Machine Module Information
+0x14972dea0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove dead machine instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.197645000] 0x14972a840 Freeing Pass 'Remove dead machine instructions' on Function 'main'...
+Running pass: AArch64 MI Peephole Optimization pass
+[2025-06-18 00:56:24.197698000] 0x14972a840 Executing Pass 'AArch64 MI Peephole Optimization pass' on Function 'main'...
+0x14972e6a0 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x14972e6a0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 MI Peephole Optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.198179000] 0x14972a840 Freeing Pass 'AArch64 MI Peephole Optimization pass' on Function 'main'...
+Running pass: AArch64 Dead register definitions
+[2025-06-18 00:56:24.198231000] 0x14972a840 Executing Pass 'AArch64 Dead register definitions' on Function 'main'...
+0x14972e720 Required Analyses: Machine Module Information
+0x14972e720 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Dead register definitions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.198697000] 0x14972a840 Freeing Pass 'AArch64 Dead register definitions' on Function 'main'...
+Running pass: Detect Dead Lanes
+[2025-06-18 00:56:24.198757000] 0x14972a840 Executing Pass 'Detect Dead Lanes' on Function 'main'...
+0x14972bd70 Required Analyses: Machine Module Information
+0x14972bd70 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Detect Dead Lanes' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.199270000] 0x14972a840 Freeing Pass 'Detect Dead Lanes' on Function 'main'...
+Running pass: Init Undef Pass
+[2025-06-18 00:56:24.199323000] 0x14972a840 Executing Pass 'Init Undef Pass' on Function 'main'...
+0x14972bdd0 Required Analyses: Machine Module Information
+0x14972bdd0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Init Undef Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.199803000] 0x14972a840 Freeing Pass 'Init Undef Pass' on Function 'main'...
+Running pass: Process Implicit Definitions
+[2025-06-18 00:56:24.199856000] 0x14972a840 Executing Pass 'Process Implicit Definitions' on Function 'main'...
+0x14972e270 Required Analyses: Machine Module Information
+0x14972e270 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Function Alias Analysis Results, Machine Module Information, Uninitialized Pass, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Process Implicit Definitions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.200575000] 0x14972a840 Freeing Pass 'Process Implicit Definitions' on Function 'main'...
+Running pass: Remove unreachable machine basic blocks
+[2025-06-18 00:56:24.200637000] 0x14972a840 Executing Pass 'Remove unreachable machine basic blocks' on Function 'main'...
+0x14972bec0 Required Analyses: Machine Module Information
+0x14972bec0 Preserved Analyses: Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Variable Analysis
+[2025-06-18 00:56:24.200884000] 0x14972a840 Executing Pass 'Live Variable Analysis' on Function 'main'...
+0x14972e7f0 Required Analyses: Remove unreachable machine basic blocks, Machine Module Information
+0x14972e7f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Eliminate PHI nodes for register allocation
+[2025-06-18 00:56:24.201122000] 0x14972a840 Executing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+0x14972e500 Required Analyses: Machine Module Information
+0x14972e500 Preserved Analyses: Live Variable Analysis, Slot index numbering, Live Interval Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x14972e500 Used Analyses: Live Variable Analysis
+ -*- 'Eliminate PHI nodes for register allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.201426000] 0x14972a840 Freeing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+[2025-06-18 00:56:24.201473000] 0x14972a840 Freeing Pass 'Remove unreachable machine basic blocks' on Function 'main'...
+Running pass: Two-Address instruction pass
+[2025-06-18 00:56:24.201528000] 0x14972a840 Executing Pass 'Two-Address instruction pass' on Function 'main'...
+0x14972e8f0 Required Analyses: Machine Module Information
+0x14972e8f0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Live Variable Analysis, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x14972e8f0 Used Analyses: Function Alias Analysis Results, Live Variable Analysis
+ -*- 'Two-Address instruction pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.202148000] 0x14972a840 Freeing Pass 'Two-Address instruction pass' on Function 'main'...
+[2025-06-18 00:56:24.202194000] 0x14972a840 Freeing Pass 'Live Variable Analysis' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:56:24.202252000] 0x14972a840 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x149608430 Required Analyses: Machine Module Information
+0x149608430 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Slot index numbering
+[2025-06-18 00:56:24.202467000] 0x14972a840 Executing Pass 'Slot index numbering' on Function 'main'...
+0x1496080e0 Required Analyses: Machine Module Information
+0x1496080e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Interval Analysis
+[2025-06-18 00:56:24.202683000] 0x14972a840 Executing Pass 'Live Interval Analysis' on Function 'main'...
+0x149607d90 Required Analyses: MachineDominator Tree Construction, Slot index numbering, Machine Module Information
+0x149607d90 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Live Variable Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Register Coalescer
+[2025-06-18 00:56:24.203262000] 0x14972a840 Executing Pass 'Register Coalescer' on Function 'main'...
+0x149607c10 Required Analyses: Live Interval Analysis, Machine Natural Loop Construction, Machine Module Information
+[2025-06-18 00:56:24.204032000] 0x14972a840 Made Modification 'Register Coalescer' on Function 'main'...
+0x149607c10 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Live Interval Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x149607c10 Used Analyses: Slot index numbering
+ -*- 'Register Coalescer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.204614000] 0x14972a840 Freeing Pass 'Register Coalescer' on Function 'main'...
+Running pass: Rename Disconnected Subregister Components
+[2025-06-18 00:56:24.204670000] 0x14972a840 Executing Pass 'Rename Disconnected Subregister Components' on Function 'main'...
+0x149607980 Required Analyses: Live Interval Analysis, Slot index numbering, Machine Module Information
+0x149607980 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Live Interval Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Rename Disconnected Subregister Components' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.205215000] 0x14972a840 Freeing Pass 'Rename Disconnected Subregister Components' on Function 'main'...
+Running pass: Machine Instruction Scheduler
+[2025-06-18 00:56:24.205271000] 0x14972a840 Executing Pass 'Machine Instruction Scheduler' on Function 'main'...
+0x149607a00 Required Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Function Alias Analysis Results, Target Pass Configuration, Slot index numbering, Live Interval Analysis, Machine Module Information
+[2025-06-18 00:56:24.206446000] 0x14972a840 Made Modification 'Machine Instruction Scheduler' on Function 'main'...
+0x149607a00 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Instruction Scheduler' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.206990000] 0x14972a840 Freeing Pass 'Machine Instruction Scheduler' on Function 'main'...
+Running pass: AArch64 Post Coalescer pass
+[2025-06-18 00:56:24.207048000] 0x14972a840 Executing Pass 'AArch64 Post Coalescer pass' on Function 'main'...
+0x149608660 Required Analyses: Live Interval Analysis, Machine Module Information
+0x149608660 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Post Coalescer pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.207278000] 0x14972a840 Freeing Pass 'AArch64 Post Coalescer pass' on Function 'main'...
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:56:24.207334000] 0x14972a840 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x149608770 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x149608770 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Debug Variable Analysis
+[2025-06-18 00:56:24.207581000] 0x14972a840 Executing Pass 'Debug Variable Analysis' on Function 'main'...
+0x14972e930 Required Analyses: MachineDominator Tree Construction, Live Interval Analysis, Machine Module Information
+0x14972e930 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Stack Slot Analysis
+[2025-06-18 00:56:24.209644000] 0x14972a840 Executing Pass 'Live Stack Slot Analysis' on Function 'main'...
+0x14972eac0 Required Analyses: Slot index numbering, Machine Module Information
+0x14972eac0 Preserved Analyses: Slot index numbering, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Virtual Register Map
+[2025-06-18 00:56:24.210722000] 0x14972a840 Executing Pass 'Virtual Register Map' on Function 'main'...
+0x14972ce90 Required Analyses: Machine Module Information
+0x14972ce90 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Register Matrix
+[2025-06-18 00:56:24.210963000] 0x14972a840 Executing Pass 'Live Register Matrix' on Function 'main'...
+0x14972cfb0 Required Analyses: Live Interval Analysis, Virtual Register Map, Machine Module Information
+0x14972cfb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Bundle Machine CFG Edges
+[2025-06-18 00:56:24.211812000] 0x14972a840 Executing Pass 'Bundle Machine CFG Edges' on Function 'main'...
+0x14972e450 Required Analyses: Machine Module Information
+0x14972e450 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Spill Code Placement Analysis
+[2025-06-18 00:56:24.212016000] 0x14972a840 Executing Pass 'Spill Code Placement Analysis' on Function 'main'...
+0x14972ee30 Required Analyses: Machine Block Frequency Analysis, Bundle Machine CFG Edges, Machine Module Information
+0x14972ee30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.212237000] 0x14972a840 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x14972ef90 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x14972ef90 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:56:24.212449000] 0x14972a840 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x14972ed80 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x14972ed80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Greedy Register Allocator
+[2025-06-18 00:56:24.212660000] 0x14972a840 Executing Pass 'Greedy Register Allocator' on Function 'main'...
+0x1496086b0 Required Analyses: Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Virtual Register Map, Live Register Matrix, Bundle Machine CFG Edges, Spill Code Placement Analysis, Machine Optimization Remark Emitter, Regalloc eviction policy, Regalloc priority policy, Machine Module Information
+0x1496086b0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, Virtual Register Map, Live Register Matrix, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Greedy Register Allocator' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.213397000] 0x14972a840 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.213440000] 0x14972a840 Freeing Pass 'Spill Code Placement Analysis' on Function 'main'...
+[2025-06-18 00:56:24.213482000] 0x14972a840 Freeing Pass 'Greedy Register Allocator' on Function 'main'...
+[2025-06-18 00:56:24.213525000] 0x14972a840 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.213567000] 0x14972a840 Freeing Pass 'Bundle Machine CFG Edges' on Function 'main'...
+Running pass: Virtual Register Rewriter
+[2025-06-18 00:56:24.213619000] 0x14972a840 Executing Pass 'Virtual Register Rewriter' on Function 'main'...
+0x14972eff0 Required Analyses: Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, Virtual Register Map, Live Register Matrix, Machine Module Information
+[2025-06-18 00:56:24.214168000] 0x14972a840 Made Modification 'Virtual Register Rewriter' on Function 'main'...
+0x14972eff0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Live Interval Analysis, Slot index numbering, Live Stack Slot Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'Virtual Register Rewriter' is not preserving 'Live Register Matrix'
+ -- 'Virtual Register Rewriter' is not preserving 'Debug Variable Analysis'
+ -- 'Virtual Register Rewriter' is not preserving 'Virtual Register Map'
+ -*- 'Virtual Register Rewriter' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.214699000] 0x14972a840 Freeing Pass 'Debug Variable Analysis' on Function 'main'...
+[2025-06-18 00:56:24.214761000] 0x14972a840 Freeing Pass 'Live Register Matrix' on Function 'main'...
+[2025-06-18 00:56:24.214806000] 0x14972a840 Freeing Pass 'Live Interval Analysis' on Function 'main'...
+[2025-06-18 00:56:24.214850000] 0x14972a840 Freeing Pass 'Virtual Register Map' on Function 'main'...
+[2025-06-18 00:56:24.214892000] 0x14972a840 Freeing Pass 'Virtual Register Rewriter' on Function 'main'...
+Running pass: Register Allocation Pass Scoring
+[2025-06-18 00:56:24.214945000] 0x14972a840 Executing Pass 'Register Allocation Pass Scoring' on Function 'main'...
+0x14972f8a0 Required Analyses: Regalloc eviction policy, Regalloc priority policy, Machine Block Frequency Analysis, Machine Module Information
+0x14972f8a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Register Allocation Pass Scoring' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.215182000] 0x14972a840 Freeing Pass 'Register Allocation Pass Scoring' on Function 'main'...
+Running pass: Stack Slot Coloring
+[2025-06-18 00:56:24.215234000] 0x14972a840 Executing Pass 'Stack Slot Coloring' on Function 'main'...
+0x14972f2d0 Required Analyses: Slot index numbering, Live Stack Slot Analysis, Machine Block Frequency Analysis, Machine Module Information
+0x14972f2d0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Slot index numbering, Live Interval Analysis, Debug Variable Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Slot Coloring' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.215770000] 0x14972a840 Freeing Pass 'Live Stack Slot Analysis' on Function 'main'...
+[2025-06-18 00:56:24.215814000] 0x14972a840 Freeing Pass 'Slot index numbering' on Function 'main'...
+[2025-06-18 00:56:24.215856000] 0x14972a840 Freeing Pass 'Stack Slot Coloring' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:56:24.215907000] 0x14972a840 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x14972f330 Required Analyses: Machine Module Information
+0x14972f330 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.216413000] 0x14972a840 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Machine Loop Invariant Code Motion
+[2025-06-18 00:56:24.216467000] 0x14972a840 Executing Pass 'Machine Loop Invariant Code Motion' on Function 'main'...
+0x14972f390 Required Analyses: Machine Natural Loop Construction, Machine Block Frequency Analysis, MachineDominator Tree Construction, Function Alias Analysis Results, Machine Module Information
+0x14972f390 Preserved Analyses: Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Loop Invariant Code Motion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.216729000] 0x14972a840 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:56:24.216772000] 0x14972a840 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.216815000] 0x14972a840 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.216859000] 0x14972a840 Freeing Pass 'Machine Loop Invariant Code Motion' on Function 'main'...
+Running pass: AArch64 Redundant Copy Elimination
+[2025-06-18 00:56:24.216912000] 0x14972a840 Executing Pass 'AArch64 Redundant Copy Elimination' on Function 'main'...
+0x14972fc00 Required Analyses: Machine Module Information
+0x14972fc00 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Redundant Copy Elimination' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.217117000] 0x14972a840 Freeing Pass 'AArch64 Redundant Copy Elimination' on Function 'main'...
+Running pass: A57 FP Anti-dependency breaker
+[2025-06-18 00:56:24.217170000] 0x14972a840 Executing Pass 'A57 FP Anti-dependency breaker' on Function 'main'...
+0x14972f4a0 Required Analyses: Machine Module Information
+0x14972f4a0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'A57 FP Anti-dependency breaker' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.217685000] 0x14972a840 Freeing Pass 'A57 FP Anti-dependency breaker' on Function 'main'...
+Running pass: Remove Redundant DEBUG_VALUE analysis
+[2025-06-18 00:56:24.217738000] 0x14972a840 Executing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+0x14972fd90 Required Analyses: Machine Module Information
+0x14972fd90 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Redundant DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.218217000] 0x14972a840 Freeing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Fixup Statepoint Caller Saved
+[2025-06-18 00:56:24.218269000] 0x14972a840 Executing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+0x14972f3f0 Required Analyses: Machine Module Information
+0x14972f3f0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Fixup Statepoint Caller Saved' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.218740000] 0x14972a840 Freeing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+Running pass: PostRA Machine Sink
+[2025-06-18 00:56:24.218814000] 0x14972a840 Executing Pass 'PostRA Machine Sink' on Function 'main'...
+0x159639fd0 Required Analyses: Machine Module Information
+0x159639fd0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'PostRA Machine Sink' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.219288000] 0x14972a840 Freeing Pass 'PostRA Machine Sink' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:56:24.219340000] 0x14972a840 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x15963a910 Required Analyses: Machine Module Information
+0x15963a910 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:56:24.219542000] 0x14972a840 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x15963a6c0 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x15963a6c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:56:24.219753000] 0x14972a840 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x15963a680 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x15963a680 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:56:24.219975000] 0x14972a840 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x15963a9d0 Required Analyses: Machine Module Information
+0x15963a9d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.220204000] 0x14972a840 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15963aaf0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15963aaf0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:56:24.220414000] 0x14972a840 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x15963aab0 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x15963aab0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Shrink Wrapping analysis
+[2025-06-18 00:56:24.220624000] 0x14972a840 Executing Pass 'Shrink Wrapping analysis' on Function 'main'...
+0x15963a180 Required Analyses: Machine Block Frequency Analysis, MachineDominator Tree Construction, MachinePostDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Module Information
+0x15963a180 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Shrink Wrapping analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.221272000] 0x14972a840 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.221314000] 0x14972a840 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.221357000] 0x14972a840 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.221399000] 0x14972a840 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:56:24.221441000] 0x14972a840 Freeing Pass 'Shrink Wrapping analysis' on Function 'main'...
+Running pass: Prologue/Epilogue Insertion & Frame Finalization
+[2025-06-18 00:56:24.221493000] 0x14972a840 Executing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x15963a1c0 Required Analyses: Machine Optimization Remark Emitter, Machine Module Information
+[2025-06-18 00:56:24.222757000] 0x14972a840 Made Modification 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x15963a1c0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Prologue/Epilogue Insertion & Frame Finalization' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.223221000] 0x14972a840 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.223261000] 0x14972a840 Freeing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+Running pass: Machine Late Instructions Cleanup Pass
+[2025-06-18 00:56:24.223311000] 0x14972a840 Executing Pass 'Machine Late Instructions Cleanup Pass' on Function 'main'...
+0x15963abf0 Required Analyses: Machine Module Information
+0x15963abf0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Late Instructions Cleanup Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.223772000] 0x14972a840 Freeing Pass 'Machine Late Instructions Cleanup Pass' on Function 'main'...
+Running pass: Control Flow Optimizer
+[2025-06-18 00:56:24.223823000] 0x14972a840 Executing Pass 'Control Flow Optimizer' on Function 'main'...
+0x15963b210 Required Analyses: Machine Block Frequency Analysis, Machine Branch Probability Analysis, Profile summary info, Target Pass Configuration, Machine Module Information
+0x15963b210 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Control Flow Optimizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.224063000] 0x14972a840 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.224104000] 0x14972a840 Freeing Pass 'Control Flow Optimizer' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.224154000] 0x14972a840 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15963b340 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15963b340 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Tail Duplication
+[2025-06-18 00:56:24.224358000] 0x14972a840 Executing Pass 'Tail Duplication' on Function 'main'...
+0x15963b250 Required Analyses: Machine Branch Probability Analysis, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x15963b250 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Tail Duplication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.224603000] 0x14972a840 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.224643000] 0x14972a840 Freeing Pass 'Tail Duplication' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:56:24.224694000] 0x14972a840 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x15963ac90 Required Analyses: Machine Module Information
+0x15963ac90 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.225169000] 0x14972a840 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Post-RA pseudo instruction expansion pass
+[2025-06-18 00:56:24.225221000] 0x14972a840 Executing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+0x15963b3a0 Required Analyses: Machine Module Information
+0x15963b3a0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Post-RA pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.225881000] 0x14972a840 Freeing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 pseudo instruction expansion pass
+[2025-06-18 00:56:24.225935000] 0x14972a840 Executing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x15963b430 Required Analyses: Machine Module Information
+[2025-06-18 00:56:24.226888000] 0x14972a840 Made Modification 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x15963b430 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.227064000] 0x14972a840 Freeing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 load / store optimization pass
+[2025-06-18 00:56:24.227115000] 0x14972a840 Executing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+0x15963b4a0 Required Analyses: Function Alias Analysis Results, Machine Module Information
+0x15963b4a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 load / store optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.228148000] 0x14972a840 Freeing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+Running pass: Insert KCFI indirect call checks
+[2025-06-18 00:56:24.228199000] 0x14972a840 Executing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+0x15963b6e0 Required Analyses: Machine Module Information
+0x15963b6e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert KCFI indirect call checks' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.228396000] 0x14972a840 Freeing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+Running pass: AArch64 speculation hardening pass
+[2025-06-18 00:56:24.228447000] 0x14972a840 Executing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+0x15963acf0 Required Analyses: Machine Module Information
+0x15963acf0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 speculation hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.228643000] 0x14972a840 Freeing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:56:24.228693000] 0x14972a840 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x15963afb0 Required Analyses: Machine Module Information
+0x15963afb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:56:24.228930000] 0x14972a840 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x15963ae80 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x15963ae80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Falkor HW Prefetch Fix Late Phase
+[2025-06-18 00:56:24.229160000] 0x14972a840 Executing Pass 'Falkor HW Prefetch Fix Late Phase' on Function 'main'...
+0x15963ade0 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x15963ade0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Falkor HW Prefetch Fix Late Phase' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.229640000] 0x14972a840 Freeing Pass 'Falkor HW Prefetch Fix Late Phase' on Function 'main'...
+Running pass: PostRA Machine Instruction Scheduler
+[2025-06-18 00:56:24.229692000] 0x14972a840 Executing Pass 'PostRA Machine Instruction Scheduler' on Function 'main'...
+0x15963b730 Required Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Function Alias Analysis Results, Target Pass Configuration, Machine Module Information
+0x15963b730 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'PostRA Machine Instruction Scheduler' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.230418000] 0x14972a840 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.230461000] 0x14972a840 Freeing Pass 'PostRA Machine Instruction Scheduler' on Function 'main'...
+[2025-06-18 00:56:24.230502000] 0x14972a840 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:56:24.230542000] 0x14972a840 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:56:24.230583000] 0x14972a840 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Analyze Machine Code For Garbage Collection
+[2025-06-18 00:56:24.230635000] 0x14972a840 Executing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+0x15963af50 Required Analyses: Machine Module Information, Create Garbage Collector Module Metadata
+0x15963af50 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Analyze Machine Code For Garbage Collection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.230844000] 0x14972a840 Freeing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:56:24.230895000] 0x14972a840 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x15963ba60 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x15963ba60 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:56:24.231115000] 0x14972a840 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x15963be90 Required Analyses: Machine Module Information
+0x15963be90 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Branch Probability Basic Block Placement
+[2025-06-18 00:56:24.231313000] 0x14972a840 Executing Pass 'Branch Probability Basic Block Placement' on Function 'main'...
+0x15963b900 Required Analyses: Machine Branch Probability Analysis, Machine Block Frequency Analysis, MachinePostDominator Tree Construction, Machine Natural Loop Construction, Profile summary info, Target Pass Configuration, Machine Module Information
+0x15963b900 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch Probability Basic Block Placement' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.231574000] 0x14972a840 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.231615000] 0x14972a840 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:56:24.231656000] 0x14972a840 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:56:24.231730000] 0x14972a840 Freeing Pass 'Branch Probability Basic Block Placement' on Function 'main'...
+Running pass: Insert fentry calls
+[2025-06-18 00:56:24.231782000] 0x14972a840 Executing Pass 'Insert fentry calls' on Function 'main'...
+0x15963bf70 Required Analyses: Machine Module Information
+0x15963bf70 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert fentry calls' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.231983000] 0x14972a840 Freeing Pass 'Insert fentry calls' on Function 'main'...
+Running pass: Insert XRay ops
+[2025-06-18 00:56:24.232035000] 0x14972a840 Executing Pass 'Insert XRay ops' on Function 'main'...
+0x15963bfb0 Required Analyses: Machine Module Information
+0x15963bfb0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert XRay ops' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.232502000] 0x14972a840 Freeing Pass 'Insert XRay ops' on Function 'main'...
+Running pass: Implement the 'patchable-function' attribute
+[2025-06-18 00:56:24.232553000] 0x14972a840 Executing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+0x15963bb10 Required Analyses: Machine Module Information
+0x15963bb10 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Implement the 'patchable-function' attribute' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.232758000] 0x14972a840 Freeing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+Running pass: Workaround A53 erratum 835769 pass
+[2025-06-18 00:56:24.232810000] 0x14972a840 Executing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+0x15963bb80 Required Analyses: Machine Module Information
+0x15963bb80 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Workaround A53 erratum 835769 pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.233305000] 0x14972a840 Freeing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+Running pass: AArch64 Collect Linker Optimization Hint (LOH)
+[2025-06-18 00:56:24.233356000] 0x14972a840 Executing Pass 'AArch64 Collect Linker Optimization Hint (LOH)' on Function 'main'...
+0x15963bbf0 Required Analyses: Machine Module Information
+0x15963bbf0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Collect Linker Optimization Hint (LOH)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.233565000] 0x14972a840 Freeing Pass 'AArch64 Collect Linker Optimization Hint (LOH)' on Function 'main'...
+Running pass: Contiguously Lay Out Funclets
+[2025-06-18 00:56:24.233617000] 0x14972a840 Executing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+0x15963bc30 Required Analyses: Machine Module Information
+0x15963bc30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Contiguously Lay Out Funclets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.233816000] 0x14972a840 Freeing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+Running pass: Remove Loads Into Fake Uses
+[2025-06-18 00:56:24.233867000] 0x14972a840 Executing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+0x15963bcc0 Required Analyses: Machine Module Information
+0x15963bcc0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Loads Into Fake Uses' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.234357000] 0x14972a840 Freeing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+Running pass: StackMap Liveness Analysis
+[2025-06-18 00:56:24.234409000] 0x14972a840 Executing Pass 'StackMap Liveness Analysis' on Function 'main'...
+0x15963bff0 Required Analyses: Machine Module Information
+0x15963bff0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'StackMap Liveness Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.234883000] 0x14972a840 Freeing Pass 'StackMap Liveness Analysis' on Function 'main'...
+Running pass: Live DEBUG_VALUE analysis
+[2025-06-18 00:56:24.234935000] 0x14972a840 Executing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+0x15963c530 Required Analyses: Target Pass Configuration, Machine Module Information
+0x15963c530 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Live DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.236250000] 0x14972a840 Freeing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Machine Sanitizer Binary Metadata
+[2025-06-18 00:56:24.236302000] 0x14972a840 Executing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+0x15963c570 Required Analyses: Machine Module Information
+0x15963c570 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Sanitizer Binary Metadata' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.236525000] 0x14972a840 Freeing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+[2025-06-18 00:56:24.236567000] 0x1497153f0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.236623000] 0x1497153f0 Freeing Pass 'Target Library Information' on Module 'test.c'...
+[2025-06-18 00:56:24.236665000] 0x1497153f0 Freeing Pass 'Type-Based Alias Analysis' on Module 'test.c'...
+[2025-06-18 00:56:24.236706000] 0x1497153f0 Freeing Pass 'Target Pass Configuration' on Module 'test.c'...
+[2025-06-18 00:56:24.236747000] 0x1497153f0 Freeing Pass 'Profile summary info' on Module 'test.c'...
+[2025-06-18 00:56:24.236788000] 0x1497153f0 Freeing Pass 'Assumption Cache Tracker' on Module 'test.c'...
+[2025-06-18 00:56:24.236831000] 0x1497153f0 Freeing Pass 'Scoped NoAlias Alias Analysis' on Module 'test.c'...
+[2025-06-18 00:56:24.236872000] 0x1497153f0 Freeing Pass 'Default Regalloc Priority Advisor' on Module 'test.c'...
+[2025-06-18 00:56:24.236913000] 0x1497153f0 Freeing Pass 'Default Regalloc Eviction Advisor' on Module 'test.c'...
+Running pass: Machine Outliner
+[2025-06-18 00:56:24.236964000] 0x1497153f0 Executing Pass 'Machine Outliner' on Module 'test.c'...
+0x15963c5e0 Required Analyses: Machine Module Information
+0x15963c5e0 Preserved Analyses: Machine Module Information
+0x15963c5e0 Used Analyses: Module summary info
+ -*- 'Machine Outliner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.238330000] 0x1497153f0 Freeing Pass 'Machine Outliner' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:56:24.238381000] 0x1497153f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: AArch64 sls hardening pass
+[2025-06-18 00:56:24.238433000] 0x15963c120 Executing Pass 'AArch64 sls hardening pass' on Function 'main'...
+0x15963c760 Required Analyses: Machine Module Information
+0x15963c760 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 sls hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.238633000] 0x15963c120 Freeing Pass 'AArch64 sls hardening pass' on Function 'main'...
+Running pass: AArch64 Pointer Authentication
+[2025-06-18 00:56:24.238684000] 0x15963c120 Executing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+0x15963c0a0 Required Analyses: Machine Module Information
+0x15963c0a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Pointer Authentication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.238882000] 0x15963c120 Freeing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+Running pass: AArch64 Branch Targets
+[2025-06-18 00:56:24.238935000] 0x15963c120 Executing Pass 'AArch64 Branch Targets' on Function 'main'...
+0x15963c2e0 Required Analyses: Machine Module Information
+0x15963c2e0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Optimization Remark Emitter, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Detect single entry single exit regions, Function register usage analysis, Analysis if a function is memory bound, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, SPIRV module analysis, WebAssembly Exception Information, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Cycle Info Analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Machine Block Frequency Analysis, Post-Dominator Tree Construction, Uniformity Analysis, SPIRV convergence regions analysis, Bundle Machine CFG Edges, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Branch Targets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.239420000] 0x15963c120 Freeing Pass 'AArch64 Branch Targets' on Function 'main'...
+Running pass: Branch relaxation pass
+[2025-06-18 00:56:24.239471000] 0x15963c120 Executing Pass 'Branch relaxation pass' on Function 'main'...
+0x15963c320 Required Analyses: Machine Module Information
+0x15963c320 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch relaxation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.239671000] 0x15963c120 Freeing Pass 'Branch relaxation pass' on Function 'main'...
+Running pass: AArch64 Compress Jump Tables
+[2025-06-18 00:56:24.239722000] 0x15963c120 Executing Pass 'AArch64 Compress Jump Tables' on Function 'main'...
+0x15963c8d0 Required Analyses: Machine Module Information
+0x15963c8d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Compress Jump Tables' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.239923000] 0x15963c120 Freeing Pass 'AArch64 Compress Jump Tables' on Function 'main'...
+Running pass: Insert CFI remember/restore state instructions
+[2025-06-18 00:56:24.239974000] 0x15963c120 Executing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+0x15963c380 Required Analyses: Machine Module Information
+0x15963c380 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert CFI remember/restore state instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.240195000] 0x15963c120 Freeing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.240247000] 0x15963c120 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15963ca30 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15963ca30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:56:24.240469000] 0x15963c120 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x15963c9f0 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x15963c9f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Stack Frame Layout Analysis
+[2025-06-18 00:56:24.240674000] 0x15963c120 Executing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+0x15963c950 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter
+0x15963c950 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Frame Layout Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.240885000] 0x15963c120 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.240926000] 0x15963c120 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.240967000] 0x15963c120 Freeing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+Running pass: Unpack machine instruction bundles
+[2025-06-18 00:56:24.241020000] 0x15963c120 Executing Pass 'Unpack machine instruction bundles' on Function 'main'...
+0x15963c990 Required Analyses: Machine Module Information
+0x15963c990 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Unpack machine instruction bundles' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.241219000] 0x15963c120 Freeing Pass 'Unpack machine instruction bundles' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:56:24.241271000] 0x15963c120 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15963cde0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15963cde0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:56:24.241479000] 0x15963c120 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x15963cea0 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x15963cea0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Assembly Printer
+[2025-06-18 00:56:24.241685000] 0x15963c120 Executing Pass 'AArch64 Assembly Printer' on Function 'main'...
+0x15963cf10 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter, Create Garbage Collector Module Metadata, Lazy Machine Block Frequency Analysis, Machine Branch Probability Analysis
+0x15963cf10 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Assembly Printer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.244953000] 0x15963c120 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:56:24.244995000] 0x15963c120 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:56:24.245037000] 0x15963c120 Freeing Pass 'AArch64 Assembly Printer' on Function 'main'...
+Running pass: Free MachineFunction
+[2025-06-18 00:56:24.245104000] 0x15963c120 Executing Pass 'Free MachineFunction' on Function 'main'...
+0x15963d480 Required Analyses: Machine Module Information
+[2025-06-18 00:56:24.245176000] 0x15963c120 Made Modification 'Free MachineFunction' on Function 'main'...
+0x15963d480 Preserved Analyses: Machine Module Information
+ -- 'Free MachineFunction' is not preserving 'Function Pass Manager'
+ -*- 'Free MachineFunction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.245305000] 0x15963c120 Freeing Pass 'Free MachineFunction' on Function 'main'...
+[2025-06-18 00:56:24.245349000] 0x1497153f0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:56:24.245406000] 0x1497153f0 Freeing Pass 'Create Garbage Collector Module Metadata' on Module 'test.c'...
+[2025-06-18 00:56:24.245448000] 0x1497153f0 Freeing Pass 'Machine Branch Probability Analysis' on Module 'test.c'...
+[2025-06-18 00:56:24.245493000] 0x1497153f0 Freeing Pass 'Machine Module Information' on Module 'test.c'...
diff --git a/optimization_2_new.txt b/optimization_2_new.txt
new file mode 100644
index 0000000000000..3cf43cdde5f75
--- /dev/null
+++ b/optimization_2_new.txt
@@ -0,0 +1,1792 @@
+ -- 'Expand large div/rem' is not preserving 'Function Pass Manager'
+ -- 'Expand large div/rem' is not preserving 'Pre-ISel Intrinsic Lowering'
+ -- 'Expand fp' is not preserving 'Expand large div/rem'
+ -- 'Expand Atomic instructions' is not preserving 'Expand fp'
+ -- 'Simplify the CFG' is not preserving 'Function Pass Manager'
+ -- 'Simplify the CFG' is not preserving 'SVE intrinsics optimizations'
+ -- 'Canonicalize natural loops' is not preserving 'Simplify the CFG'
+ -- 'Loop Data Prefetch' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Loop Data Prefetch' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Loop Data Prefetch' is not preserving 'Optimization Remark Emitter'
+ -- 'Falkor HW Prefetch Fix' is not preserving 'Canonicalize natural loops'
+ -- 'Falkor HW Prefetch Fix' is not preserving 'Loop Data Prefetch'
+ -- 'Canonicalize natural loops' is not preserving 'Falkor HW Prefetch Fix'
+ -- 'Canonicalize Freeze Instructions in Loops' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Canonicalize Freeze Instructions in Loops' is not preserving 'Loop Pass Manager'
+ -- 'Loop Strength Reduction' is not preserving 'Canonicalize Freeze Instructions in Loops'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Canonicalize natural loops'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Function Alias Analysis Results'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Natural Loop Information'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Scalar Evolution Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Merge contiguous icmps into a memcmp'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Natural Loop Information'
+ -- 'Lower Garbage Collection Instructions' is not preserving 'Expand memcmp() to load/stores'
+ -- 'Shadow Stack GC Lowering' is not preserving 'Lower Garbage Collection Instructions'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Lower @llvm.global_dtors via `__cxa_atexit`'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Function Pass Manager'
+ -- 'Constant Hoisting' is not preserving 'Remove unreachable blocks from the CFG'
+ -- 'Constant Hoisting' is not preserving 'Branch Probability Analysis'
+ -- 'Replace intrinsics with calls to vector library' is not preserving 'Constant Hoisting'
+ -- 'Partially inline calls to library functions' is not preserving 'Replace intrinsics with calls to vector library'
+ -- 'Partially inline calls to library functions' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Post-Dominator Tree Construction'
+ -- 'Partially inline calls to library functions' is not preserving 'Optimization Remark Emitter'
+ -- 'Partially inline calls to library functions' is not preserving 'Natural Loop Information'
+ -- 'Partially inline calls to library functions' is not preserving 'Block Frequency Analysis'
+ -- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is not preserving 'Partially inline calls to library functions'
+ -- 'Scalarize Masked Memory Intrinsics' is not preserving 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)'
+ -- 'Expand reduction intrinsics' is not preserving 'Scalarize Masked Memory Intrinsics'
+ -- 'AArch64 Stack Tagging' is not preserving 'Function Alias Analysis Results'
+ -- 'AArch64 Stack Tagging' is not preserving 'Optimization Remark Emitter'
+ -- 'AArch64 Stack Tagging' is not preserving 'Function Pass Manager'
+ -- 'AArch64 Stack Tagging' is not preserving 'Stack Safety Analysis'
+ -- 'Complex Deinterleaving Pass' is not preserving 'AArch64 Stack Tagging'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Function Alias Analysis Results'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Memory SSA'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Complex Deinterleaving Pass'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Natural Loop Information'
+ -- 'Interleaved Access Pass' is not preserving 'Interleaved Load Combine Pass'
+ -- 'SME ABI Pass' is not preserving 'Interleaved Access Pass'
+ -- 'SME ABI Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Type Promotion' is not preserving 'SME ABI Pass'
+ -- 'CodeGen Prepare' is not preserving 'Type Promotion'
+ -- 'CodeGen Prepare' is not preserving 'Dominator Tree Construction'
+ -- 'CodeGen Prepare' is not preserving 'Natural Loop Information'
+ -- 'Exception handling preparation' is not preserving 'CodeGen Prepare'
+ -- 'Merge internal globals' is not preserving 'AArch64 Promote Constant'
+ -- 'Merge internal globals' is not preserving 'Function Pass Manager'
+ -- 'ObjC ARC contraction' is not preserving 'Merge internal globals'
+ -- 'Prepare callbr' is not preserving 'ObjC ARC contraction'
+ -- 'Prepare callbr' is not preserving 'Function Alias Analysis Results'
+ -- 'Prepare callbr' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Safe Stack instrumentation pass' is not preserving 'Prepare callbr'
+ -- 'Insert stack protectors' is not preserving 'Safe Stack instrumentation pass'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Post-Dominator Tree Construction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'Assignment Tracking Analysis'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'AArch64 Instruction Selection'
+ -- 'SME Peephole Optimization pass' is not preserving 'Finalize ISel and expand pseudo-instructions'
+ -- 'Early Tail Duplication' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Early Tail Duplication' is not preserving 'SME Peephole Optimization pass'
+ -- 'Optimize machine instruction PHIs' is not preserving 'Early Tail Duplication'
+ -- 'Merge disjoint stack slots' is not preserving 'Optimize machine instruction PHIs'
+ -- 'Merge disjoint stack slots' is not preserving 'Slot index numbering'
+ -- 'Local Stack Slot Allocation' is not preserving 'Merge disjoint stack slots'
+ -- 'Remove dead machine instructions' is not preserving 'Local Stack Slot Allocation'
+ -- 'AArch64 Condition Optimizer' is not preserving 'Remove dead machine instructions'
+ -- 'AArch64 Conditional Compares' is not preserving 'AArch64 Condition Optimizer'
+ -- 'Machine InstCombiner' is not preserving 'AArch64 Conditional Compares'
+ -- 'AArch64 Conditional Branch Tuning' is not preserving 'Machine Trace Metrics'
+ -- 'AArch64 Conditional Branch Tuning' is not preserving 'Machine InstCombiner'
+ -- 'Early If-Conversion' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Early If-Conversion' is not preserving 'AArch64 Conditional Branch Tuning'
+ -- 'AArch64 Store Pair Suppression' is not preserving 'Early If-Conversion'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'Machine Trace Metrics'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'AArch64 Store Pair Suppression'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'MachineDominator Tree Construction'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'Machine Natural Loop Construction'
+ -- 'AArch64 Stack Tagging PreRA' is not preserving 'AArch64 SIMD instructions optimization pass'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'AArch64 Stack Tagging PreRA'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine Common Subexpression Elimination' is not preserving 'Early Machine Loop Invariant Code Motion'
+ -- 'Machine code sinking' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine code sinking' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'Machine Common Subexpression Elimination'
+ -- 'Peephole Optimizations' is not preserving 'Machine code sinking'
+ -- 'Remove dead machine instructions' is not preserving 'Peephole Optimizations'
+ -- 'AArch64 MI Peephole Optimization pass' is not preserving 'Remove dead machine instructions'
+ -- 'AArch64 Dead register definitions' is not preserving 'AArch64 MI Peephole Optimization pass'
+ -- 'Detect Dead Lanes' is not preserving 'AArch64 Dead register definitions'
+ -- 'Init Undef Pass' is not preserving 'Detect Dead Lanes'
+ -- 'Process Implicit Definitions' is not preserving 'Init Undef Pass'
+ -- 'Remove unreachable machine basic blocks' is not preserving 'Machine Cycle Info Analysis'
+ -- 'Remove unreachable machine basic blocks' is not preserving 'Process Implicit Definitions'
+ -- 'Eliminate PHI nodes for register allocation' is not preserving 'Remove unreachable machine basic blocks'
+ -- 'Two-Address instruction pass' is not preserving 'Eliminate PHI nodes for register allocation'
+ -- 'Live Interval Analysis' is not preserving 'Two-Address instruction pass'
+ -- 'Register Coalescer' is not preserving 'Live Variable Analysis'
+ -- 'Rename Disconnected Subregister Components' is not preserving 'Register Coalescer'
+ -- 'Machine Instruction Scheduler' is not preserving 'Rename Disconnected Subregister Components'
+ -- 'Greedy Register Allocator' is not preserving 'Machine Instruction Scheduler'
+ -- 'Greedy Register Allocator' is not preserving 'AArch64 Post Coalescer pass'
+ -- 'Virtual Register Rewriter' is not preserving 'Greedy Register Allocator'
+ -- 'Virtual Register Rewriter' is not preserving 'Live Register Matrix'
+ -- 'Virtual Register Rewriter' is not preserving 'Debug Variable Analysis'
+ -- 'Virtual Register Rewriter' is not preserving 'Virtual Register Map'
+ -- 'Stack Slot Coloring' is not preserving 'Virtual Register Rewriter'
+ -- 'Stack Slot Coloring' is not preserving 'Register Allocation Pass Scoring'
+ -- 'Stack Slot Coloring' is not preserving 'Live Stack Slot Analysis'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Stack Slot Coloring'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Live Interval Analysis'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Slot index numbering'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Bundle Machine CFG Edges'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Copy Propagation Pass'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Spill Code Placement Analysis'
+ -- 'AArch64 Redundant Copy Elimination' is not preserving 'Machine Natural Loop Construction'
+ -- 'AArch64 Redundant Copy Elimination' is not preserving 'Machine Loop Invariant Code Motion'
+ -- 'A57 FP Anti-dependency breaker' is not preserving 'AArch64 Redundant Copy Elimination'
+ -- 'Remove Redundant DEBUG_VALUE analysis' is not preserving 'A57 FP Anti-dependency breaker'
+ -- 'Fixup Statepoint Caller Saved' is not preserving 'Remove Redundant DEBUG_VALUE analysis'
+ -- 'PostRA Machine Sink' is not preserving 'Fixup Statepoint Caller Saved'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'PostRA Machine Sink'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'Shrink Wrapping analysis'
+ -- 'Machine Late Instructions Cleanup Pass' is not preserving 'Prologue/Epilogue Insertion & Frame Finalization'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Control Flow Optimizer' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Control Flow Optimizer' is not preserving 'MachineDominator Tree Construction'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Natural Loop Construction'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Control Flow Optimizer' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Late Instructions Cleanup Pass'
+ -- 'Tail Duplication' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Tail Duplication' is not preserving 'Control Flow Optimizer'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Tail Duplication'
+ -- 'Post-RA pseudo instruction expansion pass' is not preserving 'Machine Copy Propagation Pass'
+ -- 'AArch64 pseudo instruction expansion pass' is not preserving 'Post-RA pseudo instruction expansion pass'
+ -- 'AArch64 load / store optimization pass' is not preserving 'AArch64 pseudo instruction expansion pass'
+ -- 'Insert KCFI indirect call checks' is not preserving 'AArch64 load / store optimization pass'
+ -- 'AArch64 speculation hardening pass' is not preserving 'Insert KCFI indirect call checks'
+ -- 'Falkor HW Prefetch Fix Late Phase' is not preserving 'AArch64 speculation hardening pass'
+ -- 'PostRA Machine Instruction Scheduler' is not preserving 'Falkor HW Prefetch Fix Late Phase'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'PostRA Machine Instruction Scheduler'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'MachineDominator Tree Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Machine Natural Loop Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Analyze Machine Code For Garbage Collection'
+ -- 'Insert fentry calls' is not preserving 'Branch Probability Basic Block Placement'
+ -- 'Insert XRay ops' is not preserving 'Insert fentry calls'
+ -- 'Implement the 'patchable-function' attribute' is not preserving 'Insert XRay ops'
+ -- 'Workaround A53 erratum 835769 pass' is not preserving 'Implement the 'patchable-function' attribute'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'Workaround A53 erratum 835769 pass'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'AArch64 Collect Linker Optimization Hint (LOH)'
+ -- 'Remove Loads Into Fake Uses' is not preserving 'Contiguously Lay Out Funclets'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'Remove Loads Into Fake Uses'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'StackMap Liveness Analysis'
+ -- 'Machine Sanitizer Binary Metadata' is not preserving 'Live DEBUG_VALUE analysis'
+ -- 'AArch64 sls hardening pass' is not preserving 'Machine Outliner'
+ -- 'AArch64 sls hardening pass' is not preserving 'Function Pass Manager'
+ -- 'AArch64 Pointer Authentication' is not preserving 'AArch64 sls hardening pass'
+ -- 'AArch64 Branch Targets' is not preserving 'AArch64 Pointer Authentication'
+ -- 'Branch relaxation pass' is not preserving 'AArch64 Branch Targets'
+ -- 'AArch64 Compress Jump Tables' is not preserving 'Branch relaxation pass'
+ -- 'Unpack machine instruction bundles' is not preserving 'Insert CFI remember/restore state instructions'
+ -- 'Unpack machine instruction bundles' is not preserving 'AArch64 Compress Jump Tables'
+ -- 'Unpack machine instruction bundles' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Unpack machine instruction bundles' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Stack Frame Layout Analysis'
+ -- 'Free MachineFunction' is not preserving 'AArch64 Assembly Printer'
+ -- 'Free MachineFunction' is not preserving 'Unpack machine instruction bundles'
+ -- 'Free MachineFunction' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Free MachineFunction' is not preserving 'Lazy Machine Block Frequency Analysis'
+Pass Arguments: -tti -targetlibinfo -targetpassconfig -machinemoduleinfo -assumption-cache-tracker -profile-summary-info -tbaa -scoped-noalias-aa -collector-metadata -machine-branch-prob -regalloc-evict -regalloc-priority -pre-isel-intrinsic-lowering -expand-large-div-rem -expand-fp -atomic-expand -aarch64-sve-intrinsic-opts -simplifycfg -domtree -loops -loop-simplify -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -scalar-evolution -loop-data-prefetch -aarch64-falkor-hwpf-fix -basic-aa -loop-simplify -canon-freeze -iv-users -loop-reduce -basic-aa -aa -mergeicmps -loops -lazy-branch-prob -lazy-block-freq -expand-memcmp -gc-lowering -shadow-stack-gc-lowering -lower-global-dtors -unreachableblockelim -domtree -loops -postdomtree -branch-prob -block-freq -consthoist -replace-with-veclib -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -partially-inline-libcalls -post-inline-ee-instrument -scalarize-masked-mem-intrin -expand-reductions -stack-safety -domtree -basic-aa -aa -loops -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -aarch64-stack-tagging -complex-deinterleaving -aa -memoryssa -interleaved-load-combine -domtree -interleaved-access -aarch64-sme-abi -domtree -loops -type-promotion -codegenprepare -domtree -dwarf-eh-prepare -aarch64-promote-const -global-merge -domtree -basic-aa -aa -objc-arc-contract -callbrprepare -safe-stack -stack-protector -basic-aa -aa -loops -postdomtree -branch-prob -debug-ata -lazy-branch-prob -lazy-block-freq -aarch64-isel -finalize-isel -aarch64-sme-peephole-opt -lazy-machine-block-freq -early-tailduplication -opt-phis -slotindexes -stack-coloring -localstackalloc -dead-mi-elimination -machinedomtree -aarch64-condopt -machine-loops -machine-trace-metrics -aarch64-ccmp -lazy-machine-block-freq -machine-combiner -aarch64-cond-br-tuning -machine-trace-metrics -early-ifcvt -aarch64-stp-suppress -aarch64-simdinstr-opt -aarch64-stack-tagging-pre-ra -machinedomtree -machine-loops -machine-block-freq -early-machinelicm -machinedomtree -machine-block-freq -machine-cse -machinepostdomtree -machine-cycles -machine-sink -peephole-opt -dead-mi-elimination -aarch64-mi-peephole-opt -aarch64-dead-defs -detect-dead-lanes -init-undef -processimpdefs -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -machinedomtree -slotindexes -liveintervals -register-coalescer -rename-independent-subregs -machine-scheduler -aarch64-post-coalescer-pass -machine-block-freq -livedebugvars -livestacks -virtregmap -liveregmatrix -edge-bundles -spill-code-placement -lazy-machine-block-freq -machine-opt-remark-emitter -greedy -virtregrewriter -regallocscoringpass -stack-slot-coloring -machine-cp -machinelicm -aarch64-copyelim -aarch64-a57-fp-load-balancing -removeredundantdebugvalues -fixup-statepoint-caller-saved -postra-machine-sink -machinedomtree -machine-loops -machine-block-freq -machinepostdomtree -lazy-machine-block-freq -machine-opt-remark-emitter -shrink-wrap -prologepilog -machine-latecleanup -branch-folder -lazy-machine-block-freq -tailduplication -machine-cp -postrapseudos -aarch64-expand-pseudo -aarch64-ldst-opt -kcfi -aarch64-speculation-hardening -machinedomtree -machine-loops -aarch64-falkor-hwpf-fix-late -postmisched -gc-analysis -machine-block-freq -machinepostdomtree -block-placement -fentry-insert -xray-instrumentation -patchable-function -aarch64-fix-cortex-a53-835769-pass -aarch64-collect-loh -funclet-layout -remove-loads-into-fake-uses -stackmap-liveness -livedebugvalues -machine-sanmd -machine-outliner -aarch64-sls-hardening -aarch64-ptrauth -aarch64-branch-targets -branch-relaxation -aarch64-jump-tables -cfi-fixup -lazy-machine-block-freq -machine-opt-remark-emitter -stack-frame-layout -unpack-mi-bundles -lazy-machine-block-freq -machine-opt-remark-emitter -aarch64-asm-printer
+Target Transform Information
+Target Library Information
+Target Pass Configuration
+Machine Module Information
+Assumption Cache Tracker
+Profile summary info
+Type-Based Alias Analysis
+Scoped NoAlias Alias Analysis
+Create Garbage Collector Module Metadata
+Machine Branch Probability Analysis
+Default Regalloc Eviction Advisor
+Default Regalloc Priority Advisor
+ ModulePass Manager
+ Pre-ISel Intrinsic Lowering
+-- Pre-ISel Intrinsic Lowering
+ FunctionPass Manager
+ Expand large div/rem
+-- Expand large div/rem
+ Expand fp
+-- Expand fp
+ Expand Atomic instructions
+-- Expand Atomic instructions
+ SVE intrinsics optimizations
+ FunctionPass Manager
+ Dominator Tree Construction
+-- SVE intrinsics optimizations
+ FunctionPass Manager
+ Simplify the CFG
+-- Simplify the CFG
+ Dominator Tree Construction
+ Natural Loop Information
+ Canonicalize natural loops
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Scalar Evolution Analysis
+ Loop Data Prefetch
+-- Loop Data Prefetch
+-- Lazy Block Frequency Analysis
+-- Canonicalize natural loops
+-- Optimization Remark Emitter
+-- Lazy Branch Probability Analysis
+ Falkor HW Prefetch Fix
+-- Falkor HW Prefetch Fix
+ Basic Alias Analysis (stateless AA impl)
+-- Basic Alias Analysis (stateless AA impl)
+ Canonicalize natural loops
+ Loop Pass Manager
+ Canonicalize Freeze Instructions in Loops
+-- Canonicalize Freeze Instructions in Loops
+ Induction Variable Users
+ Loop Strength Reduction
+-- Induction Variable Users
+-- Loop Strength Reduction
+-- Natural Loop Information
+-- Scalar Evolution Analysis
+-- Canonicalize natural loops
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Merge contiguous icmps into a memcmp
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- Merge contiguous icmps into a memcmp
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Expand memcmp() to load/stores
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Dominator Tree Construction
+-- Expand memcmp() to load/stores
+ Lower Garbage Collection Instructions
+-- Lower Garbage Collection Instructions
+ Shadow Stack GC Lowering
+-- Shadow Stack GC Lowering
+ Lower @llvm.global_dtors via `__cxa_atexit`
+-- Lower @llvm.global_dtors via `__cxa_atexit`
+ FunctionPass Manager
+ Remove unreachable blocks from the CFG
+-- Remove unreachable blocks from the CFG
+ Dominator Tree Construction
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Block Frequency Analysis
+ Constant Hoisting
+-- Block Frequency Analysis
+-- Branch Probability Analysis
+-- Post-Dominator Tree Construction
+-- Constant Hoisting
+ Replace intrinsics with calls to vector library
+-- Replace intrinsics with calls to vector library
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Partially inline calls to library functions
+-- Optimization Remark Emitter
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Dominator Tree Construction
+-- Partially inline calls to library functions
+ Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+-- Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+ Scalarize Masked Memory Intrinsics
+-- Scalarize Masked Memory Intrinsics
+ Expand reduction intrinsics
+-- Expand reduction intrinsics
+ Stack Safety Analysis
+ FunctionPass Manager
+ Dominator Tree Construction
+ Natural Loop Information
+ Scalar Evolution Analysis
+ Stack Safety Local Analysis
+ FunctionPass Manager
+ Dominator Tree Construction
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ AArch64 Stack Tagging
+-- Function Alias Analysis Results
+-- AArch64 Stack Tagging
+-- Lazy Block Frequency Analysis
+-- Optimization Remark Emitter
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+ Complex Deinterleaving Pass
+-- Complex Deinterleaving Pass
+ Function Alias Analysis Results
+ Memory SSA
+ Interleaved Load Combine Pass
+-- Memory SSA
+-- Basic Alias Analysis (stateless AA impl)
+-- Function Alias Analysis Results
+-- Dominator Tree Construction
+-- Interleaved Load Combine Pass
+ Dominator Tree Construction
+ Interleaved Access Pass
+-- Dominator Tree Construction
+-- Interleaved Access Pass
+ SME ABI Pass
+-- SME ABI Pass
+ Dominator Tree Construction
+ Natural Loop Information
+ Type Promotion
+-- Type Promotion
+ CodeGen Prepare
+-- Natural Loop Information
+-- Dominator Tree Construction
+-- CodeGen Prepare
+ Dominator Tree Construction
+ Exception handling preparation
+-- Dominator Tree Construction
+-- Exception handling preparation
+-- Target Transform Information
+-- Stack Safety Analysis
+ AArch64 Promote Constant
+ FunctionPass Manager
+ Dominator Tree Construction
+-- AArch64 Promote Constant
+ FunctionPass Manager
+ Merge internal globals
+-- Merge internal globals
+ Dominator Tree Construction
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ ObjC ARC contraction
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- ObjC ARC contraction
+ Prepare callbr
+-- Prepare callbr
+ Safe Stack instrumentation pass
+-- Safe Stack instrumentation pass
+ Insert stack protectors
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Assignment Tracking Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ AArch64 Instruction Selection
+-- Lazy Block Frequency Analysis
+-- Lazy Branch Probability Analysis
+-- Assignment Tracking Analysis
+-- Insert stack protectors
+-- Natural Loop Information
+-- Post-Dominator Tree Construction
+-- AArch64 Instruction Selection
+-- Branch Probability Analysis
+ Finalize ISel and expand pseudo-instructions
+-- Finalize ISel and expand pseudo-instructions
+ SME Peephole Optimization pass
+-- SME Peephole Optimization pass
+ Lazy Machine Block Frequency Analysis
+ Early Tail Duplication
+-- Lazy Machine Block Frequency Analysis
+-- Early Tail Duplication
+ Optimize machine instruction PHIs
+-- Optimize machine instruction PHIs
+ Slot index numbering
+ Merge disjoint stack slots
+-- Slot index numbering
+-- Merge disjoint stack slots
+ Local Stack Slot Allocation
+-- Local Stack Slot Allocation
+ Remove dead machine instructions
+-- Remove dead machine instructions
+ MachineDominator Tree Construction
+ AArch64 Condition Optimizer
+-- AArch64 Condition Optimizer
+ Machine Natural Loop Construction
+ Machine Trace Metrics
+ AArch64 Conditional Compares
+-- AArch64 Conditional Compares
+ Lazy Machine Block Frequency Analysis
+ Machine InstCombiner
+-- Machine InstCombiner
+-- Machine Trace Metrics
+-- Lazy Machine Block Frequency Analysis
+ AArch64 Conditional Branch Tuning
+-- AArch64 Conditional Branch Tuning
+ Machine Trace Metrics
+ Early If-Conversion
+-- MachineDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Early If-Conversion
+ AArch64 Store Pair Suppression
+-- Machine Trace Metrics
+-- AArch64 Store Pair Suppression
+ AArch64 SIMD instructions optimization pass
+-- AArch64 SIMD instructions optimization pass
+ AArch64 Stack Tagging PreRA
+-- AArch64 Stack Tagging PreRA
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Machine Block Frequency Analysis
+ Early Machine Loop Invariant Code Motion
+-- Early Machine Loop Invariant Code Motion
+-- Machine Block Frequency Analysis
+-- MachineDominator Tree Construction
+ MachineDominator Tree Construction
+ Machine Block Frequency Analysis
+ Machine Common Subexpression Elimination
+-- Machine Common Subexpression Elimination
+ MachinePostDominator Tree Construction
+ Machine Cycle Info Analysis
+ Machine code sinking
+-- Machine code sinking
+-- Machine Block Frequency Analysis
+-- Machine Cycle Info Analysis
+-- MachineDominator Tree Construction
+-- MachinePostDominator Tree Construction
+ Peephole Optimizations
+-- Peephole Optimizations
+ Remove dead machine instructions
+-- Remove dead machine instructions
+ AArch64 MI Peephole Optimization pass
+-- AArch64 MI Peephole Optimization pass
+ AArch64 Dead register definitions
+-- AArch64 Dead register definitions
+ Detect Dead Lanes
+-- Detect Dead Lanes
+ Init Undef Pass
+-- Init Undef Pass
+ Process Implicit Definitions
+-- Process Implicit Definitions
+ Remove unreachable machine basic blocks
+ Live Variable Analysis
+ Eliminate PHI nodes for register allocation
+-- Eliminate PHI nodes for register allocation
+-- Remove unreachable machine basic blocks
+ Two-Address instruction pass
+-- Two-Address instruction pass
+-- Live Variable Analysis
+ MachineDominator Tree Construction
+ Slot index numbering
+ Live Interval Analysis
+ Register Coalescer
+-- Register Coalescer
+ Rename Disconnected Subregister Components
+-- Rename Disconnected Subregister Components
+ Machine Instruction Scheduler
+-- Machine Instruction Scheduler
+ AArch64 Post Coalescer pass
+-- AArch64 Post Coalescer pass
+ Machine Block Frequency Analysis
+ Debug Variable Analysis
+ Live Stack Slot Analysis
+ Virtual Register Map
+ Live Register Matrix
+ Bundle Machine CFG Edges
+ Spill Code Placement Analysis
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Greedy Register Allocator
+-- Greedy Register Allocator
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Bundle Machine CFG Edges
+-- Spill Code Placement Analysis
+ Virtual Register Rewriter
+-- Debug Variable Analysis
+-- Live Register Matrix
+-- Live Interval Analysis
+-- Virtual Register Map
+-- Virtual Register Rewriter
+ Register Allocation Pass Scoring
+-- Register Allocation Pass Scoring
+ Stack Slot Coloring
+-- Live Stack Slot Analysis
+-- Slot index numbering
+-- Stack Slot Coloring
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Machine Loop Invariant Code Motion
+-- Machine Natural Loop Construction
+-- Machine Block Frequency Analysis
+-- MachineDominator Tree Construction
+-- Machine Loop Invariant Code Motion
+ AArch64 Redundant Copy Elimination
+-- AArch64 Redundant Copy Elimination
+ A57 FP Anti-dependency breaker
+-- A57 FP Anti-dependency breaker
+ Remove Redundant DEBUG_VALUE analysis
+-- Remove Redundant DEBUG_VALUE analysis
+ Fixup Statepoint Caller Saved
+-- Fixup Statepoint Caller Saved
+ PostRA Machine Sink
+-- PostRA Machine Sink
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Machine Block Frequency Analysis
+ MachinePostDominator Tree Construction
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Shrink Wrapping analysis
+-- Lazy Machine Block Frequency Analysis
+-- MachinePostDominator Tree Construction
+-- MachineDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Shrink Wrapping analysis
+ Prologue/Epilogue Insertion & Frame Finalization
+-- Machine Optimization Remark Emitter
+-- Prologue/Epilogue Insertion & Frame Finalization
+ Machine Late Instructions Cleanup Pass
+-- Machine Late Instructions Cleanup Pass
+ Control Flow Optimizer
+-- Machine Block Frequency Analysis
+-- Control Flow Optimizer
+ Lazy Machine Block Frequency Analysis
+ Tail Duplication
+-- Lazy Machine Block Frequency Analysis
+-- Tail Duplication
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Post-RA pseudo instruction expansion pass
+-- Post-RA pseudo instruction expansion pass
+ AArch64 pseudo instruction expansion pass
+-- AArch64 pseudo instruction expansion pass
+ AArch64 load / store optimization pass
+-- AArch64 load / store optimization pass
+ Insert KCFI indirect call checks
+-- Insert KCFI indirect call checks
+ AArch64 speculation hardening pass
+-- AArch64 speculation hardening pass
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Falkor HW Prefetch Fix Late Phase
+-- Falkor HW Prefetch Fix Late Phase
+ PostRA Machine Instruction Scheduler
+-- MachineDominator Tree Construction
+-- PostRA Machine Instruction Scheduler
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- Dominator Tree Construction
+ Analyze Machine Code For Garbage Collection
+-- Analyze Machine Code For Garbage Collection
+ Machine Block Frequency Analysis
+ MachinePostDominator Tree Construction
+ Branch Probability Basic Block Placement
+-- Machine Block Frequency Analysis
+-- MachinePostDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Branch Probability Basic Block Placement
+ Insert fentry calls
+-- Insert fentry calls
+ Insert XRay ops
+-- Insert XRay ops
+ Implement the 'patchable-function' attribute
+-- Implement the 'patchable-function' attribute
+ Workaround A53 erratum 835769 pass
+-- Workaround A53 erratum 835769 pass
+ AArch64 Collect Linker Optimization Hint (LOH)
+-- AArch64 Collect Linker Optimization Hint (LOH)
+ Contiguously Lay Out Funclets
+-- Contiguously Lay Out Funclets
+ Remove Loads Into Fake Uses
+-- Remove Loads Into Fake Uses
+ StackMap Liveness Analysis
+-- StackMap Liveness Analysis
+ Live DEBUG_VALUE analysis
+-- Live DEBUG_VALUE analysis
+ Machine Sanitizer Binary Metadata
+-- Machine Sanitizer Binary Metadata
+-- Target Pass Configuration
+-- Profile summary info
+-- Assumption Cache Tracker
+-- Target Library Information
+-- Type-Based Alias Analysis
+-- Default Regalloc Priority Advisor
+-- Default Regalloc Eviction Advisor
+-- Scoped NoAlias Alias Analysis
+ Machine Outliner
+-- Machine Outliner
+ FunctionPass Manager
+ AArch64 sls hardening pass
+-- AArch64 sls hardening pass
+ AArch64 Pointer Authentication
+-- AArch64 Pointer Authentication
+ AArch64 Branch Targets
+-- AArch64 Branch Targets
+ Branch relaxation pass
+-- Branch relaxation pass
+ AArch64 Compress Jump Tables
+-- AArch64 Compress Jump Tables
+ Insert CFI remember/restore state instructions
+-- Insert CFI remember/restore state instructions
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Stack Frame Layout Analysis
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Stack Frame Layout Analysis
+ Unpack machine instruction bundles
+-- Unpack machine instruction bundles
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ AArch64 Assembly Printer
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- AArch64 Assembly Printer
+ Free MachineFunction
+-- Free MachineFunction
+-- Create Garbage Collector Module Metadata
+-- Machine Branch Probability Analysis
+-- Machine Module Information
+Pass Arguments: -domtree
+ FunctionPass Manager
+ Dominator Tree Construction
+Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution -stack-safety-local
+Assumption Cache Tracker
+Target Library Information
+ FunctionPass Manager
+ Dominator Tree Construction
+ Natural Loop Information
+ Scalar Evolution Analysis
+ Stack Safety Local Analysis
+Pass Arguments: -domtree
+ FunctionPass Manager
+ Dominator Tree Construction
+Running pass: Pre-ISel Intrinsic Lowering
+[2025-06-18 00:57:04.595052000] 0x1316457f0 Executing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+0x1316479a0 Required Analyses: Target Transform Information, Target Library Information, Target Pass Configuration
+ -*- 'Pre-ISel Intrinsic Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.595819000] 0x1316457f0 Freeing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:04.595870000] 0x1316457f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Expand large div/rem
+[2025-06-18 00:57:04.595922000] 0x131647a20 Executing Pass 'Expand large div/rem' on Function 'main'...
+0x1316479e0 Required Analyses: Target Pass Configuration
+0x1316479e0 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand large div/rem' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.596039000] 0x131647a20 Freeing Pass 'Expand large div/rem' on Function 'main'...
+Running pass: Expand fp
+[2025-06-18 00:57:04.596089000] 0x131647a20 Executing Pass 'Expand fp' on Function 'main'...
+0x131647970 Required Analyses: Target Pass Configuration
+0x131647970 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand fp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.596214000] 0x131647a20 Freeing Pass 'Expand fp' on Function 'main'...
+Running pass: Expand Atomic instructions
+[2025-06-18 00:57:04.596264000] 0x131647a20 Executing Pass 'Expand Atomic instructions' on Function 'main'...
+ -*- 'Expand Atomic instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.596321000] 0x131647a20 Freeing Pass 'Expand Atomic instructions' on Function 'main'...
+Running pass: SVE intrinsics optimizations
+[2025-06-18 00:57:04.596372000] 0x1316457f0 Executing Pass 'SVE intrinsics optimizations' on Module 'test.c'...
+0x131647c20 Required Analyses: Dominator Tree Construction
+0x131647c20 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'SVE intrinsics optimizations' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.596790000] 0x1316457f0 Freeing Pass 'SVE intrinsics optimizations' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:04.596841000] 0x1316457f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Simplify the CFG
+[2025-06-18 00:57:04.596891000] 0x131648310 Executing Pass 'Simplify the CFG' on Function 'main'...
+0x131647ec0 Required Analyses: Assumption Cache Tracker, Target Transform Information
+0x131647ec0 Preserved Analyses: Globals Alias Analysis
+ -*- 'Simplify the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.597009000] 0x131648310 Freeing Pass 'Simplify the CFG' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.597059000] 0x131648310 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:04.597122000] 0x131648310 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x131648680 Required Analyses: Dominator Tree Construction
+Running pass: Canonicalize natural loops
+[2025-06-18 00:57:04.597199000] 0x131648310 Executing Pass 'Canonicalize natural loops' on Function 'main'...
+0x131648750 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information
+0x131648750 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Basic Alias Analysis (stateless AA impl), Function Alias Analysis Results, Globals Alias Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Loop-Closed SSA Form Pass, Uninitialized Pass, Branch Probability Analysis, Memory SSA
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:04.597416000] 0x131648310 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x131648800 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:04.597513000] 0x131648310 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x131648880 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:04.597617000] 0x131648310 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x1316487d0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Scalar Evolution Analysis
+[2025-06-18 00:57:04.597731000] 0x131648310 Executing Pass 'Scalar Evolution Analysis' on Function 'main'...
+0x1316489d0 Required Analyses: Assumption Cache Tracker, Natural Loop Information, Dominator Tree Construction, Target Library Information
+Running pass: Loop Data Prefetch
+[2025-06-18 00:57:04.597838000] 0x131648310 Executing Pass 'Loop Data Prefetch' on Function 'main'...
+0x1316484d0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information, Canonicalize natural loops, Optimization Remark Emitter, Scalar Evolution Analysis, Target Transform Information
+0x1316484d0 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Canonicalize natural loops, Scalar Evolution Analysis
+ -*- 'Loop Data Prefetch' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.598031000] 0x131648310 Freeing Pass 'Loop Data Prefetch' on Function 'main'...
+[2025-06-18 00:57:04.598071000] 0x131648310 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.598139000] 0x131648310 Freeing Pass 'Canonicalize natural loops' on Function 'main'...
+[2025-06-18 00:57:04.598180000] 0x131648310 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.598221000] 0x131648310 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+Running pass: Falkor HW Prefetch Fix
+[2025-06-18 00:57:04.598290000] 0x131648310 Executing Pass 'Falkor HW Prefetch Fix' on Function 'main'...
+0x131648aa0 Required Analyses: Target Pass Configuration, Natural Loop Information, Scalar Evolution Analysis
+0x131648aa0 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Scalar Evolution Analysis
+ -*- 'Falkor HW Prefetch Fix' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.598436000] 0x131648310 Freeing Pass 'Falkor HW Prefetch Fix' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:04.598487000] 0x131648310 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x131648b80 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+ -*- 'Basic Alias Analysis (stateless AA impl)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.598587000] 0x131648310 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+Running pass: Canonicalize natural loops
+[2025-06-18 00:57:04.598640000] 0x131648310 Executing Pass 'Canonicalize natural loops' on Function 'main'...
+0x131648ce0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information
+0x131648ce0 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Basic Alias Analysis (stateless AA impl), Function Alias Analysis Results, Globals Alias Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Loop-Closed SSA Form Pass, Uninitialized Pass, Branch Probability Analysis, Memory SSA
+Running pass: Loop Pass Manager
+[2025-06-18 00:57:04.598859000] 0x131648310 Executing Pass 'Loop Pass Manager' on Function 'main'...
+0x131648d60 Required Analyses: Natural Loop Information, Dominator Tree Construction
+ -*- 'Loop Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.598948000] 0x131648310 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:04.598989000] 0x131648310 Freeing Pass 'Scalar Evolution Analysis' on Function 'main'...
+[2025-06-18 00:57:04.599033000] 0x131648310 Freeing Pass 'Canonicalize natural loops' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:04.599084000] 0x131648310 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x131649240 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:04.599180000] 0x131648310 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x1316491e0 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x1316491e0 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Merge contiguous icmps into a memcmp
+[2025-06-18 00:57:04.599342000] 0x131648310 Executing Pass 'Merge contiguous icmps into a memcmp' on Function 'main'...
+0x131649110 Required Analyses: Target Library Information, Target Transform Information, Function Alias Analysis Results
+0x131649110 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Merge contiguous icmps into a memcmp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.599494000] 0x131648310 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:04.599555000] 0x131648310 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:04.599596000] 0x131648310 Freeing Pass 'Merge contiguous icmps into a memcmp' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:04.599647000] 0x131648310 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x131649410 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:04.599725000] 0x131648310 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x131649270 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:04.599825000] 0x131648310 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x131649610 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Expand memcmp() to load/stores
+[2025-06-18 00:57:04.599930000] 0x131648310 Executing Pass 'Expand memcmp() to load/stores' on Function 'main'...
+0x131649080 Required Analyses: Target Library Information, Target Transform Information, Profile summary info, Lazy Branch Probability Analysis, Natural Loop Information, Lazy Block Frequency Analysis
+0x131649080 Preserved Analyses: Dominator Tree Construction
+ -*- 'Expand memcmp() to load/stores' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.600086000] 0x131648310 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.600127000] 0x131648310 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:04.600168000] 0x131648310 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:04.600209000] 0x131648310 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.600250000] 0x131648310 Freeing Pass 'Expand memcmp() to load/stores' on Function 'main'...
+Running pass: Lower Garbage Collection Instructions
+[2025-06-18 00:57:04.600301000] 0x131648310 Executing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+0x1316496a0 Required Analyses: Create Garbage Collector Module Metadata
+0x1316496a0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Lower Garbage Collection Instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.600403000] 0x131648310 Freeing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+Running pass: Shadow Stack GC Lowering
+[2025-06-18 00:57:04.600455000] 0x131648310 Executing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+0x131649780 Preserved Analyses: Dominator Tree Construction
+ -*- 'Shadow Stack GC Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.600533000] 0x131648310 Freeing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+Running pass: Lower @llvm.global_dtors via `__cxa_atexit`
+[2025-06-18 00:57:04.600586000] 0x1316457f0 Executing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+0x1316497f0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Lower @llvm.global_dtors via `__cxa_atexit`' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.600963000] 0x1316457f0 Freeing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:04.601014000] 0x1316457f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Remove unreachable blocks from the CFG
+[2025-06-18 00:57:04.601077000] 0x131649870 Executing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+0x131649830 Preserved Analyses: Dominator Tree Construction
+ -*- 'Remove unreachable blocks from the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.601159000] 0x131649870 Freeing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.601211000] 0x131649870 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:04.601266000] 0x131649870 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x131649e50 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:57:04.601341000] 0x131649870 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:57:04.601394000] 0x131649870 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x131649c90 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Block Frequency Analysis
+[2025-06-18 00:57:04.601522000] 0x131649870 Executing Pass 'Block Frequency Analysis' on Function 'main'...
+0x1316493e0 Required Analyses: Branch Probability Analysis, Natural Loop Information
+Running pass: Constant Hoisting
+[2025-06-18 00:57:04.602330000] 0x131649870 Executing Pass 'Constant Hoisting' on Function 'main'...
+0x1318bba00 Required Analyses: Block Frequency Analysis, Dominator Tree Construction, Profile summary info, Target Transform Information
+0x1318bba00 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Constant Hoisting' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.602749000] 0x131649870 Freeing Pass 'Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.602791000] 0x131649870 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:04.602849000] 0x131649870 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.602893000] 0x131649870 Freeing Pass 'Constant Hoisting' on Function 'main'...
+Running pass: Replace intrinsics with calls to vector library
+[2025-06-18 00:57:04.602958000] 0x131649870 Executing Pass 'Replace intrinsics with calls to vector library' on Function 'main'...
+0x131649f80 Required Analyses: Target Library Information
+0x131649f80 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Target Library Information, Scalar Evolution Analysis, Function Alias Analysis Results, Optimization Remark Emitter, Globals Alias Analysis
+ -*- 'Replace intrinsics with calls to vector library' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.603398000] 0x131649870 Freeing Pass 'Replace intrinsics with calls to vector library' on Function 'main'...
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:04.603449000] 0x131649870 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x13164a1f0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:04.603544000] 0x131649870 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x13164a270 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:04.603648000] 0x131649870 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x13164a1c0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Partially inline calls to library functions
+[2025-06-18 00:57:04.603762000] 0x131649870 Executing Pass 'Partially inline calls to library functions' on Function 'main'...
+0x13164a130 Required Analyses: Target Library Information, Target Transform Information, Optimization Remark Emitter
+0x13164a130 Preserved Analyses: Dominator Tree Construction
+ -*- 'Partially inline calls to library functions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.603884000] 0x131649870 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.603925000] 0x131649870 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.603965000] 0x131649870 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:04.604006000] 0x131649870 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:04.604054000] 0x131649870 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.604095000] 0x131649870 Freeing Pass 'Partially inline calls to library functions' on Function 'main'...
+Running pass: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+[2025-06-18 00:57:04.604146000] 0x131649870 Executing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+0x13164a320 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.604253000] 0x131649870 Freeing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+Running pass: Scalarize Masked Memory Intrinsics
+[2025-06-18 00:57:04.604304000] 0x131649870 Executing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+0x13164a3a0 Required Analyses: Target Transform Information
+0x13164a3a0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Scalarize Masked Memory Intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.604438000] 0x131649870 Freeing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+Running pass: Expand reduction intrinsics
+[2025-06-18 00:57:04.604489000] 0x131649870 Executing Pass 'Expand reduction intrinsics' on Function 'main'...
+0x13164a450 Required Analyses: Target Transform Information
+0x13164a450 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Expand reduction intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.604873000] 0x131649870 Freeing Pass 'Expand reduction intrinsics' on Function 'main'...
+Running pass: Stack Safety Analysis
+[2025-06-18 00:57:04.604932000] 0x1316457f0 Executing Pass 'Stack Safety Analysis' on Module 'test.c'...
+0x13164a8d0 Required Analyses: Stack Safety Local Analysis
+Running pass: Function Pass Manager
+[2025-06-18 00:57:04.605009000] 0x1316457f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.605060000] 0x13164b2a0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:04.605112000] 0x13164b2a0 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x13164b180 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:04.605211000] 0x13164b2a0 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x13164ac40 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x13164ac40 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Natural Loop Information
+[2025-06-18 00:57:04.605362000] 0x13164b2a0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x13164b550 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:04.605437000] 0x13164b2a0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x13164b4f0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:04.605551000] 0x13164b2a0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x13164b640 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:04.605654000] 0x13164b2a0 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x13164b1b0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: AArch64 Stack Tagging
+[2025-06-18 00:57:04.605767000] 0x13164b2a0 Executing Pass 'AArch64 Stack Tagging' on Function 'main'...
+0x13164a610 Required Analyses: Stack Safety Analysis, Function Alias Analysis Results, Optimization Remark Emitter
+0x13164a610 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'AArch64 Stack Tagging' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.606165000] 0x13164b2a0 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:04.606205000] 0x13164b2a0 Freeing Pass 'AArch64 Stack Tagging' on Function 'main'...
+[2025-06-18 00:57:04.606245000] 0x13164b2a0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.606285000] 0x13164b2a0 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.606326000] 0x13164b2a0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:04.606366000] 0x13164b2a0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+Running pass: Complex Deinterleaving Pass
+[2025-06-18 00:57:04.606427000] 0x13164b2a0 Executing Pass 'Complex Deinterleaving Pass' on Function 'main'...
+0x13164b520 Required Analyses: Target Library Information
+0x13164b520 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Complex Deinterleaving Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.606826000] 0x13164b2a0 Freeing Pass 'Complex Deinterleaving Pass' on Function 'main'...
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:04.606892000] 0x13164b2a0 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x13164b7d0 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x13164b7d0 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Memory SSA
+[2025-06-18 00:57:04.607043000] 0x13164b2a0 Executing Pass 'Memory SSA' on Function 'main'...
+0x13164b7a0 Required Analyses: Dominator Tree Construction, Function Alias Analysis Results
+Running pass: Interleaved Load Combine Pass
+[2025-06-18 00:57:04.607131000] 0x13164b2a0 Executing Pass 'Interleaved Load Combine Pass' on Function 'main'...
+0x13164b780 Required Analyses: Memory SSA, Dominator Tree Construction, Target Transform Information
+ -*- 'Interleaved Load Combine Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.607231000] 0x13164b2a0 Freeing Pass 'Memory SSA' on Function 'main'...
+[2025-06-18 00:57:04.607272000] 0x13164b2a0 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:04.607312000] 0x13164b2a0 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:04.607353000] 0x13164b2a0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.607394000] 0x13164b2a0 Freeing Pass 'Interleaved Load Combine Pass' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.607444000] 0x13164b2a0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Interleaved Access Pass
+[2025-06-18 00:57:04.607494000] 0x13164b2a0 Executing Pass 'Interleaved Access Pass' on Function 'main'...
+0x13164b800 Required Analyses: Dominator Tree Construction
+0x13164b800 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Interleaved Access Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.607875000] 0x13164b2a0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.607917000] 0x13164b2a0 Freeing Pass 'Interleaved Access Pass' on Function 'main'...
+Running pass: SME ABI Pass
+[2025-06-18 00:57:04.607967000] 0x13164b2a0 Executing Pass 'SME ABI Pass' on Function 'main'...
+ -*- 'SME ABI Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.608023000] 0x13164b2a0 Freeing Pass 'SME ABI Pass' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.608074000] 0x13164b2a0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:04.608125000] 0x13164b2a0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x13164bbe0 Required Analyses: Dominator Tree Construction
+Running pass: Type Promotion
+[2025-06-18 00:57:04.608200000] 0x13164b2a0 Executing Pass 'Type Promotion' on Function 'main'...
+0x13164b9c0 Required Analyses: Natural Loop Information, Target Transform Information, Target Pass Configuration
+0x13164b9c0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Type Promotion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.608622000] 0x13164b2a0 Freeing Pass 'Type Promotion' on Function 'main'...
+Running pass: CodeGen Prepare
+[2025-06-18 00:57:04.608673000] 0x13164b2a0 Executing Pass 'CodeGen Prepare' on Function 'main'...
+0x13164bf70 Required Analyses: Profile summary info, Target Library Information, Target Pass Configuration, Target Transform Information, Natural Loop Information
+0x13164bf70 Used Analyses: Reads and parses a basic block sections profile.
+ -*- 'CodeGen Prepare' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.609349000] 0x13164b2a0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:04.609391000] 0x13164b2a0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.609433000] 0x13164b2a0 Freeing Pass 'CodeGen Prepare' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.609484000] 0x13164b2a0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Exception handling preparation
+[2025-06-18 00:57:04.609535000] 0x13164b2a0 Executing Pass 'Exception handling preparation' on Function 'main'...
+0x13164bfb0 Required Analyses: Target Pass Configuration, Target Transform Information, Dominator Tree Construction
+0x13164bfb0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Exception handling preparation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.609657000] 0x13164b2a0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.609697000] 0x13164b2a0 Freeing Pass 'Exception handling preparation' on Function 'main'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.609751000] 0x1316457f0 Freeing Pass 'Target Transform Information' on Module 'test.c'...
+[2025-06-18 00:57:04.609791000] 0x1316457f0 Freeing Pass 'Stack Safety Analysis' on Module 'test.c'...
+Running pass: AArch64 Promote Constant
+[2025-06-18 00:57:04.609842000] 0x1316457f0 Executing Pass 'AArch64 Promote Constant' on Module 'test.c'...
+0x13164c0f0 Required Analyses: Dominator Tree Construction
+0x13164c0f0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'AArch64 Promote Constant' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.610246000] 0x1316457f0 Freeing Pass 'AArch64 Promote Constant' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:04.610297000] 0x1316457f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Merge internal globals
+[2025-06-18 00:57:04.610347000] 0x13164c720 Executing Pass 'Merge internal globals' on Function 'main'...
+0x13164c5a0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction
+ -*- 'Merge internal globals' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.610705000] 0x13164c720 Freeing Pass 'Merge internal globals' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:04.610756000] 0x13164c720 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:04.610807000] 0x13164c720 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x13164c680 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:04.610901000] 0x13164c720 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x13164c900 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x13164c900 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: ObjC ARC contraction
+[2025-06-18 00:57:04.611048000] 0x13164c720 Executing Pass 'ObjC ARC contraction' on Function 'main'...
+0x13164c8e0 Required Analyses: Function Alias Analysis Results, Dominator Tree Construction
+0x13164c8e0 Preserved Analyses: Function Alias Analysis Results, Basic Alias Analysis (stateless AA impl), Dominator Tree Construction
+ -*- 'ObjC ARC contraction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.611195000] 0x13164c720 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:04.611235000] 0x13164c720 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:04.611276000] 0x13164c720 Freeing Pass 'ObjC ARC contraction' on Function 'main'...
+Running pass: Prepare callbr
+[2025-06-18 00:57:04.611326000] 0x13164c720 Executing Pass 'Prepare callbr' on Function 'main'...
+0x13164ca20 Preserved Analyses: Dominator Tree Construction
+ -*- 'Prepare callbr' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.611403000] 0x13164c720 Freeing Pass 'Prepare callbr' on Function 'main'...
+Running pass: Safe Stack instrumentation pass
+[2025-06-18 00:57:04.611473000] 0x13164c720 Executing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+0x13164c6b0 Required Analyses: Target Pass Configuration, Target Library Information, Assumption Cache Tracker
+0x13164c6b0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Safe Stack instrumentation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.611594000] 0x13164c720 Freeing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+Running pass: Insert stack protectors
+[2025-06-18 00:57:04.611645000] 0x13164c720 Executing Pass 'Insert stack protectors' on Function 'main'...
+0x13164ccc0 Required Analyses: Target Pass Configuration
+0x13164ccc0 Preserved Analyses: Dominator Tree Construction
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:04.611744000] 0x13164c720 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x13164cbf0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:04.611839000] 0x13164c720 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x13164cc80 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x13164cc80 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Natural Loop Information
+[2025-06-18 00:57:04.611987000] 0x13164c720 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x13164e300 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:57:04.612061000] 0x13164c720 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:57:04.612112000] 0x13164c720 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x13164e1e0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Assignment Tracking Analysis
+[2025-06-18 00:57:04.612217000] 0x13164c720 Executing Pass 'Assignment Tracking Analysis' on Function 'main'...
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:04.612268000] 0x13164c720 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x13164e6b0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:04.612362000] 0x13164c720 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x13164e730 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: AArch64 Instruction Selection
+[2025-06-18 00:57:04.612468000] 0x13164c720 Executing Pass 'AArch64 Instruction Selection' on Function 'main'...
+0x13164caa0 Required Analyses: Function Alias Analysis Results, Create Garbage Collector Module Metadata, Insert stack protectors, Target Library Information, Assumption Cache Tracker, Branch Probability Analysis, Profile summary info, Assignment Tracking Analysis, Lazy Branch Probability Analysis, Natural Loop Information, Lazy Block Frequency Analysis, Machine Module Information
+[2025-06-18 00:57:04.620545000] 0x13164c720 Made Modification 'AArch64 Instruction Selection' on Function 'main'...
+0x13164caa0 Preserved Analyses: Create Garbage Collector Module Metadata, Assignment Tracking Analysis, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Post-Dominator Tree Construction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'AArch64 Instruction Selection' is not preserving 'Function Pass Manager'
+ -*- 'AArch64 Instruction Selection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.620863000] 0x13164c720 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.620904000] 0x13164c720 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:04.620945000] 0x13164c720 Freeing Pass 'Assignment Tracking Analysis' on Function 'main'...
+[2025-06-18 00:57:04.620985000] 0x13164c720 Freeing Pass 'Insert stack protectors' on Function 'main'...
+[2025-06-18 00:57:04.621025000] 0x13164c720 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:04.621066000] 0x13164c720 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.621106000] 0x13164c720 Freeing Pass 'AArch64 Instruction Selection' on Function 'main'...
+[2025-06-18 00:57:04.621147000] 0x13164c720 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+Running pass: Finalize ISel and expand pseudo-instructions
+[2025-06-18 00:57:04.621197000] 0x13164c720 Executing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+0x13164e960 Required Analyses: Machine Module Information
+0x13164e960 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Finalize ISel and expand pseudo-instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.621672000] 0x13164c720 Freeing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+Running pass: SME Peephole Optimization pass
+[2025-06-18 00:57:04.621723000] 0x13164c720 Executing Pass 'SME Peephole Optimization pass' on Function 'main'...
+0x13164e9a0 Required Analyses: Machine Module Information
+0x13164e9a0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'SME Peephole Optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.622181000] 0x13164c720 Freeing Pass 'SME Peephole Optimization pass' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.622247000] 0x13164c720 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x13164ec10 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x13164ec10 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early Tail Duplication
+[2025-06-18 00:57:04.622454000] 0x13164c720 Executing Pass 'Early Tail Duplication' on Function 'main'...
+0x13164eb20 Required Analyses: Machine Branch Probability Analysis, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x13164eb20 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early Tail Duplication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.622686000] 0x13164c720 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.622741000] 0x13164c720 Freeing Pass 'Early Tail Duplication' on Function 'main'...
+Running pass: Optimize machine instruction PHIs
+[2025-06-18 00:57:04.622794000] 0x13164c720 Executing Pass 'Optimize machine instruction PHIs' on Function 'main'...
+0x13164ecb0 Required Analyses: Machine Module Information
+0x13164ecb0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Optimize machine instruction PHIs' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.623252000] 0x13164c720 Freeing Pass 'Optimize machine instruction PHIs' on Function 'main'...
+Running pass: Slot index numbering
+[2025-06-18 00:57:04.623303000] 0x13164c720 Executing Pass 'Slot index numbering' on Function 'main'...
+0x13164f120 Required Analyses: Machine Module Information
+0x13164f120 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Merge disjoint stack slots
+[2025-06-18 00:57:04.623499000] 0x13164c720 Executing Pass 'Merge disjoint stack slots' on Function 'main'...
+0x13164ee50 Required Analyses: Slot index numbering, Machine Module Information
+0x13164ee50 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Merge disjoint stack slots' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.623725000] 0x13164c720 Freeing Pass 'Slot index numbering' on Function 'main'...
+[2025-06-18 00:57:04.623766000] 0x13164c720 Freeing Pass 'Merge disjoint stack slots' on Function 'main'...
+Running pass: Local Stack Slot Allocation
+[2025-06-18 00:57:04.623817000] 0x13164c720 Executing Pass 'Local Stack Slot Allocation' on Function 'main'...
+0x13164ee90 Required Analyses: Machine Module Information
+0x13164ee90 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Local Stack Slot Allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.624279000] 0x13164c720 Freeing Pass 'Local Stack Slot Allocation' on Function 'main'...
+Running pass: Remove dead machine instructions
+[2025-06-18 00:57:04.624330000] 0x13164c720 Executing Pass 'Remove dead machine instructions' on Function 'main'...
+0x13164f310 Required Analyses: Machine Module Information
+0x13164f310 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove dead machine instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.624812000] 0x13164c720 Freeing Pass 'Remove dead machine instructions' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:04.624880000] 0x13164c720 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x13164e7f0 Required Analyses: Machine Module Information
+0x13164e7f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Condition Optimizer
+[2025-06-18 00:57:04.625095000] 0x13164c720 Executing Pass 'AArch64 Condition Optimizer' on Function 'main'...
+0x13164e7a0 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x13164e7a0 Preserved Analyses: MachineDominator Tree Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Condition Optimizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.625319000] 0x13164c720 Freeing Pass 'AArch64 Condition Optimizer' on Function 'main'...
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:04.625371000] 0x13164c720 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x13164fa20 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x13164fa20 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Trace Metrics
+[2025-06-18 00:57:04.625580000] 0x13164c720 Executing Pass 'Machine Trace Metrics' on Function 'main'...
+0x13164fba0 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x13164fba0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Conditional Compares
+[2025-06-18 00:57:04.625785000] 0x13164c720 Executing Pass 'AArch64 Conditional Compares' on Function 'main'...
+0x13164f710 Required Analyses: Machine Branch Probability Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information
+0x13164f710 Preserved Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Conditional Compares' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.626054000] 0x13164c720 Freeing Pass 'AArch64 Conditional Compares' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.626106000] 0x13164c720 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x13164f5a0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x13164f5a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine InstCombiner
+[2025-06-18 00:57:04.626326000] 0x13164c720 Executing Pass 'Machine InstCombiner' on Function 'main'...
+0x13164fec0 Required Analyses: Machine Natural Loop Construction, Machine Trace Metrics, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x13164fec0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Trace Metrics, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine InstCombiner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.627332000] 0x13164c720 Freeing Pass 'Machine InstCombiner' on Function 'main'...
+[2025-06-18 00:57:04.627373000] 0x13164c720 Freeing Pass 'Machine Trace Metrics' on Function 'main'...
+[2025-06-18 00:57:04.627416000] 0x13164c720 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+Running pass: AArch64 Conditional Branch Tuning
+[2025-06-18 00:57:04.627467000] 0x13164c720 Executing Pass 'AArch64 Conditional Branch Tuning' on Function 'main'...
+0x13164f9b0 Required Analyses: Machine Module Information
+0x13164f9b0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Conditional Branch Tuning' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.627929000] 0x13164c720 Freeing Pass 'AArch64 Conditional Branch Tuning' on Function 'main'...
+Running pass: Machine Trace Metrics
+[2025-06-18 00:57:04.627981000] 0x13164c720 Executing Pass 'Machine Trace Metrics' on Function 'main'...
+0x1316506b0 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x1316506b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early If-Conversion
+[2025-06-18 00:57:04.628199000] 0x13164c720 Executing Pass 'Early If-Conversion' on Function 'main'...
+0x13164fde0 Required Analyses: Machine Branch Probability Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information
+0x13164fde0 Preserved Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early If-Conversion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.628472000] 0x13164c720 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.628513000] 0x13164c720 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:04.628554000] 0x13164c720 Freeing Pass 'Early If-Conversion' on Function 'main'...
+Running pass: AArch64 Store Pair Suppression
+[2025-06-18 00:57:04.628605000] 0x13164c720 Executing Pass 'AArch64 Store Pair Suppression' on Function 'main'...
+0x1316508c0 Required Analyses: Machine Trace Metrics, Machine Module Information
+0x1316508c0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Trace Metrics, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Store Pair Suppression' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.629087000] 0x13164c720 Freeing Pass 'Machine Trace Metrics' on Function 'main'...
+[2025-06-18 00:57:04.629129000] 0x13164c720 Freeing Pass 'AArch64 Store Pair Suppression' on Function 'main'...
+Running pass: AArch64 SIMD instructions optimization pass
+[2025-06-18 00:57:04.629180000] 0x13164c720 Executing Pass 'AArch64 SIMD instructions optimization pass' on Function 'main'...
+0x131650a40 Required Analyses: Machine Module Information
+0x131650a40 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 SIMD instructions optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.631249000] 0x13164c720 Freeing Pass 'AArch64 SIMD instructions optimization pass' on Function 'main'...
+Running pass: AArch64 Stack Tagging PreRA
+[2025-06-18 00:57:04.631301000] 0x13164c720 Executing Pass 'AArch64 Stack Tagging PreRA' on Function 'main'...
+0x131650cc0 Required Analyses: Machine Module Information
+0x131650cc0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Stack Tagging PreRA' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.631765000] 0x13164c720 Freeing Pass 'AArch64 Stack Tagging PreRA' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:04.631818000] 0x13164c720 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x131650dc0 Required Analyses: Machine Module Information
+0x131650dc0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:04.632015000] 0x13164c720 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x131650e80 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x131650e80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:04.632224000] 0x13164c720 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x131650fb0 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x131650fb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early Machine Loop Invariant Code Motion
+[2025-06-18 00:57:04.632447000] 0x13164c720 Executing Pass 'Early Machine Loop Invariant Code Motion' on Function 'main'...
+0x13164fe20 Required Analyses: Machine Natural Loop Construction, Machine Block Frequency Analysis, MachineDominator Tree Construction, Function Alias Analysis Results, Machine Module Information
+0x13164fe20 Preserved Analyses: Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early Machine Loop Invariant Code Motion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.632964000] 0x13164c720 Freeing Pass 'Early Machine Loop Invariant Code Motion' on Function 'main'...
+[2025-06-18 00:57:04.633008000] 0x13164c720 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.633051000] 0x13164c720 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:04.633103000] 0x13164c720 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x131651580 Required Analyses: Machine Module Information
+0x131651580 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:04.633302000] 0x13164c720 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x131651640 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x131651640 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Common Subexpression Elimination
+[2025-06-18 00:57:04.633522000] 0x13164c720 Executing Pass 'Machine Common Subexpression Elimination' on Function 'main'...
+0x131650ff0 Required Analyses: Machine Module Information, MachineDominator Tree Construction, Machine Block Frequency Analysis
+0x131650ff0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Common Subexpression Elimination' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.635041000] 0x13164c720 Freeing Pass 'Machine Common Subexpression Elimination' on Function 'main'...
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:57:04.635093000] 0x13164c720 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x131651290 Required Analyses: Machine Module Information
+0x131651290 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Cycle Info Analysis
+[2025-06-18 00:57:04.635350000] 0x13164c720 Executing Pass 'Machine Cycle Info Analysis' on Function 'main'...
+0x1316511a0 Required Analyses: Machine Module Information
+0x1316511a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine code sinking
+[2025-06-18 00:57:04.635555000] 0x13164c720 Executing Pass 'Machine code sinking' on Function 'main'...
+0x1316510c0 Required Analyses: Machine Module Information, Function Alias Analysis Results, MachineDominator Tree Construction, MachinePostDominator Tree Construction, Machine Cycle Info Analysis, Machine Branch Probability Analysis, Profile summary info, Machine Block Frequency Analysis, Target Pass Configuration
+[2025-06-18 00:57:04.635713000] 0x13164c720 Made Modification 'Machine code sinking' on Function 'main'...
+0x1316510c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Machine Cycle Info Analysis, Machine Natural Loop Construction
+ -- 'Machine code sinking' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine code sinking' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'MachineDominator Tree Construction'
+ -*- 'Machine code sinking' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.635960000] 0x13164c720 Freeing Pass 'Machine code sinking' on Function 'main'...
+[2025-06-18 00:57:04.636001000] 0x13164c720 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.636044000] 0x13164c720 Freeing Pass 'Machine Cycle Info Analysis' on Function 'main'...
+[2025-06-18 00:57:04.636085000] 0x13164c720 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.636126000] 0x13164c720 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+Running pass: Peephole Optimizations
+[2025-06-18 00:57:04.636178000] 0x13164c720 Executing Pass 'Peephole Optimizations' on Function 'main'...
+0x131651140 Required Analyses: Machine Module Information, Machine Natural Loop Construction
+0x131651140 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Peephole Optimizations' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.637268000] 0x13164c720 Freeing Pass 'Peephole Optimizations' on Function 'main'...
+Running pass: Remove dead machine instructions
+[2025-06-18 00:57:04.637322000] 0x13164c720 Executing Pass 'Remove dead machine instructions' on Function 'main'...
+0x131651230 Required Analyses: Machine Module Information
+0x131651230 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove dead machine instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.637785000] 0x13164c720 Freeing Pass 'Remove dead machine instructions' on Function 'main'...
+Running pass: AArch64 MI Peephole Optimization pass
+[2025-06-18 00:57:04.637837000] 0x13164c720 Executing Pass 'AArch64 MI Peephole Optimization pass' on Function 'main'...
+0x131651c60 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x131651c60 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 MI Peephole Optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.638320000] 0x13164c720 Freeing Pass 'AArch64 MI Peephole Optimization pass' on Function 'main'...
+Running pass: AArch64 Dead register definitions
+[2025-06-18 00:57:04.638380000] 0x13164c720 Executing Pass 'AArch64 Dead register definitions' on Function 'main'...
+0x131651e10 Required Analyses: Machine Module Information
+0x131651e10 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Dead register definitions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.638878000] 0x13164c720 Freeing Pass 'AArch64 Dead register definitions' on Function 'main'...
+Running pass: Detect Dead Lanes
+[2025-06-18 00:57:04.638930000] 0x13164c720 Executing Pass 'Detect Dead Lanes' on Function 'main'...
+0x13164f3c0 Required Analyses: Machine Module Information
+0x13164f3c0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Detect Dead Lanes' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.639402000] 0x13164c720 Freeing Pass 'Detect Dead Lanes' on Function 'main'...
+Running pass: Init Undef Pass
+[2025-06-18 00:57:04.639461000] 0x13164c720 Executing Pass 'Init Undef Pass' on Function 'main'...
+0x13164f420 Required Analyses: Machine Module Information
+0x13164f420 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Init Undef Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.639969000] 0x13164c720 Freeing Pass 'Init Undef Pass' on Function 'main'...
+Running pass: Process Implicit Definitions
+[2025-06-18 00:57:04.640020000] 0x13164c720 Executing Pass 'Process Implicit Definitions' on Function 'main'...
+0x131651e70 Required Analyses: Machine Module Information
+0x131651e70 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Function Alias Analysis Results, Machine Module Information, Uninitialized Pass, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Process Implicit Definitions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.640488000] 0x13164c720 Freeing Pass 'Process Implicit Definitions' on Function 'main'...
+Running pass: Remove unreachable machine basic blocks
+[2025-06-18 00:57:04.640538000] 0x13164c720 Executing Pass 'Remove unreachable machine basic blocks' on Function 'main'...
+0x13164f530 Required Analyses: Machine Module Information
+0x13164f530 Preserved Analyses: Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Variable Analysis
+[2025-06-18 00:57:04.640761000] 0x13164c720 Executing Pass 'Live Variable Analysis' on Function 'main'...
+0x131652160 Required Analyses: Remove unreachable machine basic blocks, Machine Module Information
+0x131652160 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Eliminate PHI nodes for register allocation
+[2025-06-18 00:57:04.641004000] 0x13164c720 Executing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+0x131652260 Required Analyses: Machine Module Information
+0x131652260 Preserved Analyses: Live Variable Analysis, Slot index numbering, Live Interval Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x131652260 Used Analyses: Live Variable Analysis
+ -*- 'Eliminate PHI nodes for register allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.641322000] 0x13164c720 Freeing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+[2025-06-18 00:57:04.641372000] 0x13164c720 Freeing Pass 'Remove unreachable machine basic blocks' on Function 'main'...
+Running pass: Two-Address instruction pass
+[2025-06-18 00:57:04.641423000] 0x13164c720 Executing Pass 'Two-Address instruction pass' on Function 'main'...
+0x131651770 Required Analyses: Machine Module Information
+0x131651770 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Live Variable Analysis, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x131651770 Used Analyses: Function Alias Analysis Results, Live Variable Analysis
+ -*- 'Two-Address instruction pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.641984000] 0x13164c720 Freeing Pass 'Two-Address instruction pass' on Function 'main'...
+[2025-06-18 00:57:04.642037000] 0x13164c720 Freeing Pass 'Live Variable Analysis' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:04.642088000] 0x13164c720 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x131651a00 Required Analyses: Machine Module Information
+0x131651a00 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Slot index numbering
+[2025-06-18 00:57:04.642284000] 0x13164c720 Executing Pass 'Slot index numbering' on Function 'main'...
+0x131652820 Required Analyses: Machine Module Information
+0x131652820 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Interval Analysis
+[2025-06-18 00:57:04.642486000] 0x13164c720 Executing Pass 'Live Interval Analysis' on Function 'main'...
+0x1316522c0 Required Analyses: MachineDominator Tree Construction, Slot index numbering, Machine Module Information
+0x1316522c0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Live Variable Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Register Coalescer
+[2025-06-18 00:57:04.643025000] 0x13164c720 Executing Pass 'Register Coalescer' on Function 'main'...
+0x131652610 Required Analyses: Live Interval Analysis, Machine Natural Loop Construction, Machine Module Information
+[2025-06-18 00:57:04.643151000] 0x13164c720 Made Modification 'Register Coalescer' on Function 'main'...
+0x131652610 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Live Interval Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x131652610 Used Analyses: Slot index numbering
+ -*- 'Register Coalescer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.643625000] 0x13164c720 Freeing Pass 'Register Coalescer' on Function 'main'...
+Running pass: Rename Disconnected Subregister Components
+[2025-06-18 00:57:04.643676000] 0x13164c720 Executing Pass 'Rename Disconnected Subregister Components' on Function 'main'...
+0x131651ae0 Required Analyses: Live Interval Analysis, Slot index numbering, Machine Module Information
+0x131651ae0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Live Interval Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Rename Disconnected Subregister Components' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.644209000] 0x13164c720 Freeing Pass 'Rename Disconnected Subregister Components' on Function 'main'...
+Running pass: Machine Instruction Scheduler
+[2025-06-18 00:57:04.644264000] 0x13164c720 Executing Pass 'Machine Instruction Scheduler' on Function 'main'...
+0x131652fd0 Required Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Function Alias Analysis Results, Target Pass Configuration, Slot index numbering, Live Interval Analysis, Machine Module Information
+[2025-06-18 00:57:04.644483000] 0x13164c720 Made Modification 'Machine Instruction Scheduler' on Function 'main'...
+0x131652fd0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Instruction Scheduler' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.644954000] 0x13164c720 Freeing Pass 'Machine Instruction Scheduler' on Function 'main'...
+Running pass: AArch64 Post Coalescer pass
+[2025-06-18 00:57:04.645005000] 0x13164c720 Executing Pass 'AArch64 Post Coalescer pass' on Function 'main'...
+0x131652e30 Required Analyses: Live Interval Analysis, Machine Module Information
+0x131652e30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Post Coalescer pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.645213000] 0x13164c720 Freeing Pass 'AArch64 Post Coalescer pass' on Function 'main'...
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:04.645265000] 0x13164c720 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x131652650 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x131652650 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Debug Variable Analysis
+[2025-06-18 00:57:04.645521000] 0x13164c720 Executing Pass 'Debug Variable Analysis' on Function 'main'...
+0x131652bf0 Required Analyses: MachineDominator Tree Construction, Live Interval Analysis, Machine Module Information
+0x131652bf0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Stack Slot Analysis
+[2025-06-18 00:57:04.645778000] 0x13164c720 Executing Pass 'Live Stack Slot Analysis' on Function 'main'...
+0x1316501f0 Required Analyses: Slot index numbering, Machine Module Information
+0x1316501f0 Preserved Analyses: Slot index numbering, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Virtual Register Map
+[2025-06-18 00:57:04.646013000] 0x13164c720 Executing Pass 'Virtual Register Map' on Function 'main'...
+0x131653090 Required Analyses: Machine Module Information
+0x131653090 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Register Matrix
+[2025-06-18 00:57:04.646210000] 0x13164c720 Executing Pass 'Live Register Matrix' on Function 'main'...
+0x131653150 Required Analyses: Live Interval Analysis, Virtual Register Map, Machine Module Information
+0x131653150 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Bundle Machine CFG Edges
+[2025-06-18 00:57:04.646458000] 0x13164c720 Executing Pass 'Bundle Machine CFG Edges' on Function 'main'...
+0x131653400 Required Analyses: Machine Module Information
+0x131653400 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Spill Code Placement Analysis
+[2025-06-18 00:57:04.646655000] 0x13164c720 Executing Pass 'Spill Code Placement Analysis' on Function 'main'...
+0x1316537c0 Required Analyses: Machine Block Frequency Analysis, Bundle Machine CFG Edges, Machine Module Information
+0x1316537c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.646885000] 0x13164c720 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x1316532d0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x1316532d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:04.647104000] 0x13164c720 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x131653290 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x131653290 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Greedy Register Allocator
+[2025-06-18 00:57:04.647308000] 0x13164c720 Executing Pass 'Greedy Register Allocator' on Function 'main'...
+0x1316518f0 Required Analyses: Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Virtual Register Map, Live Register Matrix, Bundle Machine CFG Edges, Spill Code Placement Analysis, Machine Optimization Remark Emitter, Regalloc eviction policy, Regalloc priority policy, Machine Module Information
+0x1316518f0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, Virtual Register Map, Live Register Matrix, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Greedy Register Allocator' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.648009000] 0x13164c720 Freeing Pass 'Greedy Register Allocator' on Function 'main'...
+[2025-06-18 00:57:04.648050000] 0x13164c720 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.648091000] 0x13164c720 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.648131000] 0x13164c720 Freeing Pass 'Bundle Machine CFG Edges' on Function 'main'...
+[2025-06-18 00:57:04.648172000] 0x13164c720 Freeing Pass 'Spill Code Placement Analysis' on Function 'main'...
+Running pass: Virtual Register Rewriter
+[2025-06-18 00:57:04.648223000] 0x13164c720 Executing Pass 'Virtual Register Rewriter' on Function 'main'...
+0x131653330 Required Analyses: Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, Virtual Register Map, Live Register Matrix, Machine Module Information
+[2025-06-18 00:57:04.648366000] 0x13164c720 Made Modification 'Virtual Register Rewriter' on Function 'main'...
+0x131653330 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Live Interval Analysis, Slot index numbering, Live Stack Slot Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'Virtual Register Rewriter' is not preserving 'Live Register Matrix'
+ -- 'Virtual Register Rewriter' is not preserving 'Debug Variable Analysis'
+ -- 'Virtual Register Rewriter' is not preserving 'Virtual Register Map'
+ -*- 'Virtual Register Rewriter' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.648925000] 0x13164c720 Freeing Pass 'Debug Variable Analysis' on Function 'main'...
+[2025-06-18 00:57:04.648966000] 0x13164c720 Freeing Pass 'Live Register Matrix' on Function 'main'...
+[2025-06-18 00:57:04.649008000] 0x13164c720 Freeing Pass 'Live Interval Analysis' on Function 'main'...
+[2025-06-18 00:57:04.649049000] 0x13164c720 Freeing Pass 'Virtual Register Map' on Function 'main'...
+[2025-06-18 00:57:04.649089000] 0x13164c720 Freeing Pass 'Virtual Register Rewriter' on Function 'main'...
+Running pass: Register Allocation Pass Scoring
+[2025-06-18 00:57:04.649140000] 0x13164c720 Executing Pass 'Register Allocation Pass Scoring' on Function 'main'...
+0x131653e80 Required Analyses: Regalloc eviction policy, Regalloc priority policy, Machine Block Frequency Analysis, Machine Module Information
+0x131653e80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Register Allocation Pass Scoring' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.649368000] 0x13164c720 Freeing Pass 'Register Allocation Pass Scoring' on Function 'main'...
+Running pass: Stack Slot Coloring
+[2025-06-18 00:57:04.649418000] 0x13164c720 Executing Pass 'Stack Slot Coloring' on Function 'main'...
+0x131653950 Required Analyses: Slot index numbering, Live Stack Slot Analysis, Machine Block Frequency Analysis, Machine Module Information
+0x131653950 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Slot index numbering, Live Interval Analysis, Debug Variable Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Slot Coloring' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.649959000] 0x13164c720 Freeing Pass 'Live Stack Slot Analysis' on Function 'main'...
+[2025-06-18 00:57:04.650000000] 0x13164c720 Freeing Pass 'Slot index numbering' on Function 'main'...
+[2025-06-18 00:57:04.650041000] 0x13164c720 Freeing Pass 'Stack Slot Coloring' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:57:04.650091000] 0x13164c720 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x131654200 Required Analyses: Machine Module Information
+0x131654200 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.650585000] 0x13164c720 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Machine Loop Invariant Code Motion
+[2025-06-18 00:57:04.650636000] 0x13164c720 Executing Pass 'Machine Loop Invariant Code Motion' on Function 'main'...
+0x131653a70 Required Analyses: Machine Natural Loop Construction, Machine Block Frequency Analysis, MachineDominator Tree Construction, Function Alias Analysis Results, Machine Module Information
+0x131653a70 Preserved Analyses: Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Loop Invariant Code Motion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.650905000] 0x13164c720 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:04.650958000] 0x13164c720 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.651004000] 0x13164c720 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.651045000] 0x13164c720 Freeing Pass 'Machine Loop Invariant Code Motion' on Function 'main'...
+Running pass: AArch64 Redundant Copy Elimination
+[2025-06-18 00:57:04.651095000] 0x13164c720 Executing Pass 'AArch64 Redundant Copy Elimination' on Function 'main'...
+0x131653b20 Required Analyses: Machine Module Information
+0x131653b20 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Redundant Copy Elimination' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.651315000] 0x13164c720 Freeing Pass 'AArch64 Redundant Copy Elimination' on Function 'main'...
+Running pass: A57 FP Anti-dependency breaker
+[2025-06-18 00:57:04.651368000] 0x13164c720 Executing Pass 'A57 FP Anti-dependency breaker' on Function 'main'...
+0x131654240 Required Analyses: Machine Module Information
+0x131654240 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'A57 FP Anti-dependency breaker' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.651835000] 0x13164c720 Freeing Pass 'A57 FP Anti-dependency breaker' on Function 'main'...
+Running pass: Remove Redundant DEBUG_VALUE analysis
+[2025-06-18 00:57:04.651887000] 0x13164c720 Executing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+0x131653990 Required Analyses: Machine Module Information
+0x131653990 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Redundant DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.652372000] 0x13164c720 Freeing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Fixup Statepoint Caller Saved
+[2025-06-18 00:57:04.652424000] 0x13164c720 Executing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+0x131653f20 Required Analyses: Machine Module Information
+0x131653f20 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Fixup Statepoint Caller Saved' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.652917000] 0x13164c720 Freeing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+Running pass: PostRA Machine Sink
+[2025-06-18 00:57:04.652968000] 0x13164c720 Executing Pass 'PostRA Machine Sink' on Function 'main'...
+0x131653f60 Required Analyses: Machine Module Information
+0x131653f60 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'PostRA Machine Sink' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.653449000] 0x13164c720 Freeing Pass 'PostRA Machine Sink' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:04.653502000] 0x13164c720 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x1316545a0 Required Analyses: Machine Module Information
+0x1316545a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:04.653699000] 0x13164c720 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x131654470 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x131654470 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:04.653922000] 0x13164c720 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x131654430 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x131654430 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:57:04.654143000] 0x13164c720 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x1316546a0 Required Analyses: Machine Module Information
+0x1316546a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.654341000] 0x13164c720 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x1316547e0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x1316547e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:04.654579000] 0x13164c720 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x1316543f0 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x1316543f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Shrink Wrapping analysis
+[2025-06-18 00:57:04.654807000] 0x13164c720 Executing Pass 'Shrink Wrapping analysis' on Function 'main'...
+0x131654050 Required Analyses: Machine Block Frequency Analysis, MachineDominator Tree Construction, MachinePostDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Module Information
+0x131654050 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Shrink Wrapping analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.655085000] 0x13164c720 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.655126000] 0x13164c720 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.655168000] 0x13164c720 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.655209000] 0x13164c720 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:04.655276000] 0x13164c720 Freeing Pass 'Shrink Wrapping analysis' on Function 'main'...
+Running pass: Prologue/Epilogue Insertion & Frame Finalization
+[2025-06-18 00:57:04.655329000] 0x13164c720 Executing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x131654780 Required Analyses: Machine Optimization Remark Emitter, Machine Module Information
+[2025-06-18 00:57:04.655823000] 0x13164c720 Made Modification 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x131654780 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Prologue/Epilogue Insertion & Frame Finalization' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.656271000] 0x13164c720 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.656314000] 0x13164c720 Freeing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+Running pass: Machine Late Instructions Cleanup Pass
+[2025-06-18 00:57:04.656366000] 0x13164c720 Executing Pass 'Machine Late Instructions Cleanup Pass' on Function 'main'...
+0x1316548e0 Required Analyses: Machine Module Information
+0x1316548e0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Late Instructions Cleanup Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.656837000] 0x13164c720 Freeing Pass 'Machine Late Instructions Cleanup Pass' on Function 'main'...
+Running pass: Control Flow Optimizer
+[2025-06-18 00:57:04.656889000] 0x13164c720 Executing Pass 'Control Flow Optimizer' on Function 'main'...
+0x131653cd0 Required Analyses: Machine Block Frequency Analysis, Machine Branch Probability Analysis, Profile summary info, Target Pass Configuration, Machine Module Information
+0x131653cd0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Control Flow Optimizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.657160000] 0x13164c720 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.657214000] 0x13164c720 Freeing Pass 'Control Flow Optimizer' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.657266000] 0x13164c720 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x131654f40 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x131654f40 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Tail Duplication
+[2025-06-18 00:57:04.657477000] 0x13164c720 Executing Pass 'Tail Duplication' on Function 'main'...
+0x131654e50 Required Analyses: Machine Branch Probability Analysis, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x131654e50 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Tail Duplication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.657710000] 0x13164c720 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.657751000] 0x13164c720 Freeing Pass 'Tail Duplication' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:57:04.657803000] 0x13164c720 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x131654980 Required Analyses: Machine Module Information
+0x131654980 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.658270000] 0x13164c720 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Post-RA pseudo instruction expansion pass
+[2025-06-18 00:57:04.658345000] 0x13164c720 Executing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+0x131654920 Required Analyses: Machine Module Information
+0x131654920 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Post-RA pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.658826000] 0x13164c720 Freeing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 pseudo instruction expansion pass
+[2025-06-18 00:57:04.658878000] 0x13164c720 Executing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x131654a20 Required Analyses: Machine Module Information
+[2025-06-18 00:57:04.659300000] 0x13164c720 Made Modification 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x131654a20 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.659481000] 0x13164c720 Freeing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 load / store optimization pass
+[2025-06-18 00:57:04.659532000] 0x13164c720 Executing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+0x131654a60 Required Analyses: Function Alias Analysis Results, Machine Module Information
+0x131654a60 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 load / store optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.659764000] 0x13164c720 Freeing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+Running pass: Insert KCFI indirect call checks
+[2025-06-18 00:57:04.659816000] 0x13164c720 Executing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+0x131654be0 Required Analyses: Machine Module Information
+0x131654be0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert KCFI indirect call checks' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.660030000] 0x13164c720 Freeing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+Running pass: AArch64 speculation hardening pass
+[2025-06-18 00:57:04.660081000] 0x13164c720 Executing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+0x131655040 Required Analyses: Machine Module Information
+0x131655040 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 speculation hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.660295000] 0x13164c720 Freeing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:04.660347000] 0x13164c720 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x131655300 Required Analyses: Machine Module Information
+0x131655300 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:04.660544000] 0x13164c720 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x1316551d0 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x1316551d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Falkor HW Prefetch Fix Late Phase
+[2025-06-18 00:57:04.660752000] 0x13164c720 Executing Pass 'Falkor HW Prefetch Fix Late Phase' on Function 'main'...
+0x131655130 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x131655130 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Falkor HW Prefetch Fix Late Phase' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.661225000] 0x13164c720 Freeing Pass 'Falkor HW Prefetch Fix Late Phase' on Function 'main'...
+Running pass: PostRA Machine Instruction Scheduler
+[2025-06-18 00:57:04.661298000] 0x13164c720 Executing Pass 'PostRA Machine Instruction Scheduler' on Function 'main'...
+0x1316553e0 Required Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Function Alias Analysis Results, Target Pass Configuration, Machine Module Information
+0x1316553e0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'PostRA Machine Instruction Scheduler' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.661808000] 0x13164c720 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.661850000] 0x13164c720 Freeing Pass 'PostRA Machine Instruction Scheduler' on Function 'main'...
+[2025-06-18 00:57:04.661891000] 0x13164c720 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:04.661932000] 0x13164c720 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:04.661973000] 0x13164c720 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Analyze Machine Code For Garbage Collection
+[2025-06-18 00:57:04.662025000] 0x13164c720 Executing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+0x1316555b0 Required Analyses: Machine Module Information, Create Garbage Collector Module Metadata
+0x1316555b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Analyze Machine Code For Garbage Collection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.662244000] 0x13164c720 Freeing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:04.662296000] 0x13164c720 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x1316556d0 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x1316556d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:57:04.662515000] 0x13164c720 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x131655810 Required Analyses: Machine Module Information
+0x131655810 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Branch Probability Basic Block Placement
+[2025-06-18 00:57:04.662727000] 0x13164c720 Executing Pass 'Branch Probability Basic Block Placement' on Function 'main'...
+0x131655600 Required Analyses: Machine Branch Probability Analysis, Machine Block Frequency Analysis, MachinePostDominator Tree Construction, Machine Natural Loop Construction, Profile summary info, Target Pass Configuration, Machine Module Information
+0x131655600 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch Probability Basic Block Placement' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.663005000] 0x13164c720 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.663046000] 0x13164c720 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:04.663088000] 0x13164c720 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:04.663129000] 0x13164c720 Freeing Pass 'Branch Probability Basic Block Placement' on Function 'main'...
+Running pass: Insert fentry calls
+[2025-06-18 00:57:04.663181000] 0x13164c720 Executing Pass 'Insert fentry calls' on Function 'main'...
+0x131655670 Required Analyses: Machine Module Information
+0x131655670 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert fentry calls' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.663383000] 0x13164c720 Freeing Pass 'Insert fentry calls' on Function 'main'...
+Running pass: Insert XRay ops
+[2025-06-18 00:57:04.663434000] 0x13164c720 Executing Pass 'Insert XRay ops' on Function 'main'...
+0x131655730 Required Analyses: Machine Module Information
+0x131655730 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert XRay ops' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.663905000] 0x13164c720 Freeing Pass 'Insert XRay ops' on Function 'main'...
+Running pass: Implement the 'patchable-function' attribute
+[2025-06-18 00:57:04.663972000] 0x13164c720 Executing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+0x131655ab0 Required Analyses: Machine Module Information
+0x131655ab0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Implement the 'patchable-function' attribute' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.664172000] 0x13164c720 Freeing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+Running pass: Workaround A53 erratum 835769 pass
+[2025-06-18 00:57:04.664223000] 0x13164c720 Executing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+0x131655af0 Required Analyses: Machine Module Information
+0x131655af0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Workaround A53 erratum 835769 pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.664687000] 0x13164c720 Freeing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+Running pass: AArch64 Collect Linker Optimization Hint (LOH)
+[2025-06-18 00:57:04.664738000] 0x13164c720 Executing Pass 'AArch64 Collect Linker Optimization Hint (LOH)' on Function 'main'...
+0x131655b80 Required Analyses: Machine Module Information
+0x131655b80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Collect Linker Optimization Hint (LOH)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.664937000] 0x13164c720 Freeing Pass 'AArch64 Collect Linker Optimization Hint (LOH)' on Function 'main'...
+Running pass: Contiguously Lay Out Funclets
+[2025-06-18 00:57:04.664988000] 0x13164c720 Executing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+0x131655bc0 Required Analyses: Machine Module Information
+0x131655bc0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Contiguously Lay Out Funclets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.665213000] 0x13164c720 Freeing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+Running pass: Remove Loads Into Fake Uses
+[2025-06-18 00:57:04.665265000] 0x13164c720 Executing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+0x131655c30 Required Analyses: Machine Module Information
+0x131655c30 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Loads Into Fake Uses' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.665729000] 0x13164c720 Freeing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+Running pass: StackMap Liveness Analysis
+[2025-06-18 00:57:04.665780000] 0x13164c720 Executing Pass 'StackMap Liveness Analysis' on Function 'main'...
+0x131655c90 Required Analyses: Machine Module Information
+0x131655c90 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'StackMap Liveness Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.666258000] 0x13164c720 Freeing Pass 'StackMap Liveness Analysis' on Function 'main'...
+Running pass: Live DEBUG_VALUE analysis
+[2025-06-18 00:57:04.666312000] 0x13164c720 Executing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+0x1316561f0 Required Analyses: Target Pass Configuration, Machine Module Information
+0x1316561f0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Live DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.668305000] 0x13164c720 Freeing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Machine Sanitizer Binary Metadata
+[2025-06-18 00:57:04.668357000] 0x13164c720 Executing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+0x131656250 Required Analyses: Machine Module Information
+0x131656250 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Sanitizer Binary Metadata' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.668558000] 0x13164c720 Freeing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+[2025-06-18 00:57:04.668600000] 0x1316457f0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.668657000] 0x1316457f0 Freeing Pass 'Target Pass Configuration' on Module 'test.c'...
+[2025-06-18 00:57:04.668698000] 0x1316457f0 Freeing Pass 'Profile summary info' on Module 'test.c'...
+[2025-06-18 00:57:04.668741000] 0x1316457f0 Freeing Pass 'Assumption Cache Tracker' on Module 'test.c'...
+[2025-06-18 00:57:04.668784000] 0x1316457f0 Freeing Pass 'Target Library Information' on Module 'test.c'...
+[2025-06-18 00:57:04.668826000] 0x1316457f0 Freeing Pass 'Type-Based Alias Analysis' on Module 'test.c'...
+[2025-06-18 00:57:04.668868000] 0x1316457f0 Freeing Pass 'Default Regalloc Priority Advisor' on Module 'test.c'...
+[2025-06-18 00:57:04.668910000] 0x1316457f0 Freeing Pass 'Default Regalloc Eviction Advisor' on Module 'test.c'...
+[2025-06-18 00:57:04.668952000] 0x1316457f0 Freeing Pass 'Scoped NoAlias Alias Analysis' on Module 'test.c'...
+Running pass: Machine Outliner
+[2025-06-18 00:57:04.669005000] 0x1316457f0 Executing Pass 'Machine Outliner' on Module 'test.c'...
+0x131656410 Required Analyses: Machine Module Information
+0x131656410 Preserved Analyses: Machine Module Information
+0x131656410 Used Analyses: Module summary info
+ -*- 'Machine Outliner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.669184000] 0x1316457f0 Freeing Pass 'Machine Outliner' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:04.669237000] 0x1316457f0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: AArch64 sls hardening pass
+[2025-06-18 00:57:04.669289000] 0x131655ea0 Executing Pass 'AArch64 sls hardening pass' on Function 'main'...
+0x131655d30 Required Analyses: Machine Module Information
+0x131655d30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 sls hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.669507000] 0x131655ea0 Freeing Pass 'AArch64 sls hardening pass' on Function 'main'...
+Running pass: AArch64 Pointer Authentication
+[2025-06-18 00:57:04.669559000] 0x131655ea0 Executing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+0x131656040 Required Analyses: Machine Module Information
+0x131656040 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Pointer Authentication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.669768000] 0x131655ea0 Freeing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+Running pass: AArch64 Branch Targets
+[2025-06-18 00:57:04.669821000] 0x131655ea0 Executing Pass 'AArch64 Branch Targets' on Function 'main'...
+0x1316564e0 Required Analyses: Machine Module Information
+0x1316564e0 Preserved Analyses: Assign reference type allocas to local address space, Spill Code Placement Analysis, SPIRV convergence regions analysis, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Machine Block Frequency Analysis, Print Machine Uniformity Info Analysis, Lazy Machine Block Frequency Analysis, Uniformity Analysis, Bundle Machine CFG Edges, Post-Dominator Tree Construction, Block Frequency Analysis, Basic Alias Analysis (stateless AA impl), Analysis if a function is memory bound, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Function register usage analysis, , Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Machine Dominance Frontier Construction, Machine Natural Loop Construction, Machine Cycle Info Analysis, MachineDominator Tree Construction, Machine Optimization Remark Emitter, Detect single entry single exit regions, Dominator Tree Construction, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Branch Targets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.670285000] 0x131655ea0 Freeing Pass 'AArch64 Branch Targets' on Function 'main'...
+Running pass: Branch relaxation pass
+[2025-06-18 00:57:04.670336000] 0x131655ea0 Executing Pass 'Branch relaxation pass' on Function 'main'...
+0x131656540 Required Analyses: Machine Module Information
+0x131656540 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch relaxation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.670538000] 0x131655ea0 Freeing Pass 'Branch relaxation pass' on Function 'main'...
+Running pass: AArch64 Compress Jump Tables
+[2025-06-18 00:57:04.670589000] 0x131655ea0 Executing Pass 'AArch64 Compress Jump Tables' on Function 'main'...
+0x131656600 Required Analyses: Machine Module Information
+0x131656600 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Compress Jump Tables' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.670815000] 0x131655ea0 Freeing Pass 'AArch64 Compress Jump Tables' on Function 'main'...
+Running pass: Insert CFI remember/restore state instructions
+[2025-06-18 00:57:04.670868000] 0x131655ea0 Executing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+0x1316565a0 Required Analyses: Machine Module Information
+0x1316565a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert CFI remember/restore state instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.671089000] 0x131655ea0 Freeing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.671140000] 0x131655ea0 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x131656760 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x131656760 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:04.671346000] 0x131655ea0 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x131656720 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x131656720 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Stack Frame Layout Analysis
+[2025-06-18 00:57:04.671551000] 0x131655ea0 Executing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+0x131656680 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter
+0x131656680 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Frame Layout Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.671776000] 0x131655ea0 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.671818000] 0x131655ea0 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.671860000] 0x131655ea0 Freeing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+Running pass: Unpack machine instruction bundles
+[2025-06-18 00:57:04.671911000] 0x131655ea0 Executing Pass 'Unpack machine instruction bundles' on Function 'main'...
+0x1316566c0 Required Analyses: Machine Module Information
+0x1316566c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Unpack machine instruction bundles' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.672127000] 0x131655ea0 Freeing Pass 'Unpack machine instruction bundles' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:04.672179000] 0x131655ea0 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x131656910 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x131656910 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:04.672384000] 0x131655ea0 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x131656970 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x131656970 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Assembly Printer
+[2025-06-18 00:57:04.672590000] 0x131655ea0 Executing Pass 'AArch64 Assembly Printer' on Function 'main'...
+0x131716880 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter, Create Garbage Collector Module Metadata, Lazy Machine Block Frequency Analysis, Machine Branch Probability Analysis
+0x131716880 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Assembly Printer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.674639000] 0x131655ea0 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:04.674682000] 0x131655ea0 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:04.674723000] 0x131655ea0 Freeing Pass 'AArch64 Assembly Printer' on Function 'main'...
+Running pass: Free MachineFunction
+[2025-06-18 00:57:04.674774000] 0x131655ea0 Executing Pass 'Free MachineFunction' on Function 'main'...
+0x131656a50 Required Analyses: Machine Module Information
+[2025-06-18 00:57:04.674844000] 0x131655ea0 Made Modification 'Free MachineFunction' on Function 'main'...
+0x131656a50 Preserved Analyses: Machine Module Information
+ -- 'Free MachineFunction' is not preserving 'Function Pass Manager'
+ -*- 'Free MachineFunction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.674939000] 0x131655ea0 Freeing Pass 'Free MachineFunction' on Function 'main'...
+[2025-06-18 00:57:04.674981000] 0x1316457f0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:04.675036000] 0x1316457f0 Freeing Pass 'Create Garbage Collector Module Metadata' on Module 'test.c'...
+[2025-06-18 00:57:04.675079000] 0x1316457f0 Freeing Pass 'Machine Branch Probability Analysis' on Module 'test.c'...
+[2025-06-18 00:57:04.675120000] 0x1316457f0 Freeing Pass 'Machine Module Information' on Module 'test.c'...
+ld: library not found for -lSystem
+clang: error: linker command failed with exit code 1 (use -v to see invocation)
diff --git a/optimization_3_new.txt b/optimization_3_new.txt
new file mode 100644
index 0000000000000..5b29b14f16b0d
--- /dev/null
+++ b/optimization_3_new.txt
@@ -0,0 +1,1867 @@
+ -- 'Expand large div/rem' is not preserving 'Pre-ISel Intrinsic Lowering'
+ -- 'Expand large div/rem' is not preserving 'Function Pass Manager'
+ -- 'Expand fp' is not preserving 'Expand large div/rem'
+ -- 'Expand Atomic instructions' is not preserving 'Expand fp'
+ -- 'Simplify the CFG' is not preserving 'SVE intrinsics optimizations'
+ -- 'Simplify the CFG' is not preserving 'Function Pass Manager'
+ -- 'Canonicalize natural loops' is not preserving 'Simplify the CFG'
+ -- 'Loop Data Prefetch' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Loop Data Prefetch' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Loop Data Prefetch' is not preserving 'Optimization Remark Emitter'
+ -- 'Falkor HW Prefetch Fix' is not preserving 'Canonicalize natural loops'
+ -- 'Falkor HW Prefetch Fix' is not preserving 'Loop Data Prefetch'
+ -- 'Canonicalize natural loops' is not preserving 'Falkor HW Prefetch Fix'
+ -- 'Canonicalize Freeze Instructions in Loops' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Canonicalize Freeze Instructions in Loops' is not preserving 'Loop Pass Manager'
+ -- 'Loop Strength Reduction' is not preserving 'Canonicalize Freeze Instructions in Loops'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Function Alias Analysis Results'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Natural Loop Information'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Scalar Evolution Analysis'
+ -- 'Merge contiguous icmps into a memcmp' is not preserving 'Canonicalize natural loops'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Merge contiguous icmps into a memcmp'
+ -- 'Expand memcmp() to load/stores' is not preserving 'Natural Loop Information'
+ -- 'Lower Garbage Collection Instructions' is not preserving 'Expand memcmp() to load/stores'
+ -- 'Shadow Stack GC Lowering' is not preserving 'Lower Garbage Collection Instructions'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Lower @llvm.global_dtors via `__cxa_atexit`'
+ -- 'Remove unreachable blocks from the CFG' is not preserving 'Function Pass Manager'
+ -- 'Constant Hoisting' is not preserving 'Branch Probability Analysis'
+ -- 'Constant Hoisting' is not preserving 'Remove unreachable blocks from the CFG'
+ -- 'Replace intrinsics with calls to vector library' is not preserving 'Constant Hoisting'
+ -- 'Partially inline calls to library functions' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Post-Dominator Tree Construction'
+ -- 'Partially inline calls to library functions' is not preserving 'Optimization Remark Emitter'
+ -- 'Partially inline calls to library functions' is not preserving 'Natural Loop Information'
+ -- 'Partially inline calls to library functions' is not preserving 'Block Frequency Analysis'
+ -- 'Partially inline calls to library functions' is not preserving 'Replace intrinsics with calls to vector library'
+ -- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is not preserving 'Partially inline calls to library functions'
+ -- 'Scalarize Masked Memory Intrinsics' is not preserving 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)'
+ -- 'Expand reduction intrinsics' is not preserving 'Scalarize Masked Memory Intrinsics'
+ -- 'Optimize selects' is not preserving 'Expand reduction intrinsics'
+ -- 'Optimize selects' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Optimize selects' is not preserving 'Post-Dominator Tree Construction'
+ -- 'Optimize selects' is not preserving 'Branch Probability Analysis'
+ -- 'Optimize selects' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Optimize selects' is not preserving 'Optimization Remark Emitter'
+ -- 'Optimize selects' is not preserving 'Natural Loop Information'
+ -- 'Optimize selects' is not preserving 'Block Frequency Analysis'
+ -- 'Optimize selects' is not preserving 'Dominator Tree Construction'
+ -- 'AArch64 Stack Tagging' is not preserving 'Function Alias Analysis Results'
+ -- 'AArch64 Stack Tagging' is not preserving 'Optimization Remark Emitter'
+ -- 'AArch64 Stack Tagging' is not preserving 'Stack Safety Analysis'
+ -- 'AArch64 Stack Tagging' is not preserving 'Function Pass Manager'
+ -- 'Complex Deinterleaving Pass' is not preserving 'AArch64 Stack Tagging'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Function Alias Analysis Results'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Memory SSA'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Complex Deinterleaving Pass'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Natural Loop Information'
+ -- 'Interleaved Load Combine Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Interleaved Access Pass' is not preserving 'Interleaved Load Combine Pass'
+ -- 'SME ABI Pass' is not preserving 'Interleaved Access Pass'
+ -- 'SME ABI Pass' is not preserving 'Dominator Tree Construction'
+ -- 'Type Promotion' is not preserving 'SME ABI Pass'
+ -- 'CodeGen Prepare' is not preserving 'Natural Loop Information'
+ -- 'CodeGen Prepare' is not preserving 'Type Promotion'
+ -- 'CodeGen Prepare' is not preserving 'Dominator Tree Construction'
+ -- 'Exception handling preparation' is not preserving 'CodeGen Prepare'
+ -- 'Merge internal globals' is not preserving 'AArch64 Promote Constant'
+ -- 'Merge internal globals' is not preserving 'Function Pass Manager'
+ -- 'ObjC ARC contraction' is not preserving 'Merge internal globals'
+ -- 'Prepare callbr' is not preserving 'Function Alias Analysis Results'
+ -- 'Prepare callbr' is not preserving 'Basic Alias Analysis (stateless AA impl)'
+ -- 'Prepare callbr' is not preserving 'ObjC ARC contraction'
+ -- 'Safe Stack instrumentation pass' is not preserving 'Prepare callbr'
+ -- 'Insert stack protectors' is not preserving 'Safe Stack instrumentation pass'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Post-Dominator Tree Construction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'Assignment Tracking Analysis'
+ -- 'Finalize ISel and expand pseudo-instructions' is not preserving 'AArch64 Instruction Selection'
+ -- 'SME Peephole Optimization pass' is not preserving 'Finalize ISel and expand pseudo-instructions'
+ -- 'Early Tail Duplication' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Early Tail Duplication' is not preserving 'SME Peephole Optimization pass'
+ -- 'Optimize machine instruction PHIs' is not preserving 'Early Tail Duplication'
+ -- 'Merge disjoint stack slots' is not preserving 'Slot index numbering'
+ -- 'Merge disjoint stack slots' is not preserving 'Optimize machine instruction PHIs'
+ -- 'Local Stack Slot Allocation' is not preserving 'Merge disjoint stack slots'
+ -- 'Remove dead machine instructions' is not preserving 'Local Stack Slot Allocation'
+ -- 'AArch64 Condition Optimizer' is not preserving 'Remove dead machine instructions'
+ -- 'AArch64 Conditional Compares' is not preserving 'AArch64 Condition Optimizer'
+ -- 'Machine InstCombiner' is not preserving 'AArch64 Conditional Compares'
+ -- 'AArch64 Conditional Branch Tuning' is not preserving 'Machine InstCombiner'
+ -- 'AArch64 Conditional Branch Tuning' is not preserving 'Machine Trace Metrics'
+ -- 'Early If-Conversion' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Early If-Conversion' is not preserving 'AArch64 Conditional Branch Tuning'
+ -- 'AArch64 Store Pair Suppression' is not preserving 'Early If-Conversion'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'MachineDominator Tree Construction'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'Machine Natural Loop Construction'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'Machine Trace Metrics'
+ -- 'AArch64 SIMD instructions optimization pass' is not preserving 'AArch64 Store Pair Suppression'
+ -- 'AArch64 Stack Tagging PreRA' is not preserving 'AArch64 SIMD instructions optimization pass'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'AArch64 Stack Tagging PreRA'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'MachineDominator Tree Construction'
+ -- 'Early Machine Loop Invariant Code Motion' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine Common Subexpression Elimination' is not preserving 'Early Machine Loop Invariant Code Motion'
+ -- 'Machine code sinking' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'Machine Common Subexpression Elimination'
+ -- 'Machine code sinking' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine code sinking' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Peephole Optimizations' is not preserving 'Machine code sinking'
+ -- 'Remove dead machine instructions' is not preserving 'Peephole Optimizations'
+ -- 'AArch64 MI Peephole Optimization pass' is not preserving 'Remove dead machine instructions'
+ -- 'AArch64 Dead register definitions' is not preserving 'AArch64 MI Peephole Optimization pass'
+ -- 'Detect Dead Lanes' is not preserving 'AArch64 Dead register definitions'
+ -- 'Init Undef Pass' is not preserving 'Detect Dead Lanes'
+ -- 'Process Implicit Definitions' is not preserving 'Init Undef Pass'
+ -- 'Remove unreachable machine basic blocks' is not preserving 'Machine Cycle Info Analysis'
+ -- 'Remove unreachable machine basic blocks' is not preserving 'Process Implicit Definitions'
+ -- 'Eliminate PHI nodes for register allocation' is not preserving 'Remove unreachable machine basic blocks'
+ -- 'Two-Address instruction pass' is not preserving 'Eliminate PHI nodes for register allocation'
+ -- 'Live Interval Analysis' is not preserving 'Two-Address instruction pass'
+ -- 'Register Coalescer' is not preserving 'Live Variable Analysis'
+ -- 'Rename Disconnected Subregister Components' is not preserving 'Register Coalescer'
+ -- 'Machine Instruction Scheduler' is not preserving 'Rename Disconnected Subregister Components'
+ -- 'Greedy Register Allocator' is not preserving 'AArch64 Post Coalescer pass'
+ -- 'Greedy Register Allocator' is not preserving 'Machine Instruction Scheduler'
+ -- 'Virtual Register Rewriter' is not preserving 'Live Register Matrix'
+ -- 'Virtual Register Rewriter' is not preserving 'Debug Variable Analysis'
+ -- 'Virtual Register Rewriter' is not preserving 'Virtual Register Map'
+ -- 'Virtual Register Rewriter' is not preserving 'Greedy Register Allocator'
+ -- 'Stack Slot Coloring' is not preserving 'Live Stack Slot Analysis'
+ -- 'Stack Slot Coloring' is not preserving 'Virtual Register Rewriter'
+ -- 'Stack Slot Coloring' is not preserving 'Register Allocation Pass Scoring'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Live Interval Analysis'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Slot index numbering'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Stack Slot Coloring'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Copy Propagation Pass'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Spill Code Placement Analysis'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Bundle Machine CFG Edges'
+ -- 'Machine Loop Invariant Code Motion' is not preserving 'Machine Block Frequency Analysis'
+ -- 'AArch64 Redundant Copy Elimination' is not preserving 'Machine Natural Loop Construction'
+ -- 'AArch64 Redundant Copy Elimination' is not preserving 'Machine Loop Invariant Code Motion'
+ -- 'A57 FP Anti-dependency breaker' is not preserving 'AArch64 Redundant Copy Elimination'
+ -- 'Remove Redundant DEBUG_VALUE analysis' is not preserving 'A57 FP Anti-dependency breaker'
+ -- 'Fixup Statepoint Caller Saved' is not preserving 'Remove Redundant DEBUG_VALUE analysis'
+ -- 'PostRA Machine Sink' is not preserving 'Fixup Statepoint Caller Saved'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'Shrink Wrapping analysis'
+ -- 'Prologue/Epilogue Insertion & Frame Finalization' is not preserving 'PostRA Machine Sink'
+ -- 'Machine Late Instructions Cleanup Pass' is not preserving 'Prologue/Epilogue Insertion & Frame Finalization'
+ -- 'Control Flow Optimizer' is not preserving 'MachineDominator Tree Construction'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Natural Loop Construction'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Control Flow Optimizer' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Late Instructions Cleanup Pass'
+ -- 'Control Flow Optimizer' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Control Flow Optimizer' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Tail Duplication' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Tail Duplication' is not preserving 'Control Flow Optimizer'
+ -- 'Machine Copy Propagation Pass' is not preserving 'Tail Duplication'
+ -- 'Post-RA pseudo instruction expansion pass' is not preserving 'Machine Copy Propagation Pass'
+ -- 'AArch64 pseudo instruction expansion pass' is not preserving 'Post-RA pseudo instruction expansion pass'
+ -- 'AArch64 load / store optimization pass' is not preserving 'AArch64 pseudo instruction expansion pass'
+ -- 'Insert KCFI indirect call checks' is not preserving 'AArch64 load / store optimization pass'
+ -- 'AArch64 speculation hardening pass' is not preserving 'Insert KCFI indirect call checks'
+ -- 'Falkor HW Prefetch Fix Late Phase' is not preserving 'AArch64 speculation hardening pass'
+ -- 'PostRA Machine Instruction Scheduler' is not preserving 'Falkor HW Prefetch Fix Late Phase'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'MachineDominator Tree Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Machine Natural Loop Construction'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Analyze Machine Code For Garbage Collection'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'PostRA Machine Instruction Scheduler'
+ -- 'Branch Probability Basic Block Placement' is not preserving 'MachinePostDominator Tree Construction'
+ -- 'Insert fentry calls' is not preserving 'Branch Probability Basic Block Placement'
+ -- 'Insert XRay ops' is not preserving 'Insert fentry calls'
+ -- 'Implement the 'patchable-function' attribute' is not preserving 'Insert XRay ops'
+ -- 'AArch64 load / store optimization pass' is not preserving 'Implement the 'patchable-function' attribute'
+ -- 'Machine Copy Propagation Pass' is not preserving 'AArch64 load / store optimization pass'
+ -- 'Workaround A53 erratum 835769 pass' is not preserving 'Machine Copy Propagation Pass'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'Workaround A53 erratum 835769 pass'
+ -- 'Contiguously Lay Out Funclets' is not preserving 'AArch64 Collect Linker Optimization Hint (LOH)'
+ -- 'Remove Loads Into Fake Uses' is not preserving 'Contiguously Lay Out Funclets'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'StackMap Liveness Analysis'
+ -- 'Live DEBUG_VALUE analysis' is not preserving 'Remove Loads Into Fake Uses'
+ -- 'Machine Sanitizer Binary Metadata' is not preserving 'Live DEBUG_VALUE analysis'
+ -- 'AArch64 sls hardening pass' is not preserving 'Machine Outliner'
+ -- 'AArch64 sls hardening pass' is not preserving 'Function Pass Manager'
+ -- 'AArch64 Pointer Authentication' is not preserving 'AArch64 sls hardening pass'
+ -- 'AArch64 Branch Targets' is not preserving 'AArch64 Pointer Authentication'
+ -- 'Branch relaxation pass' is not preserving 'AArch64 Branch Targets'
+ -- 'AArch64 Compress Jump Tables' is not preserving 'Branch relaxation pass'
+ -- 'Unpack machine instruction bundles' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Unpack machine instruction bundles' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Stack Frame Layout Analysis'
+ -- 'Unpack machine instruction bundles' is not preserving 'Insert CFI remember/restore state instructions'
+ -- 'Unpack machine instruction bundles' is not preserving 'AArch64 Compress Jump Tables'
+ -- 'Free MachineFunction' is not preserving 'Machine Optimization Remark Emitter'
+ -- 'Free MachineFunction' is not preserving 'Lazy Machine Block Frequency Analysis'
+ -- 'Free MachineFunction' is not preserving 'AArch64 Assembly Printer'
+ -- 'Free MachineFunction' is not preserving 'Unpack machine instruction bundles'
+Pass Arguments: -tti -targetlibinfo -targetpassconfig -machinemoduleinfo -assumption-cache-tracker -profile-summary-info -tbaa -scoped-noalias-aa -collector-metadata -machine-branch-prob -regalloc-evict -regalloc-priority -pre-isel-intrinsic-lowering -expand-large-div-rem -expand-fp -atomic-expand -aarch64-sve-intrinsic-opts -simplifycfg -domtree -loops -loop-simplify -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -scalar-evolution -loop-data-prefetch -aarch64-falkor-hwpf-fix -basic-aa -loop-simplify -canon-freeze -iv-users -loop-reduce -basic-aa -aa -mergeicmps -loops -lazy-branch-prob -lazy-block-freq -expand-memcmp -gc-lowering -shadow-stack-gc-lowering -lower-global-dtors -unreachableblockelim -domtree -loops -postdomtree -branch-prob -block-freq -consthoist -replace-with-veclib -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -partially-inline-libcalls -post-inline-ee-instrument -scalarize-masked-mem-intrin -expand-reductions -loops -postdomtree -branch-prob -block-freq -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -select-optimize -stack-safety -domtree -basic-aa -aa -loops -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -aarch64-stack-tagging -complex-deinterleaving -aa -memoryssa -interleaved-load-combine -domtree -interleaved-access -aarch64-sme-abi -domtree -loops -type-promotion -codegenprepare -domtree -dwarf-eh-prepare -aarch64-promote-const -global-merge -domtree -basic-aa -aa -objc-arc-contract -callbrprepare -safe-stack -stack-protector -basic-aa -aa -loops -postdomtree -branch-prob -debug-ata -lazy-branch-prob -lazy-block-freq -aarch64-isel -finalize-isel -aarch64-sme-peephole-opt -lazy-machine-block-freq -early-tailduplication -opt-phis -slotindexes -stack-coloring -localstackalloc -dead-mi-elimination -machinedomtree -aarch64-condopt -machine-loops -machine-trace-metrics -aarch64-ccmp -lazy-machine-block-freq -machine-combiner -aarch64-cond-br-tuning -machine-trace-metrics -early-ifcvt -aarch64-stp-suppress -aarch64-simdinstr-opt -aarch64-stack-tagging-pre-ra -machinedomtree -machine-loops -machine-block-freq -early-machinelicm -machinedomtree -machine-block-freq -machine-cse -machinepostdomtree -machine-cycles -machine-sink -peephole-opt -dead-mi-elimination -aarch64-mi-peephole-opt -aarch64-dead-defs -detect-dead-lanes -init-undef -processimpdefs -unreachable-mbb-elimination -livevars -phi-node-elimination -twoaddressinstruction -machinedomtree -slotindexes -liveintervals -register-coalescer -rename-independent-subregs -machine-scheduler -aarch64-post-coalescer-pass -machine-block-freq -livedebugvars -livestacks -virtregmap -liveregmatrix -edge-bundles -spill-code-placement -lazy-machine-block-freq -machine-opt-remark-emitter -greedy -virtregrewriter -regallocscoringpass -stack-slot-coloring -machine-cp -machinelicm -aarch64-copyelim -aarch64-a57-fp-load-balancing -removeredundantdebugvalues -fixup-statepoint-caller-saved -postra-machine-sink -machinedomtree -machine-loops -machine-block-freq -machinepostdomtree -lazy-machine-block-freq -machine-opt-remark-emitter -shrink-wrap -prologepilog -machine-latecleanup -branch-folder -lazy-machine-block-freq -tailduplication -machine-cp -postrapseudos -aarch64-expand-pseudo -aarch64-ldst-opt -kcfi -aarch64-speculation-hardening -machinedomtree -machine-loops -aarch64-falkor-hwpf-fix-late -postmisched -gc-analysis -machine-block-freq -machinepostdomtree -block-placement -fentry-insert -xray-instrumentation -patchable-function -aarch64-ldst-opt -machine-cp -aarch64-fix-cortex-a53-835769-pass -aarch64-collect-loh -funclet-layout -remove-loads-into-fake-uses -stackmap-liveness -livedebugvalues -machine-sanmd -machine-outliner -aarch64-sls-hardening -aarch64-ptrauth -aarch64-branch-targets -branch-relaxation -aarch64-jump-tables -cfi-fixup -lazy-machine-block-freq -machine-opt-remark-emitter -stack-frame-layout -unpack-mi-bundles -lazy-machine-block-freq -machine-opt-remark-emitter -aarch64-asm-printer
+Target Transform Information
+Target Library Information
+Target Pass Configuration
+Machine Module Information
+Assumption Cache Tracker
+Profile summary info
+Type-Based Alias Analysis
+Scoped NoAlias Alias Analysis
+Create Garbage Collector Module Metadata
+Machine Branch Probability Analysis
+Default Regalloc Eviction Advisor
+Default Regalloc Priority Advisor
+ ModulePass Manager
+ Pre-ISel Intrinsic Lowering
+-- Pre-ISel Intrinsic Lowering
+ FunctionPass Manager
+ Expand large div/rem
+-- Expand large div/rem
+ Expand fp
+-- Expand fp
+ Expand Atomic instructions
+-- Expand Atomic instructions
+ SVE intrinsics optimizations
+ FunctionPass Manager
+ Dominator Tree Construction
+-- SVE intrinsics optimizations
+ FunctionPass Manager
+ Simplify the CFG
+-- Simplify the CFG
+ Dominator Tree Construction
+ Natural Loop Information
+ Canonicalize natural loops
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Scalar Evolution Analysis
+ Loop Data Prefetch
+-- Loop Data Prefetch
+-- Lazy Block Frequency Analysis
+-- Canonicalize natural loops
+-- Optimization Remark Emitter
+-- Lazy Branch Probability Analysis
+ Falkor HW Prefetch Fix
+-- Falkor HW Prefetch Fix
+ Basic Alias Analysis (stateless AA impl)
+-- Basic Alias Analysis (stateless AA impl)
+ Canonicalize natural loops
+ Loop Pass Manager
+ Canonicalize Freeze Instructions in Loops
+-- Canonicalize Freeze Instructions in Loops
+ Induction Variable Users
+ Loop Strength Reduction
+-- Induction Variable Users
+-- Loop Strength Reduction
+-- Natural Loop Information
+-- Scalar Evolution Analysis
+-- Canonicalize natural loops
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Merge contiguous icmps into a memcmp
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- Merge contiguous icmps into a memcmp
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Expand memcmp() to load/stores
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Dominator Tree Construction
+-- Expand memcmp() to load/stores
+ Lower Garbage Collection Instructions
+-- Lower Garbage Collection Instructions
+ Shadow Stack GC Lowering
+-- Shadow Stack GC Lowering
+ Lower @llvm.global_dtors via `__cxa_atexit`
+-- Lower @llvm.global_dtors via `__cxa_atexit`
+ FunctionPass Manager
+ Remove unreachable blocks from the CFG
+-- Remove unreachable blocks from the CFG
+ Dominator Tree Construction
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Block Frequency Analysis
+ Constant Hoisting
+-- Block Frequency Analysis
+-- Branch Probability Analysis
+-- Post-Dominator Tree Construction
+-- Constant Hoisting
+ Replace intrinsics with calls to vector library
+-- Replace intrinsics with calls to vector library
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Partially inline calls to library functions
+-- Optimization Remark Emitter
+-- Lazy Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Partially inline calls to library functions
+ Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+-- Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+ Scalarize Masked Memory Intrinsics
+-- Scalarize Masked Memory Intrinsics
+ Expand reduction intrinsics
+-- Expand reduction intrinsics
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Block Frequency Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ Optimize selects
+-- Dominator Tree Construction
+-- Lazy Block Frequency Analysis
+-- Optimize selects
+-- Block Frequency Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Optimization Remark Emitter
+-- Branch Probability Analysis
+-- Post-Dominator Tree Construction
+ Stack Safety Analysis
+ FunctionPass Manager
+ Dominator Tree Construction
+ Natural Loop Information
+ Scalar Evolution Analysis
+ Stack Safety Local Analysis
+ FunctionPass Manager
+ Dominator Tree Construction
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ AArch64 Stack Tagging
+-- Function Alias Analysis Results
+-- AArch64 Stack Tagging
+-- Lazy Block Frequency Analysis
+-- Optimization Remark Emitter
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+ Complex Deinterleaving Pass
+-- Complex Deinterleaving Pass
+ Function Alias Analysis Results
+ Memory SSA
+ Interleaved Load Combine Pass
+-- Memory SSA
+-- Basic Alias Analysis (stateless AA impl)
+-- Function Alias Analysis Results
+-- Dominator Tree Construction
+-- Interleaved Load Combine Pass
+ Dominator Tree Construction
+ Interleaved Access Pass
+-- Dominator Tree Construction
+-- Interleaved Access Pass
+ SME ABI Pass
+-- SME ABI Pass
+ Dominator Tree Construction
+ Natural Loop Information
+ Type Promotion
+-- Type Promotion
+ CodeGen Prepare
+-- Natural Loop Information
+-- Dominator Tree Construction
+-- CodeGen Prepare
+ Dominator Tree Construction
+ Exception handling preparation
+-- Dominator Tree Construction
+-- Exception handling preparation
+-- Target Transform Information
+-- Stack Safety Analysis
+ AArch64 Promote Constant
+ FunctionPass Manager
+ Dominator Tree Construction
+-- AArch64 Promote Constant
+ FunctionPass Manager
+ Merge internal globals
+-- Merge internal globals
+ Dominator Tree Construction
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ ObjC ARC contraction
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- ObjC ARC contraction
+ Prepare callbr
+-- Prepare callbr
+ Safe Stack instrumentation pass
+-- Safe Stack instrumentation pass
+ Insert stack protectors
+ Basic Alias Analysis (stateless AA impl)
+ Function Alias Analysis Results
+ Natural Loop Information
+ Post-Dominator Tree Construction
+ Branch Probability Analysis
+ Assignment Tracking Analysis
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ AArch64 Instruction Selection
+-- Assignment Tracking Analysis
+-- Natural Loop Information
+-- Lazy Branch Probability Analysis
+-- Lazy Block Frequency Analysis
+-- AArch64 Instruction Selection
+-- Insert stack protectors
+-- Branch Probability Analysis
+-- Post-Dominator Tree Construction
+ Finalize ISel and expand pseudo-instructions
+-- Finalize ISel and expand pseudo-instructions
+ SME Peephole Optimization pass
+-- SME Peephole Optimization pass
+ Lazy Machine Block Frequency Analysis
+ Early Tail Duplication
+-- Lazy Machine Block Frequency Analysis
+-- Early Tail Duplication
+ Optimize machine instruction PHIs
+-- Optimize machine instruction PHIs
+ Slot index numbering
+ Merge disjoint stack slots
+-- Slot index numbering
+-- Merge disjoint stack slots
+ Local Stack Slot Allocation
+-- Local Stack Slot Allocation
+ Remove dead machine instructions
+-- Remove dead machine instructions
+ MachineDominator Tree Construction
+ AArch64 Condition Optimizer
+-- AArch64 Condition Optimizer
+ Machine Natural Loop Construction
+ Machine Trace Metrics
+ AArch64 Conditional Compares
+-- AArch64 Conditional Compares
+ Lazy Machine Block Frequency Analysis
+ Machine InstCombiner
+-- Machine InstCombiner
+-- Machine Trace Metrics
+-- Lazy Machine Block Frequency Analysis
+ AArch64 Conditional Branch Tuning
+-- AArch64 Conditional Branch Tuning
+ Machine Trace Metrics
+ Early If-Conversion
+-- MachineDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Early If-Conversion
+ AArch64 Store Pair Suppression
+-- Machine Trace Metrics
+-- AArch64 Store Pair Suppression
+ AArch64 SIMD instructions optimization pass
+-- AArch64 SIMD instructions optimization pass
+ AArch64 Stack Tagging PreRA
+-- AArch64 Stack Tagging PreRA
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Machine Block Frequency Analysis
+ Early Machine Loop Invariant Code Motion
+-- Early Machine Loop Invariant Code Motion
+-- Machine Block Frequency Analysis
+-- MachineDominator Tree Construction
+ MachineDominator Tree Construction
+ Machine Block Frequency Analysis
+ Machine Common Subexpression Elimination
+-- Machine Common Subexpression Elimination
+ MachinePostDominator Tree Construction
+ Machine Cycle Info Analysis
+ Machine code sinking
+-- Machine code sinking
+-- Machine Block Frequency Analysis
+-- Machine Cycle Info Analysis
+-- MachineDominator Tree Construction
+-- MachinePostDominator Tree Construction
+ Peephole Optimizations
+-- Peephole Optimizations
+ Remove dead machine instructions
+-- Remove dead machine instructions
+ AArch64 MI Peephole Optimization pass
+-- AArch64 MI Peephole Optimization pass
+ AArch64 Dead register definitions
+-- AArch64 Dead register definitions
+ Detect Dead Lanes
+-- Detect Dead Lanes
+ Init Undef Pass
+-- Init Undef Pass
+ Process Implicit Definitions
+-- Process Implicit Definitions
+ Remove unreachable machine basic blocks
+ Live Variable Analysis
+ Eliminate PHI nodes for register allocation
+-- Eliminate PHI nodes for register allocation
+-- Remove unreachable machine basic blocks
+ Two-Address instruction pass
+-- Two-Address instruction pass
+-- Live Variable Analysis
+ MachineDominator Tree Construction
+ Slot index numbering
+ Live Interval Analysis
+ Register Coalescer
+-- Register Coalescer
+ Rename Disconnected Subregister Components
+-- Rename Disconnected Subregister Components
+ Machine Instruction Scheduler
+-- Machine Instruction Scheduler
+ AArch64 Post Coalescer pass
+-- AArch64 Post Coalescer pass
+ Machine Block Frequency Analysis
+ Debug Variable Analysis
+ Live Stack Slot Analysis
+ Virtual Register Map
+ Live Register Matrix
+ Bundle Machine CFG Edges
+ Spill Code Placement Analysis
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Greedy Register Allocator
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Greedy Register Allocator
+-- Spill Code Placement Analysis
+-- Bundle Machine CFG Edges
+ Virtual Register Rewriter
+-- Debug Variable Analysis
+-- Live Register Matrix
+-- Live Interval Analysis
+-- Virtual Register Map
+-- Virtual Register Rewriter
+ Register Allocation Pass Scoring
+-- Register Allocation Pass Scoring
+ Stack Slot Coloring
+-- Live Stack Slot Analysis
+-- Slot index numbering
+-- Stack Slot Coloring
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Machine Loop Invariant Code Motion
+-- Machine Natural Loop Construction
+-- Machine Block Frequency Analysis
+-- MachineDominator Tree Construction
+-- Machine Loop Invariant Code Motion
+ AArch64 Redundant Copy Elimination
+-- AArch64 Redundant Copy Elimination
+ A57 FP Anti-dependency breaker
+-- A57 FP Anti-dependency breaker
+ Remove Redundant DEBUG_VALUE analysis
+-- Remove Redundant DEBUG_VALUE analysis
+ Fixup Statepoint Caller Saved
+-- Fixup Statepoint Caller Saved
+ PostRA Machine Sink
+-- PostRA Machine Sink
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Machine Block Frequency Analysis
+ MachinePostDominator Tree Construction
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Shrink Wrapping analysis
+-- Lazy Machine Block Frequency Analysis
+-- MachinePostDominator Tree Construction
+-- MachineDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Shrink Wrapping analysis
+ Prologue/Epilogue Insertion & Frame Finalization
+-- Machine Optimization Remark Emitter
+-- Prologue/Epilogue Insertion & Frame Finalization
+ Machine Late Instructions Cleanup Pass
+-- Machine Late Instructions Cleanup Pass
+ Control Flow Optimizer
+-- Machine Block Frequency Analysis
+-- Control Flow Optimizer
+ Lazy Machine Block Frequency Analysis
+ Tail Duplication
+-- Lazy Machine Block Frequency Analysis
+-- Tail Duplication
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Post-RA pseudo instruction expansion pass
+-- Post-RA pseudo instruction expansion pass
+ AArch64 pseudo instruction expansion pass
+-- AArch64 pseudo instruction expansion pass
+ AArch64 load / store optimization pass
+-- AArch64 load / store optimization pass
+ Insert KCFI indirect call checks
+-- Insert KCFI indirect call checks
+ AArch64 speculation hardening pass
+-- AArch64 speculation hardening pass
+ MachineDominator Tree Construction
+ Machine Natural Loop Construction
+ Falkor HW Prefetch Fix Late Phase
+-- Falkor HW Prefetch Fix Late Phase
+ PostRA Machine Instruction Scheduler
+-- MachineDominator Tree Construction
+-- PostRA Machine Instruction Scheduler
+ Analyze Machine Code For Garbage Collection
+-- Analyze Machine Code For Garbage Collection
+ Machine Block Frequency Analysis
+ MachinePostDominator Tree Construction
+ Branch Probability Basic Block Placement
+-- Machine Block Frequency Analysis
+-- MachinePostDominator Tree Construction
+-- Machine Natural Loop Construction
+-- Branch Probability Basic Block Placement
+ Insert fentry calls
+-- Insert fentry calls
+ Insert XRay ops
+-- Insert XRay ops
+ Implement the 'patchable-function' attribute
+-- Implement the 'patchable-function' attribute
+ AArch64 load / store optimization pass
+-- Function Alias Analysis Results
+-- Basic Alias Analysis (stateless AA impl)
+-- Dominator Tree Construction
+-- AArch64 load / store optimization pass
+ Machine Copy Propagation Pass
+-- Machine Copy Propagation Pass
+ Workaround A53 erratum 835769 pass
+-- Workaround A53 erratum 835769 pass
+ AArch64 Collect Linker Optimization Hint (LOH)
+-- AArch64 Collect Linker Optimization Hint (LOH)
+ Contiguously Lay Out Funclets
+-- Contiguously Lay Out Funclets
+ Remove Loads Into Fake Uses
+-- Remove Loads Into Fake Uses
+ StackMap Liveness Analysis
+-- StackMap Liveness Analysis
+ Live DEBUG_VALUE analysis
+-- Live DEBUG_VALUE analysis
+ Machine Sanitizer Binary Metadata
+-- Machine Sanitizer Binary Metadata
+-- Assumption Cache Tracker
+-- Profile summary info
+-- Scoped NoAlias Alias Analysis
+-- Type-Based Alias Analysis
+-- Default Regalloc Eviction Advisor
+-- Default Regalloc Priority Advisor
+-- Target Library Information
+-- Target Pass Configuration
+ Machine Outliner
+-- Machine Outliner
+ FunctionPass Manager
+ AArch64 sls hardening pass
+-- AArch64 sls hardening pass
+ AArch64 Pointer Authentication
+-- AArch64 Pointer Authentication
+ AArch64 Branch Targets
+-- AArch64 Branch Targets
+ Branch relaxation pass
+-- Branch relaxation pass
+ AArch64 Compress Jump Tables
+-- AArch64 Compress Jump Tables
+ Insert CFI remember/restore state instructions
+-- Insert CFI remember/restore state instructions
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Stack Frame Layout Analysis
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- Stack Frame Layout Analysis
+ Unpack machine instruction bundles
+-- Unpack machine instruction bundles
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ AArch64 Assembly Printer
+-- Machine Optimization Remark Emitter
+-- Lazy Machine Block Frequency Analysis
+-- AArch64 Assembly Printer
+ Free MachineFunction
+-- Free MachineFunction
+-- Create Garbage Collector Module Metadata
+-- Machine Branch Probability Analysis
+-- Machine Module Information
+Pass Arguments: -domtree
+ FunctionPass Manager
+ Dominator Tree Construction
+Pass Arguments: -assumption-cache-tracker -targetlibinfo -domtree -loops -scalar-evolution -stack-safety-local
+Assumption Cache Tracker
+Target Library Information
+ FunctionPass Manager
+ Dominator Tree Construction
+ Natural Loop Information
+ Scalar Evolution Analysis
+ Stack Safety Local Analysis
+Pass Arguments: -domtree
+ FunctionPass Manager
+ Dominator Tree Construction
+Running pass: Pre-ISel Intrinsic Lowering
+[2025-06-18 00:57:43.670010000] 0x153005ad0 Executing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+0x151f21a70 Required Analyses: Target Transform Information, Target Library Information, Target Pass Configuration
+ -*- 'Pre-ISel Intrinsic Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.670506000] 0x153005ad0 Freeing Pass 'Pre-ISel Intrinsic Lowering' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:43.670558000] 0x153005ad0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Expand large div/rem
+[2025-06-18 00:57:43.670610000] 0x151f20600 Executing Pass 'Expand large div/rem' on Function 'main'...
+0x151f21ab0 Required Analyses: Target Pass Configuration
+0x151f21ab0 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand large div/rem' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.670727000] 0x151f20600 Freeing Pass 'Expand large div/rem' on Function 'main'...
+Running pass: Expand fp
+[2025-06-18 00:57:43.670791000] 0x151f20600 Executing Pass 'Expand fp' on Function 'main'...
+0x151f21ad0 Required Analyses: Target Pass Configuration
+0x151f21ad0 Preserved Analyses: Function Alias Analysis Results, Globals Alias Analysis
+ -*- 'Expand fp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.670932000] 0x151f20600 Freeing Pass 'Expand fp' on Function 'main'...
+Running pass: Expand Atomic instructions
+[2025-06-18 00:57:43.670985000] 0x151f20600 Executing Pass 'Expand Atomic instructions' on Function 'main'...
+ -*- 'Expand Atomic instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.671042000] 0x151f20600 Freeing Pass 'Expand Atomic instructions' on Function 'main'...
+Running pass: SVE intrinsics optimizations
+[2025-06-18 00:57:43.671094000] 0x153005ad0 Executing Pass 'SVE intrinsics optimizations' on Module 'test.c'...
+0x151f21100 Required Analyses: Dominator Tree Construction
+0x151f21100 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'SVE intrinsics optimizations' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.671492000] 0x153005ad0 Freeing Pass 'SVE intrinsics optimizations' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:43.671543000] 0x153005ad0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Simplify the CFG
+[2025-06-18 00:57:43.671595000] 0x151f235e0 Executing Pass 'Simplify the CFG' on Function 'main'...
+0x151f21120 Required Analyses: Assumption Cache Tracker, Target Transform Information
+0x151f21120 Preserved Analyses: Globals Alias Analysis
+ -*- 'Simplify the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.671719000] 0x151f235e0 Freeing Pass 'Simplify the CFG' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.671772000] 0x151f235e0 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.671826000] 0x151f235e0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x151f23760 Required Analyses: Dominator Tree Construction
+Running pass: Canonicalize natural loops
+[2025-06-18 00:57:43.671904000] 0x151f235e0 Executing Pass 'Canonicalize natural loops' on Function 'main'...
+0x151f21960 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information
+0x151f21960 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Basic Alias Analysis (stateless AA impl), Function Alias Analysis Results, Globals Alias Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Loop-Closed SSA Form Pass, Uninitialized Pass, Branch Probability Analysis, Memory SSA
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:43.672125000] 0x151f235e0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x151f23870 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:43.672243000] 0x151f235e0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x151f238d0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:43.672352000] 0x151f235e0 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x151f21980 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Scalar Evolution Analysis
+[2025-06-18 00:57:43.672471000] 0x151f235e0 Executing Pass 'Scalar Evolution Analysis' on Function 'main'...
+0x151f23a20 Required Analyses: Assumption Cache Tracker, Natural Loop Information, Dominator Tree Construction, Target Library Information
+Running pass: Loop Data Prefetch
+[2025-06-18 00:57:43.672581000] 0x151f235e0 Executing Pass 'Loop Data Prefetch' on Function 'main'...
+0x151f216d0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information, Canonicalize natural loops, Optimization Remark Emitter, Scalar Evolution Analysis, Target Transform Information
+0x151f216d0 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Canonicalize natural loops, Scalar Evolution Analysis
+ -*- 'Loop Data Prefetch' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.672781000] 0x151f235e0 Freeing Pass 'Loop Data Prefetch' on Function 'main'...
+[2025-06-18 00:57:43.672823000] 0x151f235e0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.672866000] 0x151f235e0 Freeing Pass 'Canonicalize natural loops' on Function 'main'...
+[2025-06-18 00:57:43.672908000] 0x151f235e0 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.672951000] 0x151f235e0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+Running pass: Falkor HW Prefetch Fix
+[2025-06-18 00:57:43.673004000] 0x151f235e0 Executing Pass 'Falkor HW Prefetch Fix' on Function 'main'...
+0x151f23af0 Required Analyses: Target Pass Configuration, Natural Loop Information, Scalar Evolution Analysis
+0x151f23af0 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Scalar Evolution Analysis
+ -*- 'Falkor HW Prefetch Fix' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.673150000] 0x151f235e0 Freeing Pass 'Falkor HW Prefetch Fix' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:43.673202000] 0x151f235e0 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x151f23bd0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+ -*- 'Basic Alias Analysis (stateless AA impl)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.673304000] 0x151f235e0 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+Running pass: Canonicalize natural loops
+[2025-06-18 00:57:43.673357000] 0x151f235e0 Executing Pass 'Canonicalize natural loops' on Function 'main'...
+0x151f23d30 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Natural Loop Information
+0x151f23d30 Preserved Analyses: Dominator Tree Construction, Natural Loop Information, Basic Alias Analysis (stateless AA impl), Function Alias Analysis Results, Globals Alias Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Loop-Closed SSA Form Pass, Uninitialized Pass, Branch Probability Analysis, Memory SSA
+Running pass: Loop Pass Manager
+[2025-06-18 00:57:43.673579000] 0x151f235e0 Executing Pass 'Loop Pass Manager' on Function 'main'...
+0x151f23db0 Required Analyses: Natural Loop Information, Dominator Tree Construction
+ -*- 'Loop Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.673693000] 0x151f235e0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.673736000] 0x151f235e0 Freeing Pass 'Scalar Evolution Analysis' on Function 'main'...
+[2025-06-18 00:57:43.673793000] 0x151f235e0 Freeing Pass 'Canonicalize natural loops' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:43.673845000] 0x151f235e0 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x1530080f0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:43.673945000] 0x151f235e0 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x153008090 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x153008090 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Merge contiguous icmps into a memcmp
+[2025-06-18 00:57:43.674104000] 0x151f235e0 Executing Pass 'Merge contiguous icmps into a memcmp' on Function 'main'...
+0x153007fc0 Required Analyses: Target Library Information, Target Transform Information, Function Alias Analysis Results
+0x153007fc0 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Merge contiguous icmps into a memcmp' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.674663000] 0x151f235e0 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:43.674710000] 0x151f235e0 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:43.674753000] 0x151f235e0 Freeing Pass 'Merge contiguous icmps into a memcmp' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.674813000] 0x151f235e0 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x1530082c0 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:43.674893000] 0x151f235e0 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x153008120 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:43.674993000] 0x151f235e0 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x1530084c0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Expand memcmp() to load/stores
+[2025-06-18 00:57:43.675102000] 0x151f235e0 Executing Pass 'Expand memcmp() to load/stores' on Function 'main'...
+0x153007f30 Required Analyses: Target Library Information, Target Transform Information, Profile summary info, Lazy Branch Probability Analysis, Natural Loop Information, Lazy Block Frequency Analysis
+0x153007f30 Preserved Analyses: Dominator Tree Construction
+ -*- 'Expand memcmp() to load/stores' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.675267000] 0x151f235e0 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.675309000] 0x151f235e0 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.675351000] 0x151f235e0 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.675393000] 0x151f235e0 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.675435000] 0x151f235e0 Freeing Pass 'Expand memcmp() to load/stores' on Function 'main'...
+Running pass: Lower Garbage Collection Instructions
+[2025-06-18 00:57:43.675487000] 0x151f235e0 Executing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+0x153008550 Required Analyses: Create Garbage Collector Module Metadata
+0x153008550 Preserved Analyses: Dominator Tree Construction
+ -*- 'Lower Garbage Collection Instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.675624000] 0x151f235e0 Freeing Pass 'Lower Garbage Collection Instructions' on Function 'main'...
+Running pass: Shadow Stack GC Lowering
+[2025-06-18 00:57:43.675677000] 0x151f235e0 Executing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+0x153008630 Preserved Analyses: Dominator Tree Construction
+ -*- 'Shadow Stack GC Lowering' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.675781000] 0x151f235e0 Freeing Pass 'Shadow Stack GC Lowering' on Function 'main'...
+Running pass: Lower @llvm.global_dtors via `__cxa_atexit`
+[2025-06-18 00:57:43.675834000] 0x153005ad0 Executing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+0x1530086a0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Lower @llvm.global_dtors via `__cxa_atexit`' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.676258000] 0x153005ad0 Freeing Pass 'Lower @llvm.global_dtors via `__cxa_atexit`' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:43.676318000] 0x153005ad0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Remove unreachable blocks from the CFG
+[2025-06-18 00:57:43.676372000] 0x153008720 Executing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+0x1530086e0 Preserved Analyses: Dominator Tree Construction
+ -*- 'Remove unreachable blocks from the CFG' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.676465000] 0x153008720 Freeing Pass 'Remove unreachable blocks from the CFG' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.676517000] 0x153008720 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.676569000] 0x153008720 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x153008d00 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:57:43.676645000] 0x153008720 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:57:43.676700000] 0x153008720 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x153008b40 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Block Frequency Analysis
+[2025-06-18 00:57:43.677845000] 0x153008720 Executing Pass 'Block Frequency Analysis' on Function 'main'...
+0x153008290 Required Analyses: Branch Probability Analysis, Natural Loop Information
+Running pass: Constant Hoisting
+[2025-06-18 00:57:43.678192000] 0x153008720 Executing Pass 'Constant Hoisting' on Function 'main'...
+0x153838000 Required Analyses: Block Frequency Analysis, Dominator Tree Construction, Profile summary info, Target Transform Information
+0x153838000 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Constant Hoisting' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.679487000] 0x153008720 Freeing Pass 'Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.679533000] 0x153008720 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.679575000] 0x153008720 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.679618000] 0x153008720 Freeing Pass 'Constant Hoisting' on Function 'main'...
+Running pass: Replace intrinsics with calls to vector library
+[2025-06-18 00:57:43.679670000] 0x153008720 Executing Pass 'Replace intrinsics with calls to vector library' on Function 'main'...
+0x153008e30 Required Analyses: Target Library Information
+0x153008e30 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Target Library Information, Scalar Evolution Analysis, Function Alias Analysis Results, Optimization Remark Emitter, Globals Alias Analysis
+ -*- 'Replace intrinsics with calls to vector library' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.680118000] 0x153008720 Freeing Pass 'Replace intrinsics with calls to vector library' on Function 'main'...
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:43.680172000] 0x153008720 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x1530090f0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:43.680269000] 0x153008720 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x153009120 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:43.680378000] 0x153008720 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x1530090c0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Partially inline calls to library functions
+[2025-06-18 00:57:43.680520000] 0x153008720 Executing Pass 'Partially inline calls to library functions' on Function 'main'...
+0x153008f40 Required Analyses: Target Library Information, Target Transform Information, Optimization Remark Emitter
+0x153008f40 Preserved Analyses: Dominator Tree Construction
+ -*- 'Partially inline calls to library functions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.680645000] 0x153008720 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.680686000] 0x153008720 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.680728000] 0x153008720 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.680769000] 0x153008720 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.680811000] 0x153008720 Freeing Pass 'Partially inline calls to library functions' on Function 'main'...
+Running pass: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+[2025-06-18 00:57:43.680866000] 0x153008720 Executing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+0x1530091d0 Preserved Analyses: Globals Alias Analysis, Dominator Tree Construction
+ -*- 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.680954000] 0x153008720 Freeing Pass 'Instrument function entry/exit with calls to e.g. mcount() (post inlining)' on Function 'main'...
+Running pass: Scalarize Masked Memory Intrinsics
+[2025-06-18 00:57:43.681006000] 0x153008720 Executing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+0x153009250 Required Analyses: Target Transform Information
+0x153009250 Preserved Analyses: Dominator Tree Construction
+ -*- 'Scalarize Masked Memory Intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.681153000] 0x153008720 Freeing Pass 'Scalarize Masked Memory Intrinsics' on Function 'main'...
+Running pass: Expand reduction intrinsics
+[2025-06-18 00:57:43.681205000] 0x153008720 Executing Pass 'Expand reduction intrinsics' on Function 'main'...
+0x153009300 Required Analyses: Target Transform Information
+0x153009300 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Expand reduction intrinsics' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.681598000] 0x153008720 Freeing Pass 'Expand reduction intrinsics' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.681649000] 0x153008720 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x153009700 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:57:43.681757000] 0x153008720 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:57:43.681811000] 0x153008720 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x153009a00 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Block Frequency Analysis
+[2025-06-18 00:57:43.681922000] 0x153008720 Executing Pass 'Block Frequency Analysis' on Function 'main'...
+0x1530097d0 Required Analyses: Branch Probability Analysis, Natural Loop Information
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:43.682014000] 0x153008720 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x153009890 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:43.682123000] 0x153008720 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x153009c30 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:43.682229000] 0x153008720 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x153009860 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: Optimize selects
+[2025-06-18 00:57:43.682347000] 0x153008720 Executing Pass 'Optimize selects' on Function 'main'...
+0x153009580 Required Analyses: Profile summary info, Target Pass Configuration, Target Transform Information, Natural Loop Information, Block Frequency Analysis, Optimization Remark Emitter
+ -*- 'Optimize selects' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.682497000] 0x153008720 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.682540000] 0x153008720 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.682581000] 0x153008720 Freeing Pass 'Optimize selects' on Function 'main'...
+[2025-06-18 00:57:43.682622000] 0x153008720 Freeing Pass 'Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.682665000] 0x153008720 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.682706000] 0x153008720 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.682748000] 0x153008720 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.682789000] 0x153008720 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.682830000] 0x153008720 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Stack Safety Analysis
+[2025-06-18 00:57:43.682882000] 0x153005ad0 Executing Pass 'Stack Safety Analysis' on Module 'test.c'...
+0x153009e40 Required Analyses: Stack Safety Local Analysis
+Running pass: Function Pass Manager
+[2025-06-18 00:57:43.682958000] 0x153005ad0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.683009000] 0x15300a960 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:43.683062000] 0x15300a960 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x15300a840 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:43.683158000] 0x15300a960 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x15300a0f0 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x15300a0f0 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.683331000] 0x15300a960 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x15300ac10 Required Analyses: Dominator Tree Construction
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:43.683406000] 0x15300a960 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x15300ab20 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:43.683502000] 0x15300a960 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x15300ad00 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: Optimization Remark Emitter
+[2025-06-18 00:57:43.683619000] 0x15300a960 Executing Pass 'Optimization Remark Emitter' on Function 'main'...
+0x15300a870 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Lazy Block Frequency Analysis, Profile summary info
+Running pass: AArch64 Stack Tagging
+[2025-06-18 00:57:43.683735000] 0x15300a960 Executing Pass 'AArch64 Stack Tagging' on Function 'main'...
+0x153009ce0 Required Analyses: Stack Safety Analysis, Function Alias Analysis Results, Optimization Remark Emitter
+0x153009ce0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'AArch64 Stack Tagging' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.684143000] 0x15300a960 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:43.684185000] 0x15300a960 Freeing Pass 'AArch64 Stack Tagging' on Function 'main'...
+[2025-06-18 00:57:43.684227000] 0x15300a960 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.684268000] 0x15300a960 Freeing Pass 'Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.684309000] 0x15300a960 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.684351000] 0x15300a960 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+Running pass: Complex Deinterleaving Pass
+[2025-06-18 00:57:43.684403000] 0x15300a960 Executing Pass 'Complex Deinterleaving Pass' on Function 'main'...
+0x15300abe0 Required Analyses: Target Library Information
+0x15300abe0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Complex Deinterleaving Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.684979000] 0x15300a960 Freeing Pass 'Complex Deinterleaving Pass' on Function 'main'...
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:43.685033000] 0x15300a960 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x15300ae90 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x15300ae90 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Memory SSA
+[2025-06-18 00:57:43.685190000] 0x15300a960 Executing Pass 'Memory SSA' on Function 'main'...
+0x15300ae60 Required Analyses: Dominator Tree Construction, Function Alias Analysis Results
+Running pass: Interleaved Load Combine Pass
+[2025-06-18 00:57:43.685282000] 0x15300a960 Executing Pass 'Interleaved Load Combine Pass' on Function 'main'...
+0x15300ae40 Required Analyses: Memory SSA, Dominator Tree Construction, Target Transform Information
+ -*- 'Interleaved Load Combine Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.685384000] 0x15300a960 Freeing Pass 'Memory SSA' on Function 'main'...
+[2025-06-18 00:57:43.685426000] 0x15300a960 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:43.685467000] 0x15300a960 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:43.685508000] 0x15300a960 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.685549000] 0x15300a960 Freeing Pass 'Interleaved Load Combine Pass' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.685600000] 0x15300a960 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Interleaved Access Pass
+[2025-06-18 00:57:43.685653000] 0x15300a960 Executing Pass 'Interleaved Access Pass' on Function 'main'...
+0x15300aec0 Required Analyses: Dominator Tree Construction
+0x15300aec0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Interleaved Access Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.686042000] 0x15300a960 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.686084000] 0x15300a960 Freeing Pass 'Interleaved Access Pass' on Function 'main'...
+Running pass: SME ABI Pass
+[2025-06-18 00:57:43.686156000] 0x15300a960 Executing Pass 'SME ABI Pass' on Function 'main'...
+ -*- 'SME ABI Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.686213000] 0x15300a960 Freeing Pass 'SME ABI Pass' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.686265000] 0x15300a960 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.686318000] 0x15300a960 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x15300b2a0 Required Analyses: Dominator Tree Construction
+Running pass: Type Promotion
+[2025-06-18 00:57:43.686396000] 0x15300a960 Executing Pass 'Type Promotion' on Function 'main'...
+0x15300b080 Required Analyses: Natural Loop Information, Target Transform Information, Target Pass Configuration
+0x15300b080 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Type Promotion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.686814000] 0x15300a960 Freeing Pass 'Type Promotion' on Function 'main'...
+Running pass: CodeGen Prepare
+[2025-06-18 00:57:43.686866000] 0x15300a960 Executing Pass 'CodeGen Prepare' on Function 'main'...
+0x15300b630 Required Analyses: Profile summary info, Target Library Information, Target Pass Configuration, Target Transform Information, Natural Loop Information
+0x15300b630 Used Analyses: Reads and parses a basic block sections profile.
+ -*- 'CodeGen Prepare' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.689859000] 0x15300a960 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.689901000] 0x15300a960 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.689943000] 0x15300a960 Freeing Pass 'CodeGen Prepare' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.689994000] 0x15300a960 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Exception handling preparation
+[2025-06-18 00:57:43.690047000] 0x15300a960 Executing Pass 'Exception handling preparation' on Function 'main'...
+0x15300b670 Required Analyses: Target Pass Configuration, Target Transform Information, Dominator Tree Construction
+0x15300b670 Preserved Analyses: Dominator Tree Construction
+ -*- 'Exception handling preparation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.690173000] 0x15300a960 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.690215000] 0x15300a960 Freeing Pass 'Exception handling preparation' on Function 'main'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.690271000] 0x153005ad0 Freeing Pass 'Target Transform Information' on Module 'test.c'...
+[2025-06-18 00:57:43.690312000] 0x153005ad0 Freeing Pass 'Stack Safety Analysis' on Module 'test.c'...
+Running pass: AArch64 Promote Constant
+[2025-06-18 00:57:43.690368000] 0x153005ad0 Executing Pass 'AArch64 Promote Constant' on Module 'test.c'...
+0x15300b7b0 Required Analyses: Dominator Tree Construction
+0x15300b7b0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'AArch64 Promote Constant' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.690794000] 0x153005ad0 Freeing Pass 'AArch64 Promote Constant' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:43.690846000] 0x153005ad0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: Merge internal globals
+[2025-06-18 00:57:43.690899000] 0x151f24080 Executing Pass 'Merge internal globals' on Function 'main'...
+0x151f23fe0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis
+ -*- 'Merge internal globals' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.691269000] 0x151f24080 Freeing Pass 'Merge internal globals' on Function 'main'...
+Running pass: Dominator Tree Construction
+[2025-06-18 00:57:43.691321000] 0x151f24080 Executing Pass 'Dominator Tree Construction' on Function 'main'...
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:43.691374000] 0x151f24080 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x151f24300 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:43.691474000] 0x151f24080 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x151f24260 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x151f24260 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: ObjC ARC contraction
+[2025-06-18 00:57:43.691634000] 0x151f24080 Executing Pass 'ObjC ARC contraction' on Function 'main'...
+0x151f24240 Required Analyses: Function Alias Analysis Results, Dominator Tree Construction
+0x151f24240 Preserved Analyses: Function Alias Analysis Results, Basic Alias Analysis (stateless AA impl), Dominator Tree Construction
+ -*- 'ObjC ARC contraction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.691933000] 0x151f24080 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:43.691975000] 0x151f24080 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:43.692016000] 0x151f24080 Freeing Pass 'ObjC ARC contraction' on Function 'main'...
+Running pass: Prepare callbr
+[2025-06-18 00:57:43.692067000] 0x151f24080 Executing Pass 'Prepare callbr' on Function 'main'...
+0x151f24440 Preserved Analyses: Dominator Tree Construction
+ -*- 'Prepare callbr' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.692146000] 0x151f24080 Freeing Pass 'Prepare callbr' on Function 'main'...
+Running pass: Safe Stack instrumentation pass
+[2025-06-18 00:57:43.692197000] 0x151f24080 Executing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+0x151f24330 Required Analyses: Target Pass Configuration, Target Library Information, Assumption Cache Tracker
+0x151f24330 Preserved Analyses: Dominator Tree Construction
+ -*- 'Safe Stack instrumentation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.692320000] 0x151f24080 Freeing Pass 'Safe Stack instrumentation pass' on Function 'main'...
+Running pass: Insert stack protectors
+[2025-06-18 00:57:43.692371000] 0x151f24080 Executing Pass 'Insert stack protectors' on Function 'main'...
+0x151f244a0 Required Analyses: Target Pass Configuration
+0x151f244a0 Preserved Analyses: Dominator Tree Construction
+Running pass: Basic Alias Analysis (stateless AA impl)
+[2025-06-18 00:57:43.692471000] 0x151f24080 Executing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+0x15300bce0 Required Analyses: Assumption Cache Tracker, Dominator Tree Construction, Target Library Information
+Running pass: Function Alias Analysis Results
+[2025-06-18 00:57:43.692570000] 0x151f24080 Executing Pass 'Function Alias Analysis Results' on Function 'main'...
+0x15300bd70 Required Analyses: Basic Alias Analysis (stateless AA impl), Target Library Information
+0x15300bd70 Used Analyses: Scoped NoAlias Alias Analysis, Type-Based Alias Analysis, Globals Alias Analysis, ScalarEvolution-based Alias Analysis, External Alias Analysis
+Running pass: Natural Loop Information
+[2025-06-18 00:57:43.692726000] 0x151f24080 Executing Pass 'Natural Loop Information' on Function 'main'...
+0x15300cca0 Required Analyses: Dominator Tree Construction
+Running pass: Post-Dominator Tree Construction
+[2025-06-18 00:57:43.692804000] 0x151f24080 Executing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Branch Probability Analysis
+[2025-06-18 00:57:43.692858000] 0x151f24080 Executing Pass 'Branch Probability Analysis' on Function 'main'...
+0x15300c8b0 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information, Post-Dominator Tree Construction
+Running pass: Assignment Tracking Analysis
+[2025-06-18 00:57:43.692966000] 0x151f24080 Executing Pass 'Assignment Tracking Analysis' on Function 'main'...
+Running pass: Lazy Branch Probability Analysis
+[2025-06-18 00:57:43.693019000] 0x151f24080 Executing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+0x15300cd70 Required Analyses: Dominator Tree Construction, Natural Loop Information, Target Library Information
+Running pass: Lazy Block Frequency Analysis
+[2025-06-18 00:57:43.693116000] 0x151f24080 Executing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+0x15300cdf0 Required Analyses: Lazy Branch Probability Analysis, Natural Loop Information, Target Library Information, Dominator Tree Construction
+Running pass: AArch64 Instruction Selection
+[2025-06-18 00:57:43.693222000] 0x151f24080 Executing Pass 'AArch64 Instruction Selection' on Function 'main'...
+0x151f247d0 Required Analyses: Function Alias Analysis Results, Create Garbage Collector Module Metadata, Insert stack protectors, Target Library Information, Assumption Cache Tracker, Branch Probability Analysis, Profile summary info, Assignment Tracking Analysis, Lazy Branch Probability Analysis, Natural Loop Information, Lazy Block Frequency Analysis, Machine Module Information
+[2025-06-18 00:57:43.712107000] 0x151f24080 Made Modification 'AArch64 Instruction Selection' on Function 'main'...
+0x151f247d0 Preserved Analyses: Create Garbage Collector Module Metadata, Assignment Tracking Analysis, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Post-Dominator Tree Construction'
+ -- 'AArch64 Instruction Selection' is not preserving 'Branch Probability Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Lazy Block Frequency Analysis'
+ -- 'AArch64 Instruction Selection' is not preserving 'Insert stack protectors'
+ -- 'AArch64 Instruction Selection' is not preserving 'Function Pass Manager'
+ -*- 'AArch64 Instruction Selection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.712425000] 0x151f24080 Freeing Pass 'Assignment Tracking Analysis' on Function 'main'...
+[2025-06-18 00:57:43.712467000] 0x151f24080 Freeing Pass 'Natural Loop Information' on Function 'main'...
+[2025-06-18 00:57:43.712511000] 0x151f24080 Freeing Pass 'Lazy Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.712553000] 0x151f24080 Freeing Pass 'Lazy Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.712595000] 0x151f24080 Freeing Pass 'AArch64 Instruction Selection' on Function 'main'...
+[2025-06-18 00:57:43.712638000] 0x151f24080 Freeing Pass 'Insert stack protectors' on Function 'main'...
+[2025-06-18 00:57:43.712680000] 0x151f24080 Freeing Pass 'Branch Probability Analysis' on Function 'main'...
+[2025-06-18 00:57:43.712722000] 0x151f24080 Freeing Pass 'Post-Dominator Tree Construction' on Function 'main'...
+Running pass: Finalize ISel and expand pseudo-instructions
+[2025-06-18 00:57:43.712776000] 0x151f24080 Executing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+0x15300d140 Required Analyses: Machine Module Information
+0x15300d140 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Finalize ISel and expand pseudo-instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.713135000] 0x151f24080 Freeing Pass 'Finalize ISel and expand pseudo-instructions' on Function 'main'...
+Running pass: SME Peephole Optimization pass
+[2025-06-18 00:57:43.713188000] 0x151f24080 Executing Pass 'SME Peephole Optimization pass' on Function 'main'...
+0x15300d180 Required Analyses: Machine Module Information
+0x15300d180 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'SME Peephole Optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.713687000] 0x151f24080 Freeing Pass 'SME Peephole Optimization pass' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.713739000] 0x151f24080 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15300d2e0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15300d2e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early Tail Duplication
+[2025-06-18 00:57:43.713951000] 0x151f24080 Executing Pass 'Early Tail Duplication' on Function 'main'...
+0x15300d1f0 Required Analyses: Machine Branch Probability Analysis, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x15300d1f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early Tail Duplication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.714189000] 0x151f24080 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.714674000] 0x151f24080 Freeing Pass 'Early Tail Duplication' on Function 'main'...
+Running pass: Optimize machine instruction PHIs
+[2025-06-18 00:57:43.714728000] 0x151f24080 Executing Pass 'Optimize machine instruction PHIs' on Function 'main'...
+0x15300d360 Required Analyses: Machine Module Information
+0x15300d360 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Optimize machine instruction PHIs' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.715204000] 0x151f24080 Freeing Pass 'Optimize machine instruction PHIs' on Function 'main'...
+Running pass: Slot index numbering
+[2025-06-18 00:57:43.715280000] 0x151f24080 Executing Pass 'Slot index numbering' on Function 'main'...
+0x15300d7b0 Required Analyses: Machine Module Information
+0x15300d7b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Merge disjoint stack slots
+[2025-06-18 00:57:43.715482000] 0x151f24080 Executing Pass 'Merge disjoint stack slots' on Function 'main'...
+0x15300d500 Required Analyses: Slot index numbering, Machine Module Information
+0x15300d500 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Merge disjoint stack slots' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.715709000] 0x151f24080 Freeing Pass 'Slot index numbering' on Function 'main'...
+[2025-06-18 00:57:43.715751000] 0x151f24080 Freeing Pass 'Merge disjoint stack slots' on Function 'main'...
+Running pass: Local Stack Slot Allocation
+[2025-06-18 00:57:43.715804000] 0x151f24080 Executing Pass 'Local Stack Slot Allocation' on Function 'main'...
+0x15300d540 Required Analyses: Machine Module Information
+0x15300d540 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Local Stack Slot Allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.716280000] 0x151f24080 Freeing Pass 'Local Stack Slot Allocation' on Function 'main'...
+Running pass: Remove dead machine instructions
+[2025-06-18 00:57:43.716333000] 0x151f24080 Executing Pass 'Remove dead machine instructions' on Function 'main'...
+0x15300d9a0 Required Analyses: Machine Module Information
+0x15300d9a0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove dead machine instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.716840000] 0x151f24080 Freeing Pass 'Remove dead machine instructions' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:43.716892000] 0x151f24080 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x15300ceb0 Required Analyses: Machine Module Information
+0x15300ceb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Condition Optimizer
+[2025-06-18 00:57:43.717217000] 0x151f24080 Executing Pass 'AArch64 Condition Optimizer' on Function 'main'...
+0x15300ce60 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x15300ce60 Preserved Analyses: MachineDominator Tree Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Condition Optimizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.717438000] 0x151f24080 Freeing Pass 'AArch64 Condition Optimizer' on Function 'main'...
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:43.717489000] 0x151f24080 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x15300de80 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x15300de80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Trace Metrics
+[2025-06-18 00:57:43.717697000] 0x151f24080 Executing Pass 'Machine Trace Metrics' on Function 'main'...
+0x15300e2a0 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x15300e2a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Conditional Compares
+[2025-06-18 00:57:43.717905000] 0x151f24080 Executing Pass 'AArch64 Conditional Compares' on Function 'main'...
+0x15300dff0 Required Analyses: Machine Branch Probability Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information
+0x15300dff0 Preserved Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Conditional Compares' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.718583000] 0x151f24080 Freeing Pass 'AArch64 Conditional Compares' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.718635000] 0x151f24080 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x15300df50 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x15300df50 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine InstCombiner
+[2025-06-18 00:57:43.718840000] 0x151f24080 Executing Pass 'Machine InstCombiner' on Function 'main'...
+0x15300e6d0 Required Analyses: Machine Natural Loop Construction, Machine Trace Metrics, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x15300e6d0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Trace Metrics, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine InstCombiner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.720731000] 0x151f24080 Freeing Pass 'Machine InstCombiner' on Function 'main'...
+[2025-06-18 00:57:43.720775000] 0x151f24080 Freeing Pass 'Machine Trace Metrics' on Function 'main'...
+[2025-06-18 00:57:43.720817000] 0x151f24080 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+Running pass: AArch64 Conditional Branch Tuning
+[2025-06-18 00:57:43.720868000] 0x151f24080 Executing Pass 'AArch64 Conditional Branch Tuning' on Function 'main'...
+0x15300de00 Required Analyses: Machine Module Information
+0x15300de00 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Conditional Branch Tuning' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.721367000] 0x151f24080 Freeing Pass 'AArch64 Conditional Branch Tuning' on Function 'main'...
+Running pass: Machine Trace Metrics
+[2025-06-18 00:57:43.721421000] 0x151f24080 Executing Pass 'Machine Trace Metrics' on Function 'main'...
+0x15300ee70 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x15300ee70 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early If-Conversion
+[2025-06-18 00:57:43.721626000] 0x151f24080 Executing Pass 'Early If-Conversion' on Function 'main'...
+0x15300e690 Required Analyses: Machine Branch Probability Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information
+0x15300e690 Preserved Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Trace Metrics, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early If-Conversion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.721896000] 0x151f24080 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.721936000] 0x151f24080 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:43.721977000] 0x151f24080 Freeing Pass 'Early If-Conversion' on Function 'main'...
+Running pass: AArch64 Store Pair Suppression
+[2025-06-18 00:57:43.722029000] 0x151f24080 Executing Pass 'AArch64 Store Pair Suppression' on Function 'main'...
+0x15300ea00 Required Analyses: Machine Trace Metrics, Machine Module Information
+0x15300ea00 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Trace Metrics, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Store Pair Suppression' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.722518000] 0x151f24080 Freeing Pass 'Machine Trace Metrics' on Function 'main'...
+[2025-06-18 00:57:43.722668000] 0x151f24080 Freeing Pass 'AArch64 Store Pair Suppression' on Function 'main'...
+Running pass: AArch64 SIMD instructions optimization pass
+[2025-06-18 00:57:43.722721000] 0x151f24080 Executing Pass 'AArch64 SIMD instructions optimization pass' on Function 'main'...
+0x15300f060 Required Analyses: Machine Module Information
+0x15300f060 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 SIMD instructions optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.723826000] 0x151f24080 Freeing Pass 'AArch64 SIMD instructions optimization pass' on Function 'main'...
+Running pass: AArch64 Stack Tagging PreRA
+[2025-06-18 00:57:43.723877000] 0x151f24080 Executing Pass 'AArch64 Stack Tagging PreRA' on Function 'main'...
+0x15300ebb0 Required Analyses: Machine Module Information
+0x15300ebb0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Stack Tagging PreRA' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.724341000] 0x151f24080 Freeing Pass 'AArch64 Stack Tagging PreRA' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:43.724393000] 0x151f24080 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x15300d050 Required Analyses: Machine Module Information
+0x15300d050 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:43.724590000] 0x151f24080 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x15300f4b0 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x15300f4b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:43.724811000] 0x151f24080 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x15300f680 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x15300f680 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Early Machine Loop Invariant Code Motion
+[2025-06-18 00:57:43.725057000] 0x151f24080 Executing Pass 'Early Machine Loop Invariant Code Motion' on Function 'main'...
+0x15300ece0 Required Analyses: Machine Natural Loop Construction, Machine Block Frequency Analysis, MachineDominator Tree Construction, Function Alias Analysis Results, Machine Module Information
+0x15300ece0 Preserved Analyses: Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Early Machine Loop Invariant Code Motion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.726031000] 0x151f24080 Freeing Pass 'Early Machine Loop Invariant Code Motion' on Function 'main'...
+[2025-06-18 00:57:43.726077000] 0x151f24080 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.726119000] 0x151f24080 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:43.726171000] 0x151f24080 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x15300f770 Required Analyses: Machine Module Information
+0x15300f770 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:43.726373000] 0x151f24080 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x15300f890 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x15300f890 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Common Subexpression Elimination
+[2025-06-18 00:57:43.726593000] 0x151f24080 Executing Pass 'Machine Common Subexpression Elimination' on Function 'main'...
+0x15300f6c0 Required Analyses: Machine Module Information, MachineDominator Tree Construction, Machine Block Frequency Analysis
+0x15300f6c0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Common Subexpression Elimination' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.727277000] 0x151f24080 Freeing Pass 'Machine Common Subexpression Elimination' on Function 'main'...
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:57:43.727329000] 0x151f24080 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x15300fb70 Required Analyses: Machine Module Information
+0x15300fb70 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Cycle Info Analysis
+[2025-06-18 00:57:43.727792000] 0x151f24080 Executing Pass 'Machine Cycle Info Analysis' on Function 'main'...
+0x15300fa80 Required Analyses: Machine Module Information
+0x15300fa80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine code sinking
+[2025-06-18 00:57:43.727994000] 0x151f24080 Executing Pass 'Machine code sinking' on Function 'main'...
+0x15300f830 Required Analyses: Machine Module Information, Function Alias Analysis Results, MachineDominator Tree Construction, MachinePostDominator Tree Construction, Machine Cycle Info Analysis, Machine Branch Probability Analysis, Profile summary info, Machine Block Frequency Analysis, Target Pass Configuration
+[2025-06-18 00:57:43.728157000] 0x151f24080 Made Modification 'Machine code sinking' on Function 'main'...
+0x15300f830 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis, Machine Cycle Info Analysis, Machine Natural Loop Construction
+ -- 'Machine code sinking' is not preserving 'MachineDominator Tree Construction'
+ -- 'Machine code sinking' is not preserving 'Machine Block Frequency Analysis'
+ -- 'Machine code sinking' is not preserving 'MachinePostDominator Tree Construction'
+ -*- 'Machine code sinking' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.728406000] 0x151f24080 Freeing Pass 'Machine code sinking' on Function 'main'...
+[2025-06-18 00:57:43.728447000] 0x151f24080 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.728489000] 0x151f24080 Freeing Pass 'Machine Cycle Info Analysis' on Function 'main'...
+[2025-06-18 00:57:43.728531000] 0x151f24080 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.728572000] 0x151f24080 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+Running pass: Peephole Optimizations
+[2025-06-18 00:57:43.728625000] 0x151f24080 Executing Pass 'Peephole Optimizations' on Function 'main'...
+0x141e04310 Required Analyses: Machine Module Information, Machine Natural Loop Construction
+0x141e04310 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Peephole Optimizations' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.729151000] 0x151f24080 Freeing Pass 'Peephole Optimizations' on Function 'main'...
+Running pass: Remove dead machine instructions
+[2025-06-18 00:57:43.729203000] 0x151f24080 Executing Pass 'Remove dead machine instructions' on Function 'main'...
+0x141e040b0 Required Analyses: Machine Module Information
+0x141e040b0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove dead machine instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.729675000] 0x151f24080 Freeing Pass 'Remove dead machine instructions' on Function 'main'...
+Running pass: AArch64 MI Peephole Optimization pass
+[2025-06-18 00:57:43.729727000] 0x151f24080 Executing Pass 'AArch64 MI Peephole Optimization pass' on Function 'main'...
+0x141e04120 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x141e04120 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 MI Peephole Optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.730254000] 0x151f24080 Freeing Pass 'AArch64 MI Peephole Optimization pass' on Function 'main'...
+Running pass: AArch64 Dead register definitions
+[2025-06-18 00:57:43.730307000] 0x151f24080 Executing Pass 'AArch64 Dead register definitions' on Function 'main'...
+0x141e046a0 Required Analyses: Machine Module Information
+0x141e046a0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Dead register definitions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.730778000] 0x151f24080 Freeing Pass 'AArch64 Dead register definitions' on Function 'main'...
+Running pass: Detect Dead Lanes
+[2025-06-18 00:57:43.730830000] 0x151f24080 Executing Pass 'Detect Dead Lanes' on Function 'main'...
+0x141e043c0 Required Analyses: Machine Module Information
+0x141e043c0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Detect Dead Lanes' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.731305000] 0x151f24080 Freeing Pass 'Detect Dead Lanes' on Function 'main'...
+Running pass: Init Undef Pass
+[2025-06-18 00:57:43.731356000] 0x151f24080 Executing Pass 'Init Undef Pass' on Function 'main'...
+0x141e04840 Required Analyses: Machine Module Information
+0x141e04840 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Init Undef Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.731839000] 0x151f24080 Freeing Pass 'Init Undef Pass' on Function 'main'...
+Running pass: Process Implicit Definitions
+[2025-06-18 00:57:43.731890000] 0x151f24080 Executing Pass 'Process Implicit Definitions' on Function 'main'...
+0x141e04930 Required Analyses: Machine Module Information
+0x141e04930 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Function Alias Analysis Results, Machine Module Information, Uninitialized Pass, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Process Implicit Definitions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.732368000] 0x151f24080 Freeing Pass 'Process Implicit Definitions' on Function 'main'...
+Running pass: Remove unreachable machine basic blocks
+[2025-06-18 00:57:43.732422000] 0x151f24080 Executing Pass 'Remove unreachable machine basic blocks' on Function 'main'...
+0x141e04400 Required Analyses: Machine Module Information
+0x141e04400 Preserved Analyses: Machine Natural Loop Construction, MachineDominator Tree Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Variable Analysis
+[2025-06-18 00:57:43.732643000] 0x151f24080 Executing Pass 'Live Variable Analysis' on Function 'main'...
+0x15300da30 Required Analyses: Remove unreachable machine basic blocks, Machine Module Information
+0x15300da30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Eliminate PHI nodes for register allocation
+[2025-06-18 00:57:43.732878000] 0x151f24080 Executing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+0x15300fa20 Required Analyses: Machine Module Information
+0x15300fa20 Preserved Analyses: Live Variable Analysis, Slot index numbering, Live Interval Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x15300fa20 Used Analyses: Live Variable Analysis
+ -*- 'Eliminate PHI nodes for register allocation' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.733166000] 0x151f24080 Freeing Pass 'Eliminate PHI nodes for register allocation' on Function 'main'...
+[2025-06-18 00:57:43.733208000] 0x151f24080 Freeing Pass 'Remove unreachable machine basic blocks' on Function 'main'...
+Running pass: Two-Address instruction pass
+[2025-06-18 00:57:43.733259000] 0x151f24080 Executing Pass 'Two-Address instruction pass' on Function 'main'...
+0x15300db30 Required Analyses: Machine Module Information
+0x15300db30 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Live Variable Analysis, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x15300db30 Used Analyses: Function Alias Analysis Results, Live Variable Analysis
+ -*- 'Two-Address instruction pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.733794000] 0x151f24080 Freeing Pass 'Two-Address instruction pass' on Function 'main'...
+[2025-06-18 00:57:43.733835000] 0x151f24080 Freeing Pass 'Live Variable Analysis' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:43.733887000] 0x151f24080 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x1530104a0 Required Analyses: Machine Module Information
+0x1530104a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Slot index numbering
+[2025-06-18 00:57:43.734097000] 0x151f24080 Executing Pass 'Slot index numbering' on Function 'main'...
+0x15300ffd0 Required Analyses: Machine Module Information
+0x15300ffd0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Interval Analysis
+[2025-06-18 00:57:43.734319000] 0x151f24080 Executing Pass 'Live Interval Analysis' on Function 'main'...
+0x15300fde0 Required Analyses: MachineDominator Tree Construction, Slot index numbering, Machine Module Information
+0x15300fde0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Live Variable Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Register Coalescer
+[2025-06-18 00:57:43.734835000] 0x151f24080 Executing Pass 'Register Coalescer' on Function 'main'...
+0x15300db70 Required Analyses: Live Interval Analysis, Machine Natural Loop Construction, Machine Module Information
+[2025-06-18 00:57:43.735075000] 0x151f24080 Made Modification 'Register Coalescer' on Function 'main'...
+0x15300db70 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+0x15300db70 Used Analyses: Slot index numbering
+ -*- 'Register Coalescer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.735560000] 0x151f24080 Freeing Pass 'Register Coalescer' on Function 'main'...
+Running pass: Rename Disconnected Subregister Components
+[2025-06-18 00:57:43.735612000] 0x151f24080 Executing Pass 'Rename Disconnected Subregister Components' on Function 'main'...
+0x1530101c0 Required Analyses: Live Interval Analysis, Slot index numbering, Machine Module Information
+0x1530101c0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Rename Disconnected Subregister Components' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.736141000] 0x151f24080 Freeing Pass 'Rename Disconnected Subregister Components' on Function 'main'...
+Running pass: Machine Instruction Scheduler
+[2025-06-18 00:57:43.736193000] 0x151f24080 Executing Pass 'Machine Instruction Scheduler' on Function 'main'...
+0x153010600 Required Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Function Alias Analysis Results, Target Pass Configuration, Slot index numbering, Live Interval Analysis, Machine Module Information
+[2025-06-18 00:57:43.737812000] 0x151f24080 Made Modification 'Machine Instruction Scheduler' on Function 'main'...
+0x153010600 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Slot index numbering, Live Interval Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Instruction Scheduler' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.738273000] 0x151f24080 Freeing Pass 'Machine Instruction Scheduler' on Function 'main'...
+Running pass: AArch64 Post Coalescer pass
+[2025-06-18 00:57:43.738325000] 0x151f24080 Executing Pass 'AArch64 Post Coalescer pass' on Function 'main'...
+0x153010930 Required Analyses: Live Interval Analysis, Machine Module Information
+0x153010930 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Post Coalescer pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.738557000] 0x151f24080 Freeing Pass 'AArch64 Post Coalescer pass' on Function 'main'...
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:43.738608000] 0x151f24080 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x1530105c0 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x1530105c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Debug Variable Analysis
+[2025-06-18 00:57:43.738829000] 0x151f24080 Executing Pass 'Debug Variable Analysis' on Function 'main'...
+0x141e04470 Required Analyses: MachineDominator Tree Construction, Live Interval Analysis, Machine Module Information
+0x141e04470 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Stack Slot Analysis
+[2025-06-18 00:57:43.739200000] 0x151f24080 Executing Pass 'Live Stack Slot Analysis' on Function 'main'...
+0x141e04a30 Required Analyses: Slot index numbering, Machine Module Information
+0x141e04a30 Preserved Analyses: Slot index numbering, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Virtual Register Map
+[2025-06-18 00:57:43.740085000] 0x151f24080 Executing Pass 'Virtual Register Map' on Function 'main'...
+0x141e05020 Required Analyses: Machine Module Information
+0x141e05020 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Live Register Matrix
+[2025-06-18 00:57:43.740290000] 0x151f24080 Executing Pass 'Live Register Matrix' on Function 'main'...
+0x141e04b90 Required Analyses: Live Interval Analysis, Virtual Register Map, Machine Module Information
+0x141e04b90 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Bundle Machine CFG Edges
+[2025-06-18 00:57:43.741192000] 0x151f24080 Executing Pass 'Bundle Machine CFG Edges' on Function 'main'...
+0x141e04d50 Required Analyses: Machine Module Information
+0x141e04d50 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Spill Code Placement Analysis
+[2025-06-18 00:57:43.741388000] 0x151f24080 Executing Pass 'Spill Code Placement Analysis' on Function 'main'...
+0x141e050e0 Required Analyses: Machine Block Frequency Analysis, Bundle Machine CFG Edges, Machine Module Information
+0x141e050e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.741629000] 0x151f24080 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x141e05300 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x141e05300 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:43.741835000] 0x151f24080 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x141e052c0 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x141e052c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Greedy Register Allocator
+[2025-06-18 00:57:43.742041000] 0x151f24080 Executing Pass 'Greedy Register Allocator' on Function 'main'...
+0x153010980 Required Analyses: Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, MachineDominator Tree Construction, Machine Natural Loop Construction, Virtual Register Map, Live Register Matrix, Bundle Machine CFG Edges, Spill Code Placement Analysis, Machine Optimization Remark Emitter, Regalloc eviction policy, Regalloc priority policy, Machine Module Information
+0x153010980 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, Virtual Register Map, Live Register Matrix, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Greedy Register Allocator' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.742718000] 0x151f24080 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.742760000] 0x151f24080 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.742802000] 0x151f24080 Freeing Pass 'Greedy Register Allocator' on Function 'main'...
+[2025-06-18 00:57:43.742862000] 0x151f24080 Freeing Pass 'Spill Code Placement Analysis' on Function 'main'...
+[2025-06-18 00:57:43.742904000] 0x151f24080 Freeing Pass 'Bundle Machine CFG Edges' on Function 'main'...
+Running pass: Virtual Register Rewriter
+[2025-06-18 00:57:43.742956000] 0x151f24080 Executing Pass 'Virtual Register Rewriter' on Function 'main'...
+0x141e05360 Required Analyses: Live Interval Analysis, Slot index numbering, Debug Variable Analysis, Live Stack Slot Analysis, Virtual Register Map, Live Register Matrix, Machine Module Information
+[2025-06-18 00:57:43.744008000] 0x151f24080 Made Modification 'Virtual Register Rewriter' on Function 'main'...
+0x141e05360 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Live Interval Analysis, Slot index numbering, Live Stack Slot Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -- 'Virtual Register Rewriter' is not preserving 'Live Register Matrix'
+ -- 'Virtual Register Rewriter' is not preserving 'Debug Variable Analysis'
+ -- 'Virtual Register Rewriter' is not preserving 'Virtual Register Map'
+ -*- 'Virtual Register Rewriter' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.744538000] 0x151f24080 Freeing Pass 'Debug Variable Analysis' on Function 'main'...
+[2025-06-18 00:57:43.744579000] 0x151f24080 Freeing Pass 'Live Register Matrix' on Function 'main'...
+[2025-06-18 00:57:43.744622000] 0x151f24080 Freeing Pass 'Live Interval Analysis' on Function 'main'...
+[2025-06-18 00:57:43.744664000] 0x151f24080 Freeing Pass 'Virtual Register Map' on Function 'main'...
+[2025-06-18 00:57:43.744706000] 0x151f24080 Freeing Pass 'Virtual Register Rewriter' on Function 'main'...
+Running pass: Register Allocation Pass Scoring
+[2025-06-18 00:57:43.744761000] 0x151f24080 Executing Pass 'Register Allocation Pass Scoring' on Function 'main'...
+0x141e054f0 Required Analyses: Regalloc eviction policy, Regalloc priority policy, Machine Block Frequency Analysis, Machine Module Information
+0x141e054f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Register Allocation Pass Scoring' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.744991000] 0x151f24080 Freeing Pass 'Register Allocation Pass Scoring' on Function 'main'...
+Running pass: Stack Slot Coloring
+[2025-06-18 00:57:43.745042000] 0x151f24080 Executing Pass 'Stack Slot Coloring' on Function 'main'...
+0x141e055d0 Required Analyses: Slot index numbering, Live Stack Slot Analysis, Machine Block Frequency Analysis, Machine Module Information
+0x141e055d0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Slot index numbering, Live Interval Analysis, Debug Variable Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Slot Coloring' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.745738000] 0x151f24080 Freeing Pass 'Live Stack Slot Analysis' on Function 'main'...
+[2025-06-18 00:57:43.745782000] 0x151f24080 Freeing Pass 'Slot index numbering' on Function 'main'...
+[2025-06-18 00:57:43.745824000] 0x151f24080 Freeing Pass 'Stack Slot Coloring' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:57:43.745875000] 0x151f24080 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x141e056f0 Required Analyses: Machine Module Information
+0x141e056f0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.746406000] 0x151f24080 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Machine Loop Invariant Code Motion
+[2025-06-18 00:57:43.746458000] 0x151f24080 Executing Pass 'Machine Loop Invariant Code Motion' on Function 'main'...
+0x141e05630 Required Analyses: Machine Natural Loop Construction, Machine Block Frequency Analysis, MachineDominator Tree Construction, Function Alias Analysis Results, Machine Module Information
+0x141e05630 Preserved Analyses: Machine Natural Loop Construction, Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Loop Invariant Code Motion' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.746750000] 0x151f24080 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:43.746791000] 0x151f24080 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.746833000] 0x151f24080 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.746874000] 0x151f24080 Freeing Pass 'Machine Loop Invariant Code Motion' on Function 'main'...
+Running pass: AArch64 Redundant Copy Elimination
+[2025-06-18 00:57:43.746925000] 0x151f24080 Executing Pass 'AArch64 Redundant Copy Elimination' on Function 'main'...
+0x141e057a0 Required Analyses: Machine Module Information
+0x141e057a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Redundant Copy Elimination' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.747136000] 0x151f24080 Freeing Pass 'AArch64 Redundant Copy Elimination' on Function 'main'...
+Running pass: A57 FP Anti-dependency breaker
+[2025-06-18 00:57:43.747188000] 0x151f24080 Executing Pass 'A57 FP Anti-dependency breaker' on Function 'main'...
+0x141e05a80 Required Analyses: Machine Module Information
+0x141e05a80 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'A57 FP Anti-dependency breaker' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.747658000] 0x151f24080 Freeing Pass 'A57 FP Anti-dependency breaker' on Function 'main'...
+Running pass: Remove Redundant DEBUG_VALUE analysis
+[2025-06-18 00:57:43.747710000] 0x151f24080 Executing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+0x141e05c30 Required Analyses: Machine Module Information
+0x141e05c30 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Redundant DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.748966000] 0x151f24080 Freeing Pass 'Remove Redundant DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Fixup Statepoint Caller Saved
+[2025-06-18 00:57:43.749020000] 0x151f24080 Executing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+0x141e05590 Required Analyses: Machine Module Information
+0x141e05590 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Fixup Statepoint Caller Saved' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.749485000] 0x151f24080 Freeing Pass 'Fixup Statepoint Caller Saved' on Function 'main'...
+Running pass: PostRA Machine Sink
+[2025-06-18 00:57:43.749536000] 0x151f24080 Executing Pass 'PostRA Machine Sink' on Function 'main'...
+0x141e05e20 Required Analyses: Machine Module Information
+0x141e05e20 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'PostRA Machine Sink' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.750000000] 0x151f24080 Freeing Pass 'PostRA Machine Sink' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:43.750064000] 0x151f24080 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x141e06230 Required Analyses: Machine Module Information
+0x141e06230 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:43.750602000] 0x151f24080 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x141e06160 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x141e06160 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:43.750812000] 0x151f24080 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x141e05ff0 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x141e05ff0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:57:43.751034000] 0x151f24080 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x141e062f0 Required Analyses: Machine Module Information
+0x141e062f0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.751234000] 0x151f24080 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x141e063d0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x141e063d0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:43.751444000] 0x151f24080 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x141e06030 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x141e06030 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Shrink Wrapping analysis
+[2025-06-18 00:57:43.751650000] 0x151f24080 Executing Pass 'Shrink Wrapping analysis' on Function 'main'...
+0x141e05f30 Required Analyses: Machine Block Frequency Analysis, MachineDominator Tree Construction, MachinePostDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Machine Module Information
+0x141e05f30 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Shrink Wrapping analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.752664000] 0x151f24080 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.752707000] 0x151f24080 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.752757000] 0x151f24080 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.752807000] 0x151f24080 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:43.752848000] 0x151f24080 Freeing Pass 'Shrink Wrapping analysis' on Function 'main'...
+Running pass: Prologue/Epilogue Insertion & Frame Finalization
+[2025-06-18 00:57:43.752899000] 0x151f24080 Executing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x141e05f70 Required Analyses: Machine Optimization Remark Emitter, Machine Module Information
+[2025-06-18 00:57:43.754447000] 0x151f24080 Made Modification 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+0x141e05f70 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Prologue/Epilogue Insertion & Frame Finalization' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.754891000] 0x151f24080 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.754932000] 0x151f24080 Freeing Pass 'Prologue/Epilogue Insertion & Frame Finalization' on Function 'main'...
+Running pass: Machine Late Instructions Cleanup Pass
+[2025-06-18 00:57:43.754984000] 0x151f24080 Executing Pass 'Machine Late Instructions Cleanup Pass' on Function 'main'...
+0x141e064b0 Required Analyses: Machine Module Information
+0x141e064b0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Late Instructions Cleanup Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.756684000] 0x151f24080 Freeing Pass 'Machine Late Instructions Cleanup Pass' on Function 'main'...
+Running pass: Control Flow Optimizer
+[2025-06-18 00:57:43.756736000] 0x151f24080 Executing Pass 'Control Flow Optimizer' on Function 'main'...
+0x141e06a80 Required Analyses: Machine Block Frequency Analysis, Machine Branch Probability Analysis, Profile summary info, Target Pass Configuration, Machine Module Information
+0x141e06a80 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Control Flow Optimizer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.756981000] 0x151f24080 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.757023000] 0x151f24080 Freeing Pass 'Control Flow Optimizer' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.757075000] 0x151f24080 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x141e06bb0 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x141e06bb0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Tail Duplication
+[2025-06-18 00:57:43.757282000] 0x151f24080 Executing Pass 'Tail Duplication' on Function 'main'...
+0x141e06ac0 Required Analyses: Machine Branch Probability Analysis, Lazy Machine Block Frequency Analysis, Profile summary info, Machine Module Information
+0x141e06ac0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Tail Duplication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.757512000] 0x151f24080 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.757553000] 0x151f24080 Freeing Pass 'Tail Duplication' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:57:43.757604000] 0x151f24080 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x141e06550 Required Analyses: Machine Module Information
+0x141e06550 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.758221000] 0x151f24080 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Post-RA pseudo instruction expansion pass
+[2025-06-18 00:57:43.758273000] 0x151f24080 Executing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+0x141e065e0 Required Analyses: Machine Module Information
+0x141e065e0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Post-RA pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.758754000] 0x151f24080 Freeing Pass 'Post-RA pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 pseudo instruction expansion pass
+[2025-06-18 00:57:43.758806000] 0x151f24080 Executing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x141e06670 Required Analyses: Machine Module Information
+[2025-06-18 00:57:43.759856000] 0x151f24080 Made Modification 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+0x141e06670 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 pseudo instruction expansion pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.760038000] 0x151f24080 Freeing Pass 'AArch64 pseudo instruction expansion pass' on Function 'main'...
+Running pass: AArch64 load / store optimization pass
+[2025-06-18 00:57:43.760092000] 0x151f24080 Executing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+0x141e066b0 Required Analyses: Function Alias Analysis Results, Machine Module Information
+0x141e066b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 load / store optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.760838000] 0x151f24080 Freeing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+Running pass: Insert KCFI indirect call checks
+[2025-06-18 00:57:43.760891000] 0x151f24080 Executing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+0x141e06830 Required Analyses: Machine Module Information
+0x141e06830 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert KCFI indirect call checks' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.761095000] 0x151f24080 Freeing Pass 'Insert KCFI indirect call checks' on Function 'main'...
+Running pass: AArch64 speculation hardening pass
+[2025-06-18 00:57:43.761147000] 0x151f24080 Executing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+0x141e06c10 Required Analyses: Machine Module Information
+0x141e06c10 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 speculation hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.761349000] 0x151f24080 Freeing Pass 'AArch64 speculation hardening pass' on Function 'main'...
+Running pass: MachineDominator Tree Construction
+[2025-06-18 00:57:43.761401000] 0x151f24080 Executing Pass 'MachineDominator Tree Construction' on Function 'main'...
+0x141e06f00 Required Analyses: Machine Module Information
+0x141e06f00 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Natural Loop Construction
+[2025-06-18 00:57:43.761605000] 0x151f24080 Executing Pass 'Machine Natural Loop Construction' on Function 'main'...
+0x141e06dd0 Required Analyses: MachineDominator Tree Construction, Machine Module Information
+0x141e06dd0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Falkor HW Prefetch Fix Late Phase
+[2025-06-18 00:57:43.761820000] 0x151f24080 Executing Pass 'Falkor HW Prefetch Fix Late Phase' on Function 'main'...
+0x141e06d30 Required Analyses: Machine Natural Loop Construction, Machine Module Information
+0x141e06d30 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Falkor HW Prefetch Fix Late Phase' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.762327000] 0x151f24080 Freeing Pass 'Falkor HW Prefetch Fix Late Phase' on Function 'main'...
+Running pass: PostRA Machine Instruction Scheduler
+[2025-06-18 00:57:43.762379000] 0x151f24080 Executing Pass 'PostRA Machine Instruction Scheduler' on Function 'main'...
+0x141e06fe0 Required Analyses: MachineDominator Tree Construction, Machine Natural Loop Construction, Function Alias Analysis Results, Target Pass Configuration, Machine Module Information
+0x141e06fe0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'PostRA Machine Instruction Scheduler' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.762892000] 0x151f24080 Freeing Pass 'MachineDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.762934000] 0x151f24080 Freeing Pass 'PostRA Machine Instruction Scheduler' on Function 'main'...
+Running pass: Analyze Machine Code For Garbage Collection
+[2025-06-18 00:57:43.762987000] 0x151f24080 Executing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+0x141e07700 Required Analyses: Machine Module Information, Create Garbage Collector Module Metadata
+0x141e07700 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Analyze Machine Code For Garbage Collection' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.763199000] 0x151f24080 Freeing Pass 'Analyze Machine Code For Garbage Collection' on Function 'main'...
+Running pass: Machine Block Frequency Analysis
+[2025-06-18 00:57:43.763251000] 0x151f24080 Executing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+0x141e07210 Required Analyses: Machine Branch Probability Analysis, Machine Natural Loop Construction, Machine Module Information
+0x141e07210 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: MachinePostDominator Tree Construction
+[2025-06-18 00:57:43.763493000] 0x151f24080 Executing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+0x141e077c0 Required Analyses: Machine Module Information
+0x141e077c0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Branch Probability Basic Block Placement
+[2025-06-18 00:57:43.763692000] 0x151f24080 Executing Pass 'Branch Probability Basic Block Placement' on Function 'main'...
+0x141e07750 Required Analyses: Machine Branch Probability Analysis, Machine Block Frequency Analysis, MachinePostDominator Tree Construction, Machine Natural Loop Construction, Profile summary info, Target Pass Configuration, Machine Module Information
+0x141e07750 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch Probability Basic Block Placement' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.763958000] 0x151f24080 Freeing Pass 'Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.764012000] 0x151f24080 Freeing Pass 'MachinePostDominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.764054000] 0x151f24080 Freeing Pass 'Machine Natural Loop Construction' on Function 'main'...
+[2025-06-18 00:57:43.764096000] 0x151f24080 Freeing Pass 'Branch Probability Basic Block Placement' on Function 'main'...
+Running pass: Insert fentry calls
+[2025-06-18 00:57:43.764148000] 0x151f24080 Executing Pass 'Insert fentry calls' on Function 'main'...
+0x141e071b0 Required Analyses: Machine Module Information
+0x141e071b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert fentry calls' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.764351000] 0x151f24080 Freeing Pass 'Insert fentry calls' on Function 'main'...
+Running pass: Insert XRay ops
+[2025-06-18 00:57:43.764402000] 0x151f24080 Executing Pass 'Insert XRay ops' on Function 'main'...
+0x141e07290 Required Analyses: Machine Module Information
+0x141e07290 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert XRay ops' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.765099000] 0x151f24080 Freeing Pass 'Insert XRay ops' on Function 'main'...
+Running pass: Implement the 'patchable-function' attribute
+[2025-06-18 00:57:43.765152000] 0x151f24080 Executing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+0x141e073e0 Required Analyses: Machine Module Information
+0x141e073e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Implement the 'patchable-function' attribute' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.765355000] 0x151f24080 Freeing Pass 'Implement the 'patchable-function' attribute' on Function 'main'...
+Running pass: AArch64 load / store optimization pass
+[2025-06-18 00:57:43.765406000] 0x151f24080 Executing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+0x141e07460 Required Analyses: Function Alias Analysis Results, Machine Module Information
+0x141e07460 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 load / store optimization pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.765620000] 0x151f24080 Freeing Pass 'Function Alias Analysis Results' on Function 'main'...
+[2025-06-18 00:57:43.765661000] 0x151f24080 Freeing Pass 'Basic Alias Analysis (stateless AA impl)' on Function 'main'...
+[2025-06-18 00:57:43.765703000] 0x151f24080 Freeing Pass 'Dominator Tree Construction' on Function 'main'...
+[2025-06-18 00:57:43.765745000] 0x151f24080 Freeing Pass 'AArch64 load / store optimization pass' on Function 'main'...
+Running pass: Machine Copy Propagation Pass
+[2025-06-18 00:57:43.765796000] 0x151f24080 Executing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+0x141e07420 Required Analyses: Machine Module Information
+0x141e07420 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Copy Propagation Pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.766415000] 0x151f24080 Freeing Pass 'Machine Copy Propagation Pass' on Function 'main'...
+Running pass: Workaround A53 erratum 835769 pass
+[2025-06-18 00:57:43.766490000] 0x151f24080 Executing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+0x141e078d0 Required Analyses: Machine Module Information
+0x141e078d0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Workaround A53 erratum 835769 pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.766963000] 0x151f24080 Freeing Pass 'Workaround A53 erratum 835769 pass' on Function 'main'...
+Running pass: AArch64 Collect Linker Optimization Hint (LOH)
+[2025-06-18 00:57:43.767015000] 0x151f24080 Executing Pass 'AArch64 Collect Linker Optimization Hint (LOH)' on Function 'main'...
+0x141e07960 Required Analyses: Machine Module Information
+0x141e07960 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Collect Linker Optimization Hint (LOH)' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.767218000] 0x151f24080 Freeing Pass 'AArch64 Collect Linker Optimization Hint (LOH)' on Function 'main'...
+Running pass: Contiguously Lay Out Funclets
+[2025-06-18 00:57:43.767270000] 0x151f24080 Executing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+0x141e079a0 Required Analyses: Machine Module Information
+0x141e079a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Contiguously Lay Out Funclets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.767470000] 0x151f24080 Freeing Pass 'Contiguously Lay Out Funclets' on Function 'main'...
+Running pass: Remove Loads Into Fake Uses
+[2025-06-18 00:57:43.767522000] 0x151f24080 Executing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+0x141e07a10 Required Analyses: Machine Module Information
+0x141e07a10 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Remove Loads Into Fake Uses' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.768023000] 0x151f24080 Freeing Pass 'Remove Loads Into Fake Uses' on Function 'main'...
+Running pass: StackMap Liveness Analysis
+[2025-06-18 00:57:43.768075000] 0x151f24080 Executing Pass 'StackMap Liveness Analysis' on Function 'main'...
+0x141e07a70 Required Analyses: Machine Module Information
+0x141e07a70 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'StackMap Liveness Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.768542000] 0x151f24080 Freeing Pass 'StackMap Liveness Analysis' on Function 'main'...
+Running pass: Live DEBUG_VALUE analysis
+[2025-06-18 00:57:43.768595000] 0x151f24080 Executing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+0x141e07fd0 Required Analyses: Target Pass Configuration, Machine Module Information
+0x141e07fd0 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Live DEBUG_VALUE analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.770632000] 0x151f24080 Freeing Pass 'Live DEBUG_VALUE analysis' on Function 'main'...
+Running pass: Machine Sanitizer Binary Metadata
+[2025-06-18 00:57:43.770687000] 0x151f24080 Executing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+0x141e081b0 Required Analyses: Machine Module Information
+0x141e081b0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Machine Sanitizer Binary Metadata' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.770910000] 0x151f24080 Freeing Pass 'Machine Sanitizer Binary Metadata' on Function 'main'...
+[2025-06-18 00:57:43.770952000] 0x153005ad0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.771008000] 0x153005ad0 Freeing Pass 'Assumption Cache Tracker' on Module 'test.c'...
+[2025-06-18 00:57:43.771050000] 0x153005ad0 Freeing Pass 'Profile summary info' on Module 'test.c'...
+[2025-06-18 00:57:43.771091000] 0x153005ad0 Freeing Pass 'Scoped NoAlias Alias Analysis' on Module 'test.c'...
+[2025-06-18 00:57:43.771133000] 0x153005ad0 Freeing Pass 'Type-Based Alias Analysis' on Module 'test.c'...
+[2025-06-18 00:57:43.771174000] 0x153005ad0 Freeing Pass 'Default Regalloc Eviction Advisor' on Module 'test.c'...
+[2025-06-18 00:57:43.771215000] 0x153005ad0 Freeing Pass 'Default Regalloc Priority Advisor' on Module 'test.c'...
+[2025-06-18 00:57:43.771257000] 0x153005ad0 Freeing Pass 'Target Library Information' on Module 'test.c'...
+[2025-06-18 00:57:43.771298000] 0x153005ad0 Freeing Pass 'Target Pass Configuration' on Module 'test.c'...
+Running pass: Machine Outliner
+[2025-06-18 00:57:43.771349000] 0x153005ad0 Executing Pass 'Machine Outliner' on Module 'test.c'...
+0x141e07b10 Required Analyses: Machine Module Information
+0x141e07b10 Preserved Analyses: Machine Module Information
+0x141e07b10 Used Analyses: Module summary info
+ -*- 'Machine Outliner' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.771783000] 0x153005ad0 Freeing Pass 'Machine Outliner' on Module 'test.c'...
+Running pass: Function Pass Manager
+[2025-06-18 00:57:43.771835000] 0x153005ad0 Executing Pass 'Function Pass Manager' on Module 'test.c'...
+Running pass: AArch64 sls hardening pass
+[2025-06-18 00:57:43.771888000] 0x141e08260 Executing Pass 'AArch64 sls hardening pass' on Function 'main'...
+0x141e07b60 Required Analyses: Machine Module Information
+0x141e07b60 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 sls hardening pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.772092000] 0x141e08260 Freeing Pass 'AArch64 sls hardening pass' on Function 'main'...
+Running pass: AArch64 Pointer Authentication
+[2025-06-18 00:57:43.772143000] 0x141e08260 Executing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+0x141e07ce0 Required Analyses: Machine Module Information
+0x141e07ce0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Pointer Authentication' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.772365000] 0x141e08260 Freeing Pass 'AArch64 Pointer Authentication' on Function 'main'...
+Running pass: AArch64 Branch Targets
+[2025-06-18 00:57:43.772418000] 0x141e08260 Executing Pass 'AArch64 Branch Targets' on Function 'main'...
+0x141e07d80 Required Analyses: Machine Module Information
+0x141e07d80 Preserved Analyses: Machine Cycle Info Analysis, Machine Dominance Frontier Construction, MachineDominator Tree Construction, Machine Natural Loop Construction, Machine Optimization Remark Emitter, Print Machine Cycle Info Analysis, MachinePostDominator Tree Construction, Print Machine Uniformity Info Analysis, Detect single entry single exit regions, Assign reference type allocas to local address space, Spill Code Placement Analysis, Dominator Tree Construction, Analysis if a function is memory bound, Basic Alias Analysis (stateless AA impl), Block Frequency Analysis, Cycle Info Analysis, SPIRV module analysis, WebAssembly Exception Information, Lazy Branch Probability Analysis, Lazy Block Frequency Analysis, Natural Loop Information, Post-Dominator Tree Construction, Uniformity Analysis, Function register usage analysis, , Bundle Machine CFG Edges, Lazy Machine Block Frequency Analysis, SPIRV convergence regions analysis, Machine Block Frequency Analysis, Machine Module Information, Uninitialized Pass, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Branch Targets' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.772884000] 0x141e08260 Freeing Pass 'AArch64 Branch Targets' on Function 'main'...
+Running pass: Branch relaxation pass
+[2025-06-18 00:57:43.772936000] 0x141e08260 Executing Pass 'Branch relaxation pass' on Function 'main'...
+0x141e07dc0 Required Analyses: Machine Module Information
+0x141e07dc0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Branch relaxation pass' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.773138000] 0x141e08260 Freeing Pass 'Branch relaxation pass' on Function 'main'...
+Running pass: AArch64 Compress Jump Tables
+[2025-06-18 00:57:43.773190000] 0x141e08260 Executing Pass 'AArch64 Compress Jump Tables' on Function 'main'...
+0x141e083e0 Required Analyses: Machine Module Information
+0x141e083e0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Compress Jump Tables' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.773390000] 0x141e08260 Freeing Pass 'AArch64 Compress Jump Tables' on Function 'main'...
+Running pass: Insert CFI remember/restore state instructions
+[2025-06-18 00:57:43.773441000] 0x141e08260 Executing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+0x141e07e20 Required Analyses: Machine Module Information
+0x141e07e20 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Insert CFI remember/restore state instructions' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.773803000] 0x141e08260 Freeing Pass 'Insert CFI remember/restore state instructions' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.773855000] 0x141e08260 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x141e08540 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x141e08540 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:43.774065000] 0x141e08260 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x141e08500 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x141e08500 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Stack Frame Layout Analysis
+[2025-06-18 00:57:43.774273000] 0x141e08260 Executing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+0x141e08460 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter
+0x141e08460 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Stack Frame Layout Analysis' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.774488000] 0x141e08260 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.774529000] 0x141e08260 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.774571000] 0x141e08260 Freeing Pass 'Stack Frame Layout Analysis' on Function 'main'...
+Running pass: Unpack machine instruction bundles
+[2025-06-18 00:57:43.774622000] 0x141e08260 Executing Pass 'Unpack machine instruction bundles' on Function 'main'...
+0x141e084a0 Required Analyses: Machine Module Information
+0x141e084a0 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'Unpack machine instruction bundles' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.774821000] 0x141e08260 Freeing Pass 'Unpack machine instruction bundles' on Function 'main'...
+Running pass: Lazy Machine Block Frequency Analysis
+[2025-06-18 00:57:43.774873000] 0x141e08260 Executing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+0x153010a40 Required Analyses: Machine Branch Probability Analysis, Machine Module Information
+0x153010a40 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: Machine Optimization Remark Emitter
+[2025-06-18 00:57:43.775099000] 0x141e08260 Executing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+0x153011250 Required Analyses: Lazy Machine Block Frequency Analysis, Machine Module Information
+0x153011250 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+Running pass: AArch64 Assembly Printer
+[2025-06-18 00:57:43.775309000] 0x141e08260 Executing Pass 'AArch64 Assembly Printer' on Function 'main'...
+0x151f25250 Required Analyses: Machine Module Information, Machine Optimization Remark Emitter, Create Garbage Collector Module Metadata, Lazy Machine Block Frequency Analysis, Machine Branch Probability Analysis
+0x151f25250 Preserved Analyses: Machine Module Information, Basic Alias Analysis (stateless AA impl), Uninitialized Pass, Dominator Tree Construction, Function Alias Analysis Results, Globals Alias Analysis, Induction Variable Users, Natural Loop Information, Memory Dependence Analysis, Scalar Evolution Analysis, ScalarEvolution-based Alias Analysis
+ -*- 'AArch64 Assembly Printer' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.778212000] 0x141e08260 Freeing Pass 'Machine Optimization Remark Emitter' on Function 'main'...
+[2025-06-18 00:57:43.778254000] 0x141e08260 Freeing Pass 'Lazy Machine Block Frequency Analysis' on Function 'main'...
+[2025-06-18 00:57:43.778296000] 0x141e08260 Freeing Pass 'AArch64 Assembly Printer' on Function 'main'...
+Running pass: Free MachineFunction
+[2025-06-18 00:57:43.778366000] 0x141e08260 Executing Pass 'Free MachineFunction' on Function 'main'...
+0x153011150 Required Analyses: Machine Module Information
+[2025-06-18 00:57:43.778449000] 0x141e08260 Made Modification 'Free MachineFunction' on Function 'main'...
+0x153011150 Preserved Analyses: Machine Module Information
+ -- 'Free MachineFunction' is not preserving 'Function Pass Manager'
+ -*- 'Free MachineFunction' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.778551000] 0x141e08260 Freeing Pass 'Free MachineFunction' on Function 'main'...
+[2025-06-18 00:57:43.778596000] 0x153005ad0 Made Modification 'Function Pass Manager' on Module 'test.c'...
+ -*- 'Function Pass Manager' is the last user of following pass instances. Free these instances
+[2025-06-18 00:57:43.778653000] 0x153005ad0 Freeing Pass 'Create Garbage Collector Module Metadata' on Module 'test.c'...
+[2025-06-18 00:57:43.778696000] 0x153005ad0 Freeing Pass 'Machine Branch Probability Analysis' on Module 'test.c'...
+[2025-06-18 00:57:43.778739000] 0x153005ad0 Freeing Pass 'Machine Module Information' on Module 'test.c'...
+ld: library not found for -lSystem
+clang: error: linker command failed with exit code 1 (use -v to see invocation)
diff --git a/print_after_all_new.txt b/print_after_all_new.txt
new file mode 100644
index 0000000000000..f23549554adb0
--- /dev/null
+++ b/print_after_all_new.txt
@@ -0,0 +1,4385 @@
+; *** IR Dump After EntryExitInstrumenterPass on main ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+; *** IR Dump After AlwaysInlinerPass on [module] ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+; *** IR Dump After CoroConditionalWrapper on [module] ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+; *** IR Dump After AnnotationRemarksPass on main ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+*** IR Dump After Expand large div/rem (expand-large-div-rem) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Expand fp (expand-fp) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Expand Atomic instructions (atomic-expand) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Lower Garbage Collection Instructions (gc-lowering) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Shadow Stack GC Lowering (shadow-stack-gc-lowering) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Lower @llvm.global_dtors via `__cxa_atexit` (lower-global-dtors) ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+*** IR Dump After Remove unreachable blocks from the CFG (unreachableblockelim) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Instrument function entry/exit with calls to e.g. mcount() (post inlining) (post-inline-ee-instrument) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Expand reduction intrinsics (expand-reductions) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After AArch64 Stack Tagging (aarch64-stack-tagging) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After SME ABI Pass (aarch64-sme-abi) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Exception handling preparation (dwarf-eh-prepare) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Prepare callbr (callbrprepare) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump After Safe Stack instrumentation pass (safe-stack) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+# *** IR Dump After IRTranslator (irtranslator) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %11:_(s32) = G_CONSTANT i32 0
+ %12:_(s32) = G_CONSTANT i32 5
+ %13:_(s32) = G_CONSTANT i32 10
+ %17:_(s32) = G_CONSTANT i32 100
+ %18:_(s32) = G_CONSTANT i32 200
+ %25:_(s32) = G_CONSTANT i32 15
+ %30:_(s32) = G_CONSTANT i32 2
+ %33:_(s32) = G_CONSTANT i32 1
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ %10:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %27:_(s1) = G_ICMP intpred(slt), %26:_(s32), %13:_
+ G_BRCOND %27:_(s1), %bb.3
+ G_BR %bb.5
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %31:_(s32) = nsw G_MUL %29:_, %30:_
+ G_STORE %31:_(s32), %10:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %34:_(s32) = nsw G_ADD %32:_, %33:_
+ G_STORE %34:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:_(s32) = G_LOAD %3:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64O0PreLegalizerCombiner (aarch64-O0-prelegalizer-combiner) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %11:_(s32) = G_CONSTANT i32 0
+ %12:_(s32) = G_CONSTANT i32 5
+ %13:_(s32) = G_CONSTANT i32 10
+ %17:_(s32) = G_CONSTANT i32 100
+ %18:_(s32) = G_CONSTANT i32 200
+ %25:_(s32) = G_CONSTANT i32 15
+ %30:_(s32) = G_CONSTANT i32 2
+ %33:_(s32) = G_CONSTANT i32 1
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ %10:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %27:_(s1) = G_ICMP intpred(sge), %26:_(s32), %13:_
+ %35:_(s1) = G_CONSTANT i1 true
+ G_BRCOND %27:_(s1), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %37:_(s32) = G_CONSTANT i32 1
+ %31:_(s32) = nsw G_SHL %29:_, %37:_(s32)
+ G_STORE %31:_(s32), %10:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %34:_(s32) = nsw G_ADD %32:_, %33:_
+ G_STORE %34:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:_(s32) = G_LOAD %3:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Localizer (localizer) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %30:_(s32) = G_CONSTANT i32 2
+ %33:_(s32) = G_CONSTANT i32 1
+ %10:_(p0) = G_FRAME_INDEX %stack.10
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %11:_(s32) = G_CONSTANT i32 0
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %12:_(s32) = G_CONSTANT i32 5
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %13:_(s32) = G_CONSTANT i32 10
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %17:_(s32) = G_CONSTANT i32 100
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %18:_(s32) = G_CONSTANT i32 200
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %25:_(s32) = G_CONSTANT i32 15
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:_(p0) = G_FRAME_INDEX %stack.9
+ %26:_(s32) = G_LOAD %39:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:_(s32) = G_CONSTANT i32 10
+ %27:_(s1) = G_ICMP intpred(sge), %26:_(s32), %44:_
+ %35:_(s1) = G_CONSTANT i1 true
+ G_BRCOND %27:_(s1), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:_(p0) = G_FRAME_INDEX %stack.9
+ %29:_(s32) = G_LOAD %40:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %37:_(s32) = G_CONSTANT i32 1
+ %31:_(s32) = nsw G_SHL %29:_, %37:_(s32)
+ %38:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:_(s32), %38:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:_(p0) = G_FRAME_INDEX %stack.9
+ %32:_(s32) = G_LOAD %41:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:_(s32) = G_CONSTANT i32 1
+ %34:_(s32) = nsw G_ADD %32:_, %43:_
+ G_STORE %34:_(s32), %41:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:_(p0) = G_FRAME_INDEX %stack.3
+ %28:_(s32) = G_LOAD %42:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Legalizer (legalizer) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %11:_(s32) = G_CONSTANT i32 0
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %12:_(s32) = G_CONSTANT i32 5
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %13:_(s32) = G_CONSTANT i32 10
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %17:_(s32) = G_CONSTANT i32 100
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %18:_(s32) = G_CONSTANT i32 200
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %25:_(s32) = G_CONSTANT i32 15
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:_(p0) = G_FRAME_INDEX %stack.9
+ %26:_(s32) = G_LOAD %39:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:_(s32) = G_CONSTANT i32 10
+ %47:_(s32) = G_ICMP intpred(sge), %26:_(s32), %44:_
+ G_BRCOND %47:_(s32), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:_(p0) = G_FRAME_INDEX %stack.9
+ %29:_(s32) = G_LOAD %40:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %45:_(s64) = G_CONSTANT i64 1
+ %31:_(s32) = nsw G_SHL %29:_, %45:_(s64)
+ %38:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:_(s32), %38:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:_(p0) = G_FRAME_INDEX %stack.9
+ %32:_(s32) = G_LOAD %41:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:_(s32) = G_CONSTANT i32 1
+ %34:_(s32) = nsw G_ADD %32:_, %43:_
+ G_STORE %34:_(s32), %41:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:_(p0) = G_FRAME_INDEX %stack.3
+ %28:_(s32) = G_LOAD %42:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64PostLegalizerLowering (aarch64-postlegalizer-lowering) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %11:_(s32) = G_CONSTANT i32 0
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %12:_(s32) = G_CONSTANT i32 5
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %13:_(s32) = G_CONSTANT i32 10
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %17:_(s32) = G_CONSTANT i32 100
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %18:_(s32) = G_CONSTANT i32 200
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %25:_(s32) = G_CONSTANT i32 15
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:_(p0) = G_FRAME_INDEX %stack.9
+ %26:_(s32) = G_LOAD %39:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:_(s32) = G_CONSTANT i32 10
+ %47:_(s32) = G_ICMP intpred(sge), %26:_(s32), %44:_
+ G_BRCOND %47:_(s32), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:_(p0) = G_FRAME_INDEX %stack.9
+ %29:_(s32) = G_LOAD %40:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %45:_(s64) = G_CONSTANT i64 1
+ %31:_(s32) = nsw G_SHL %29:_, %45:_(s64)
+ %38:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:_(s32), %38:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:_(p0) = G_FRAME_INDEX %stack.9
+ %32:_(s32) = G_LOAD %41:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:_(s32) = G_CONSTANT i32 1
+ %34:_(s32) = nsw G_ADD %32:_, %43:_
+ G_STORE %34:_(s32), %41:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:_(p0) = G_FRAME_INDEX %stack.3
+ %28:_(s32) = G_LOAD %42:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After RegBankSelect (regbankselect) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %0:gpr(p0) = G_FRAME_INDEX %stack.0
+ %11:gpr(s32) = G_CONSTANT i32 0
+ G_STORE %11:gpr(s32), %0:gpr(p0) :: (store (s32) into %ir.1)
+ %1:gpr(p0) = G_FRAME_INDEX %stack.1
+ %12:gpr(s32) = G_CONSTANT i32 5
+ G_STORE %12:gpr(s32), %1:gpr(p0) :: (store (s32) into %ir.2)
+ %2:gpr(p0) = G_FRAME_INDEX %stack.2
+ %13:gpr(s32) = G_CONSTANT i32 10
+ G_STORE %13:gpr(s32), %2:gpr(p0) :: (store (s32) into %ir.3)
+ %14:gpr(s32) = G_LOAD %1:gpr(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr(s32) = G_LOAD %2:gpr(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr(s32) = nsw G_ADD %14:gpr, %15:gpr
+ %3:gpr(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:gpr(s32), %3:gpr(p0) :: (store (s32) into %ir.4)
+ %4:gpr(p0) = G_FRAME_INDEX %stack.4
+ %17:gpr(s32) = G_CONSTANT i32 100
+ G_STORE %17:gpr(s32), %4:gpr(p0) :: (store (s32) into %ir.5)
+ %5:gpr(p0) = G_FRAME_INDEX %stack.5
+ %18:gpr(s32) = G_CONSTANT i32 200
+ G_STORE %18:gpr(s32), %5:gpr(p0) :: (store (s32) into %ir.6)
+ %19:gpr(s32) = G_LOAD %4:gpr(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr(s32) = G_LOAD %5:gpr(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr(s32) = nsw G_ADD %19:gpr, %20:gpr
+ %6:gpr(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:gpr(s32), %6:gpr(p0) :: (store (s32) into %ir.7)
+ %22:gpr(s32) = G_LOAD %1:gpr(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr(s32) = G_LOAD %2:gpr(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr(s32) = nsw G_ADD %22:gpr, %23:gpr
+ %7:gpr(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:gpr(s32), %7:gpr(p0) :: (store (s32) into %ir.8)
+ %8:gpr(p0) = G_FRAME_INDEX %stack.8
+ %25:gpr(s32) = G_CONSTANT i32 15
+ G_STORE %25:gpr(s32), %8:gpr(p0) :: (store (s32) into %ir.9)
+ %9:gpr(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:gpr(s32), %9:gpr(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:gpr(p0) = G_FRAME_INDEX %stack.9
+ %26:gpr(s32) = G_LOAD %39:gpr(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:gpr(s32) = G_CONSTANT i32 10
+ %47:gpr(s32) = G_ICMP intpred(sge), %26:gpr(s32), %44:gpr
+ G_BRCOND %47:gpr(s32), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:gpr(p0) = G_FRAME_INDEX %stack.9
+ %29:gpr(s32) = G_LOAD %40:gpr(p0) :: (dereferenceable load (s32) from %ir.10)
+ %45:gpr(s64) = G_CONSTANT i64 1
+ %31:gpr(s32) = nsw G_SHL %29:gpr, %45:gpr(s64)
+ %38:gpr(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:gpr(s32), %38:gpr(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:gpr(p0) = G_FRAME_INDEX %stack.9
+ %32:gpr(s32) = G_LOAD %41:gpr(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:gpr(s32) = G_CONSTANT i32 1
+ %34:gpr(s32) = nsw G_ADD %32:gpr, %43:gpr
+ G_STORE %34:gpr(s32), %41:gpr(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:gpr(p0) = G_FRAME_INDEX %stack.3
+ %28:gpr(s32) = G_LOAD %42:gpr(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After InstructionSelect (instruction-select) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 Instruction Selection (aarch64-isel) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Finalize ISel and expand pseudo-instructions (finalize-isel) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Local Stack Slot Allocation (localstackalloc) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Eliminate PHI nodes for register allocation (phi-node-elimination) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Two-Address instruction pass (twoaddressinstruction) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Fast Register Allocator (regallocfast) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, %stack.1, 0 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, %stack.2, 0 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.3, 0 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, %stack.4, 0 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, %stack.5, 0 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.6, 0 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.7, 0 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Remove Redundant DEBUG_VALUE analysis (removeredundantdebugvalues) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, %stack.1, 0 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, %stack.2, 0 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.3, 0 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, %stack.4, 0 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, %stack.5, 0 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.6, 0 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.7, 0 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Fixup Statepoint Caller Saved (fixup-statepoint-caller-saved) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, %stack.1, 0 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, %stack.2, 0 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.3, 0 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, %stack.4, 0 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, %stack.5, 0 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.6, 0 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.7, 0 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Post-RA pseudo instruction expansion pass (postrapseudos) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 pseudo instruction expansion pass (aarch64-expand-pseudo) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Insert KCFI indirect call checks (kcfi) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 speculation hardening pass (aarch64-speculation-hardening) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Analyze Machine Code For Garbage Collection (gc-analysis) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Insert fentry calls (fentry-insert) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Insert XRay ops (xray-instrumentation) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Implement the 'patchable-function' attribute (patchable-function) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Workaround A53 erratum 835769 pass (aarch64-fix-cortex-a53-835769-pass) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Contiguously Lay Out Funclets (funclet-layout) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Remove Loads Into Fake Uses (remove-loads-into-fake-uses) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After StackMap Liveness Analysis (stackmap-liveness) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Live DEBUG_VALUE analysis (livedebugvalues) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Machine Sanitizer Binary Metadata (machine-sanmd) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 sls hardening pass (aarch64-sls-hardening) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 Pointer Authentication (aarch64-ptrauth) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 Branch Targets (aarch64-branch-targets) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Branch relaxation pass (branch-relaxation) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Insert CFI remember/restore state instructions (cfi-fixup) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Stack Frame Layout Analysis (stack-frame-layout) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After Unpack machine instruction bundles (unpack-mi-bundles) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump After AArch64 Assembly Printer (aarch64-asm-printer) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
diff --git a/print_before_all_new.txt b/print_before_all_new.txt
new file mode 100644
index 0000000000000..24e31e5ee6135
--- /dev/null
+++ b/print_before_all_new.txt
@@ -0,0 +1,4310 @@
+; *** IR Dump Before EntryExitInstrumenterPass on main ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+; *** IR Dump Before AlwaysInlinerPass on [module] ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+; *** IR Dump Before CoroConditionalWrapper on [module] ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+; *** IR Dump Before AnnotationRemarksPass on main ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Pre-ISel Intrinsic Lowering (pre-isel-intrinsic-lowering) ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+*** IR Dump Before Expand large div/rem (expand-large-div-rem) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Expand fp (expand-fp) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Expand Atomic instructions (atomic-expand) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Lower Garbage Collection Instructions (gc-lowering) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Shadow Stack GC Lowering (shadow-stack-gc-lowering) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Lower @llvm.global_dtors via `__cxa_atexit` (lower-global-dtors) ***
+; ModuleID = 'test.c'
+source_filename = "test.c"
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "arm64-apple-macosx13.0.0"
+
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+
+attributes #0 = { noinline nounwind optnone ssp uwtable(sync) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="apple-m1" "target-features"="+aes,+altnzcv,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fptoint,+fullfp16,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+sha3,+specrestrict,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,+zcm,+zcz" }
+
+!llvm.module.flags = !{!0, !1, !2, !3}
+!llvm.ident = !{!4}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 8, !"PIC Level", i32 2}
+!2 = !{i32 7, !"uwtable", i32 1}
+!3 = !{i32 7, !"frame-pointer", i32 1}
+!4 = !{!"clang version 21.0.0git (https://github.com/llvm/llvm-project.git fb07683bc2402a75f6a5c568cdab195b695cd322)"}
+!5 = distinct !{!5, !6}
+!6 = !{!"llvm.loop.mustprogress"}
+*** IR Dump Before Remove unreachable blocks from the CFG (unreachableblockelim) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Instrument function entry/exit with calls to e.g. mcount() (post inlining) (post-inline-ee-instrument) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Scalarize Masked Memory Intrinsics (scalarize-masked-mem-intrin) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Expand reduction intrinsics (expand-reductions) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before AArch64 Stack Tagging (aarch64-stack-tagging) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before SME ABI Pass (aarch64-sme-abi) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Exception handling preparation (dwarf-eh-prepare) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Prepare callbr (callbrprepare) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+*** IR Dump Before Safe Stack instrumentation pass (safe-stack) ***
+; Function Attrs: noinline nounwind optnone ssp uwtable(sync)
+define i32 @main() #0 {
+ %1 = alloca i32, align 4
+ %2 = alloca i32, align 4
+ %3 = alloca i32, align 4
+ %4 = alloca i32, align 4
+ %5 = alloca i32, align 4
+ %6 = alloca i32, align 4
+ %7 = alloca i32, align 4
+ %8 = alloca i32, align 4
+ %9 = alloca i32, align 4
+ %10 = alloca i32, align 4
+ %11 = alloca i32, align 4
+ store i32 0, ptr %1, align 4
+ store i32 5, ptr %2, align 4
+ store i32 10, ptr %3, align 4
+ %12 = load i32, ptr %2, align 4
+ %13 = load i32, ptr %3, align 4
+ %14 = add nsw i32 %12, %13
+ store i32 %14, ptr %4, align 4
+ store i32 100, ptr %5, align 4
+ store i32 200, ptr %6, align 4
+ %15 = load i32, ptr %5, align 4
+ %16 = load i32, ptr %6, align 4
+ %17 = add nsw i32 %15, %16
+ store i32 %17, ptr %7, align 4
+ %18 = load i32, ptr %2, align 4
+ %19 = load i32, ptr %3, align 4
+ %20 = add nsw i32 %18, %19
+ store i32 %20, ptr %8, align 4
+ store i32 15, ptr %9, align 4
+ store i32 0, ptr %10, align 4
+ br label %21
+
+21: ; preds = %27, %0
+ %22 = load i32, ptr %10, align 4
+ %23 = icmp slt i32 %22, 10
+ br i1 %23, label %24, label %30
+
+24: ; preds = %21
+ %25 = load i32, ptr %10, align 4
+ %26 = mul nsw i32 %25, 2
+ store i32 %26, ptr %11, align 4
+ br label %27
+
+27: ; preds = %24
+ %28 = load i32, ptr %10, align 4
+ %29 = add nsw i32 %28, 1
+ store i32 %29, ptr %10, align 4
+ br label %21, !llvm.loop !5
+
+30: ; preds = %21
+ %31 = load i32, ptr %4, align 4
+ ret i32 %31
+}
+# *** IR Dump Before IRTranslator (irtranslator) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64O0PreLegalizerCombiner (aarch64-O0-prelegalizer-combiner) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %11:_(s32) = G_CONSTANT i32 0
+ %12:_(s32) = G_CONSTANT i32 5
+ %13:_(s32) = G_CONSTANT i32 10
+ %17:_(s32) = G_CONSTANT i32 100
+ %18:_(s32) = G_CONSTANT i32 200
+ %25:_(s32) = G_CONSTANT i32 15
+ %30:_(s32) = G_CONSTANT i32 2
+ %33:_(s32) = G_CONSTANT i32 1
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ %10:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %27:_(s1) = G_ICMP intpred(slt), %26:_(s32), %13:_
+ G_BRCOND %27:_(s1), %bb.3
+ G_BR %bb.5
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %31:_(s32) = nsw G_MUL %29:_, %30:_
+ G_STORE %31:_(s32), %10:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %34:_(s32) = nsw G_ADD %32:_, %33:_
+ G_STORE %34:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:_(s32) = G_LOAD %3:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Localizer (localizer) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %11:_(s32) = G_CONSTANT i32 0
+ %12:_(s32) = G_CONSTANT i32 5
+ %13:_(s32) = G_CONSTANT i32 10
+ %17:_(s32) = G_CONSTANT i32 100
+ %18:_(s32) = G_CONSTANT i32 200
+ %25:_(s32) = G_CONSTANT i32 15
+ %30:_(s32) = G_CONSTANT i32 2
+ %33:_(s32) = G_CONSTANT i32 1
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ %10:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %27:_(s1) = G_ICMP intpred(sge), %26:_(s32), %13:_
+ %35:_(s1) = G_CONSTANT i1 true
+ G_BRCOND %27:_(s1), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %37:_(s32) = G_CONSTANT i32 1
+ %31:_(s32) = nsw G_SHL %29:_, %37:_(s32)
+ G_STORE %31:_(s32), %10:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:_(s32) = G_LOAD %9:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %34:_(s32) = nsw G_ADD %32:_, %33:_
+ G_STORE %34:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:_(s32) = G_LOAD %3:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Legalizer (legalizer) ***:
+# Machine code for function main: IsSSA, TracksLiveness
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %30:_(s32) = G_CONSTANT i32 2
+ %33:_(s32) = G_CONSTANT i32 1
+ %10:_(p0) = G_FRAME_INDEX %stack.10
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %11:_(s32) = G_CONSTANT i32 0
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %12:_(s32) = G_CONSTANT i32 5
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %13:_(s32) = G_CONSTANT i32 10
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %17:_(s32) = G_CONSTANT i32 100
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %18:_(s32) = G_CONSTANT i32 200
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %25:_(s32) = G_CONSTANT i32 15
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:_(p0) = G_FRAME_INDEX %stack.9
+ %26:_(s32) = G_LOAD %39:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:_(s32) = G_CONSTANT i32 10
+ %27:_(s1) = G_ICMP intpred(sge), %26:_(s32), %44:_
+ %35:_(s1) = G_CONSTANT i1 true
+ G_BRCOND %27:_(s1), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:_(p0) = G_FRAME_INDEX %stack.9
+ %29:_(s32) = G_LOAD %40:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %37:_(s32) = G_CONSTANT i32 1
+ %31:_(s32) = nsw G_SHL %29:_, %37:_(s32)
+ %38:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:_(s32), %38:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:_(p0) = G_FRAME_INDEX %stack.9
+ %32:_(s32) = G_LOAD %41:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:_(s32) = G_CONSTANT i32 1
+ %34:_(s32) = nsw G_ADD %32:_, %43:_
+ G_STORE %34:_(s32), %41:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:_(p0) = G_FRAME_INDEX %stack.3
+ %28:_(s32) = G_LOAD %42:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64PostLegalizerLowering (aarch64-postlegalizer-lowering) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %11:_(s32) = G_CONSTANT i32 0
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %12:_(s32) = G_CONSTANT i32 5
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %13:_(s32) = G_CONSTANT i32 10
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %17:_(s32) = G_CONSTANT i32 100
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %18:_(s32) = G_CONSTANT i32 200
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %25:_(s32) = G_CONSTANT i32 15
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:_(p0) = G_FRAME_INDEX %stack.9
+ %26:_(s32) = G_LOAD %39:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:_(s32) = G_CONSTANT i32 10
+ %47:_(s32) = G_ICMP intpred(sge), %26:_(s32), %44:_
+ G_BRCOND %47:_(s32), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:_(p0) = G_FRAME_INDEX %stack.9
+ %29:_(s32) = G_LOAD %40:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %45:_(s64) = G_CONSTANT i64 1
+ %31:_(s32) = nsw G_SHL %29:_, %45:_(s64)
+ %38:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:_(s32), %38:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:_(p0) = G_FRAME_INDEX %stack.9
+ %32:_(s32) = G_LOAD %41:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:_(s32) = G_CONSTANT i32 1
+ %34:_(s32) = nsw G_ADD %32:_, %43:_
+ G_STORE %34:_(s32), %41:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:_(p0) = G_FRAME_INDEX %stack.3
+ %28:_(s32) = G_LOAD %42:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before RegBankSelect (regbankselect) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %0:_(p0) = G_FRAME_INDEX %stack.0
+ %11:_(s32) = G_CONSTANT i32 0
+ G_STORE %11:_(s32), %0:_(p0) :: (store (s32) into %ir.1)
+ %1:_(p0) = G_FRAME_INDEX %stack.1
+ %12:_(s32) = G_CONSTANT i32 5
+ G_STORE %12:_(s32), %1:_(p0) :: (store (s32) into %ir.2)
+ %2:_(p0) = G_FRAME_INDEX %stack.2
+ %13:_(s32) = G_CONSTANT i32 10
+ G_STORE %13:_(s32), %2:_(p0) :: (store (s32) into %ir.3)
+ %14:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:_(s32) = nsw G_ADD %14:_, %15:_
+ %3:_(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:_(s32), %3:_(p0) :: (store (s32) into %ir.4)
+ %4:_(p0) = G_FRAME_INDEX %stack.4
+ %17:_(s32) = G_CONSTANT i32 100
+ G_STORE %17:_(s32), %4:_(p0) :: (store (s32) into %ir.5)
+ %5:_(p0) = G_FRAME_INDEX %stack.5
+ %18:_(s32) = G_CONSTANT i32 200
+ G_STORE %18:_(s32), %5:_(p0) :: (store (s32) into %ir.6)
+ %19:_(s32) = G_LOAD %4:_(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:_(s32) = G_LOAD %5:_(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:_(s32) = nsw G_ADD %19:_, %20:_
+ %6:_(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:_(s32), %6:_(p0) :: (store (s32) into %ir.7)
+ %22:_(s32) = G_LOAD %1:_(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:_(s32) = G_LOAD %2:_(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:_(s32) = nsw G_ADD %22:_, %23:_
+ %7:_(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:_(s32), %7:_(p0) :: (store (s32) into %ir.8)
+ %8:_(p0) = G_FRAME_INDEX %stack.8
+ %25:_(s32) = G_CONSTANT i32 15
+ G_STORE %25:_(s32), %8:_(p0) :: (store (s32) into %ir.9)
+ %9:_(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:_(s32), %9:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:_(p0) = G_FRAME_INDEX %stack.9
+ %26:_(s32) = G_LOAD %39:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:_(s32) = G_CONSTANT i32 10
+ %47:_(s32) = G_ICMP intpred(sge), %26:_(s32), %44:_
+ G_BRCOND %47:_(s32), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:_(p0) = G_FRAME_INDEX %stack.9
+ %29:_(s32) = G_LOAD %40:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %45:_(s64) = G_CONSTANT i64 1
+ %31:_(s32) = nsw G_SHL %29:_, %45:_(s64)
+ %38:_(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:_(s32), %38:_(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:_(p0) = G_FRAME_INDEX %stack.9
+ %32:_(s32) = G_LOAD %41:_(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:_(s32) = G_CONSTANT i32 1
+ %34:_(s32) = nsw G_ADD %32:_, %43:_
+ G_STORE %34:_(s32), %41:_(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:_(p0) = G_FRAME_INDEX %stack.3
+ %28:_(s32) = G_LOAD %42:_(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:_(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before InstructionSelect (instruction-select) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %0:gpr(p0) = G_FRAME_INDEX %stack.0
+ %11:gpr(s32) = G_CONSTANT i32 0
+ G_STORE %11:gpr(s32), %0:gpr(p0) :: (store (s32) into %ir.1)
+ %1:gpr(p0) = G_FRAME_INDEX %stack.1
+ %12:gpr(s32) = G_CONSTANT i32 5
+ G_STORE %12:gpr(s32), %1:gpr(p0) :: (store (s32) into %ir.2)
+ %2:gpr(p0) = G_FRAME_INDEX %stack.2
+ %13:gpr(s32) = G_CONSTANT i32 10
+ G_STORE %13:gpr(s32), %2:gpr(p0) :: (store (s32) into %ir.3)
+ %14:gpr(s32) = G_LOAD %1:gpr(p0) :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr(s32) = G_LOAD %2:gpr(p0) :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr(s32) = nsw G_ADD %14:gpr, %15:gpr
+ %3:gpr(p0) = G_FRAME_INDEX %stack.3
+ G_STORE %16:gpr(s32), %3:gpr(p0) :: (store (s32) into %ir.4)
+ %4:gpr(p0) = G_FRAME_INDEX %stack.4
+ %17:gpr(s32) = G_CONSTANT i32 100
+ G_STORE %17:gpr(s32), %4:gpr(p0) :: (store (s32) into %ir.5)
+ %5:gpr(p0) = G_FRAME_INDEX %stack.5
+ %18:gpr(s32) = G_CONSTANT i32 200
+ G_STORE %18:gpr(s32), %5:gpr(p0) :: (store (s32) into %ir.6)
+ %19:gpr(s32) = G_LOAD %4:gpr(p0) :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr(s32) = G_LOAD %5:gpr(p0) :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr(s32) = nsw G_ADD %19:gpr, %20:gpr
+ %6:gpr(p0) = G_FRAME_INDEX %stack.6
+ G_STORE %21:gpr(s32), %6:gpr(p0) :: (store (s32) into %ir.7)
+ %22:gpr(s32) = G_LOAD %1:gpr(p0) :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr(s32) = G_LOAD %2:gpr(p0) :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr(s32) = nsw G_ADD %22:gpr, %23:gpr
+ %7:gpr(p0) = G_FRAME_INDEX %stack.7
+ G_STORE %24:gpr(s32), %7:gpr(p0) :: (store (s32) into %ir.8)
+ %8:gpr(p0) = G_FRAME_INDEX %stack.8
+ %25:gpr(s32) = G_CONSTANT i32 15
+ G_STORE %25:gpr(s32), %8:gpr(p0) :: (store (s32) into %ir.9)
+ %9:gpr(p0) = G_FRAME_INDEX %stack.9
+ G_STORE %11:gpr(s32), %9:gpr(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %39:gpr(p0) = G_FRAME_INDEX %stack.9
+ %26:gpr(s32) = G_LOAD %39:gpr(p0) :: (dereferenceable load (s32) from %ir.10)
+ %44:gpr(s32) = G_CONSTANT i32 10
+ %47:gpr(s32) = G_ICMP intpred(sge), %26:gpr(s32), %44:gpr
+ G_BRCOND %47:gpr(s32), %bb.5
+ G_BR %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %40:gpr(p0) = G_FRAME_INDEX %stack.9
+ %29:gpr(s32) = G_LOAD %40:gpr(p0) :: (dereferenceable load (s32) from %ir.10)
+ %45:gpr(s64) = G_CONSTANT i64 1
+ %31:gpr(s32) = nsw G_SHL %29:gpr, %45:gpr(s64)
+ %38:gpr(p0) = G_FRAME_INDEX %stack.10
+ G_STORE %31:gpr(s32), %38:gpr(p0) :: (store (s32) into %ir.11)
+ G_BR %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %41:gpr(p0) = G_FRAME_INDEX %stack.9
+ %32:gpr(s32) = G_LOAD %41:gpr(p0) :: (dereferenceable load (s32) from %ir.10)
+ %43:gpr(s32) = G_CONSTANT i32 1
+ %34:gpr(s32) = nsw G_ADD %32:gpr, %43:gpr
+ G_STORE %34:gpr(s32), %41:gpr(p0) :: (store (s32) into %ir.10)
+ G_BR %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %42:gpr(p0) = G_FRAME_INDEX %stack.3
+ %28:gpr(s32) = G_LOAD %42:gpr(p0) :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr(s32)
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 Instruction Selection (aarch64-isel) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Finalize ISel and expand pseudo-instructions (finalize-isel) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Local Stack Slot Allocation (localstackalloc) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Eliminate PHI nodes for register allocation (phi-node-elimination) ***:
+# Machine code for function main: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Two-Address instruction pass (twoaddressinstruction) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Fast Register Allocator (regallocfast) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ %12:gpr32 = MOVi32imm 5
+ STRWui %12:gpr32, %stack.1, 0 :: (store (s32) into %ir.2)
+ %13:gpr32 = MOVi32imm 10
+ STRWui %13:gpr32, %stack.2, 0 :: (store (s32) into %ir.3)
+ %14:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %15:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %16:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
+ STRWui %16:gpr32, %stack.3, 0 :: (store (s32) into %ir.4)
+ %17:gpr32 = MOVi32imm 100
+ STRWui %17:gpr32, %stack.4, 0 :: (store (s32) into %ir.5)
+ %18:gpr32 = MOVi32imm 200
+ STRWui %18:gpr32, %stack.5, 0 :: (store (s32) into %ir.6)
+ %19:gpr32 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ %20:gpr32 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ %21:gpr32 = nsw ADDWrr %19:gpr32, %20:gpr32
+ STRWui %21:gpr32, %stack.6, 0 :: (store (s32) into %ir.7)
+ %22:gpr32 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ %23:gpr32 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ %24:gpr32 = nsw ADDWrr %22:gpr32, %23:gpr32
+ STRWui %24:gpr32, %stack.7, 0 :: (store (s32) into %ir.8)
+ %25:gpr32 = MOVi32imm 15
+ STRWui %25:gpr32, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ %26:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %48:gpr32 = SUBSWri %26:gpr32common, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ %29:gpr32 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %31:gpr32 = UBFMWri %29:gpr32, 31, 30
+ STRWui %31:gpr32, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ %32:gpr32common = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ %34:gpr32common = nsw ADDWri %32:gpr32common, 1, 0
+ STRWui %34:gpr32common, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ %28:gpr32 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ $w0 = COPY %28:gpr32
+ RET_ReallyLR implicit $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Remove Redundant DEBUG_VALUE analysis (removeredundantdebugvalues) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, %stack.1, 0 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, %stack.2, 0 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.3, 0 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, %stack.4, 0 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, %stack.5, 0 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.6, 0 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.7, 0 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Fixup Statepoint Caller Saved (fixup-statepoint-caller-saved) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, %stack.1, 0 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, %stack.2, 0 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.3, 0 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, %stack.4, 0 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, %stack.5, 0 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.6, 0 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.7, 0 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Prologue/Epilogue Insertion & Frame Finalization (prologepilog) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP]
+ fi#1: size=4, align=4, at location [SP]
+ fi#2: size=4, align=4, at location [SP]
+ fi#3: size=4, align=4, at location [SP]
+ fi#4: size=4, align=4, at location [SP]
+ fi#5: size=4, align=4, at location [SP]
+ fi#6: size=4, align=4, at location [SP]
+ fi#7: size=4, align=4, at location [SP]
+ fi#8: size=4, align=4, at location [SP]
+ fi#9: size=4, align=4, at location [SP]
+ fi#10: size=4, align=4, at location [SP]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ STRWui $wzr, %stack.0, 0 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, %stack.1, 0 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, %stack.2, 0 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.3, 0 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, %stack.4, 0 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, %stack.5, 0 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui %stack.4, 0 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui %stack.5, 0 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.6, 0 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui %stack.1, 0 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui %stack.2, 0 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, %stack.7, 0 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, %stack.8, 0 :: (store (s32) into %ir.9)
+ STRWui $wzr, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, %stack.10, 0 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui %stack.9, 0 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, %stack.9, 0 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui %stack.3, 0 :: (dereferenceable load (s32) from %ir.4)
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Post-RA pseudo instruction expansion pass (postrapseudos) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 pseudo instruction expansion pass (aarch64-expand-pseudo) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVi32imm 5
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVi32imm 10
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVi32imm 100
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVi32imm 200
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ renamable $w8 = nsw ADDWrr killed renamable $w8, killed renamable $w9
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVi32imm 15
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET_ReallyLR implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Insert KCFI indirect call checks (kcfi) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 speculation hardening pass (aarch64-speculation-hardening) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Analyze Machine Code For Garbage Collection (gc-analysis) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Insert fentry calls (fentry-insert) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Insert XRay ops (xray-instrumentation) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Implement the 'patchable-function' attribute (patchable-function) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Workaround A53 erratum 835769 pass (aarch64-fix-cortex-a53-835769-pass) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Contiguously Lay Out Funclets (funclet-layout) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Remove Loads Into Fake Uses (remove-loads-into-fake-uses) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before StackMap Liveness Analysis (stackmap-liveness) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Live DEBUG_VALUE analysis (livedebugvalues) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Machine Sanitizer Binary Metadata (machine-sanmd) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 sls hardening pass (aarch64-sls-hardening) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 Pointer Authentication (aarch64-ptrauth) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 Branch Targets (aarch64-branch-targets) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Branch relaxation pass (branch-relaxation) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.1 (%ir-block.0):
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.2 (%ir-block.21):
+; predecessors: %bb.1, %bb.4
+ successors: %bb.3, %bb.5
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.5, implicit killed $nzcv
+ B %bb.3
+
+bb.3 (%ir-block.24):
+; predecessors: %bb.2
+ successors: %bb.4(0x80000000); %bb.4(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.4
+
+bb.4 (%ir-block.27):
+; predecessors: %bb.3
+ successors: %bb.2(0x80000000); %bb.2(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.2
+
+bb.5 (%ir-block.30):
+; predecessors: %bb.2
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Insert CFI remember/restore state instructions (cfi-fixup) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Stack Frame Layout Analysis (stack-frame-layout) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before Unpack machine instruction bundles (unpack-mi-bundles) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+# *** IR Dump Before AArch64 Assembly Printer (aarch64-asm-printer) ***:
+# Machine code for function main: NoPHIs, TracksLiveness, NoVRegs, Legalized, RegBankSelected, Selected, TiedOpsRewritten
+Frame Objects:
+ fi#0: size=4, align=4, at location [SP-4]
+ fi#1: size=4, align=4, at location [SP-8]
+ fi#2: size=4, align=4, at location [SP-12]
+ fi#3: size=4, align=4, at location [SP-16]
+ fi#4: size=4, align=4, at location [SP-20]
+ fi#5: size=4, align=4, at location [SP-24]
+ fi#6: size=4, align=4, at location [SP-28]
+ fi#7: size=4, align=4, at location [SP-32]
+ fi#8: size=4, align=4, at location [SP-36]
+ fi#9: size=4, align=4, at location [SP-40]
+ fi#10: size=4, align=4, at location [SP-44]
+
+bb.0 (%ir-block.0):
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ $sp = frame-setup SUBXri $sp, 48, 0
+ frame-setup CFI_INSTRUCTION def_cfa_offset <mcsymbol >48
+ STRWui $wzr, $sp, 11 :: (store (s32) into %ir.1)
+ renamable $w8 = MOVZWi 5, 0
+ STRWui killed renamable $w8, $sp, 10 :: (store (s32) into %ir.2)
+ renamable $w8 = MOVZWi 10, 0
+ STRWui killed renamable $w8, $sp, 9 :: (store (s32) into %ir.3)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 8 :: (store (s32) into %ir.4)
+ renamable $w8 = MOVZWi 100, 0
+ STRWui killed renamable $w8, $sp, 7 :: (store (s32) into %ir.5)
+ renamable $w8 = MOVZWi 200, 0
+ STRWui killed renamable $w8, $sp, 6 :: (store (s32) into %ir.6)
+ renamable $w8 = LDRWui $sp, 7 :: (dereferenceable load (s32) from %ir.5)
+ renamable $w9 = LDRWui $sp, 6 :: (dereferenceable load (s32) from %ir.6)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 5 :: (store (s32) into %ir.7)
+ renamable $w8 = LDRWui $sp, 10 :: (dereferenceable load (s32) from %ir.2)
+ renamable $w9 = LDRWui $sp, 9 :: (dereferenceable load (s32) from %ir.3)
+ $w8 = ADDWrs killed renamable $w8, killed renamable $w9, 0
+ STRWui killed renamable $w8, $sp, 4 :: (store (s32) into %ir.8)
+ renamable $w8 = MOVZWi 15, 0
+ STRWui killed renamable $w8, $sp, 3 :: (store (s32) into %ir.9)
+ STRWui $wzr, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.1 (%ir-block.21):
+; predecessors: %bb.0, %bb.3
+ successors: %bb.2, %bb.4
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ dead renamable $w8 = SUBSWri killed renamable $w8, 10, 0, implicit-def $nzcv
+ Bcc 10, %bb.4, implicit killed $nzcv
+ B %bb.2
+
+bb.2 (%ir-block.24):
+; predecessors: %bb.1
+ successors: %bb.3(0x80000000); %bb.3(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = UBFMWri killed renamable $w8, 31, 30
+ STRWui killed renamable $w8, $sp, 1 :: (store (s32) into %ir.11)
+ B %bb.3
+
+bb.3 (%ir-block.27):
+; predecessors: %bb.2
+ successors: %bb.1(0x80000000); %bb.1(100.00%)
+
+ renamable $w8 = LDRWui $sp, 2 :: (dereferenceable load (s32) from %ir.10)
+ renamable $w8 = nsw ADDWri killed renamable $w8, 1, 0
+ STRWui killed renamable $w8, $sp, 2 :: (store (s32) into %ir.10)
+ B %bb.1
+
+bb.4 (%ir-block.30):
+; predecessors: %bb.1
+
+ renamable $w0 = LDRWui $sp, 8 :: (dereferenceable load (s32) from %ir.4)
+ $sp = frame-destroy ADDXri $sp, 48, 0
+ RET undef $lr, implicit killed $w0
+
+# End machine code for function main.
+
+ld: library not found for -lSystem
+clang: error: linker command failed with exit code 1 (use -v to see invocation)
diff --git a/structure_new.txt b/structure_new.txt
new file mode 100644
index 0000000000000..41dd162688d9d
--- /dev/null
+++ b/structure_new.txt
@@ -0,0 +1,87 @@
+Pass Arguments: -tti -targetlibinfo -targetpassconfig -machinemoduleinfo -collector-metadata -profile-summary-info -assumption-cache-tracker -machine-branch-prob -pre-isel-intrinsic-lowering -expand-large-div-rem -expand-fp -atomic-expand -gc-lowering -shadow-stack-gc-lowering -lower-global-dtors -unreachableblockelim -post-inline-ee-instrument -scalarize-masked-mem-intrin -expand-reductions -domtree -loops -lazy-branch-prob -lazy-block-freq -opt-remark-emitter -aarch64-stack-tagging -aarch64-sme-abi -dwarf-eh-prepare -callbrprepare -safe-stack -stack-protector -cseinfo -irtranslator -gisel-known-bits -aarch64-O0-prelegalizer-combiner -localizer -cseinfo -gisel-known-bits -legalizer -aarch64-postlegalizer-lowering -regbankselect -gisel-known-bits -instruction-select -debug-ata -aarch64-isel -finalize-isel -localstackalloc -phi-node-elimination -twoaddressinstruction -regallocfast -removeredundantdebugvalues -fixup-statepoint-caller-saved -lazy-machine-block-freq -machine-opt-remark-emitter -prologepilog -postrapseudos -aarch64-expand-pseudo -kcfi -aarch64-speculation-hardening -gc-analysis -fentry-insert -xray-instrumentation -patchable-function -aarch64-fix-cortex-a53-835769-pass -funclet-layout -remove-loads-into-fake-uses -stackmap-liveness -livedebugvalues -machine-sanmd -aarch64-sls-hardening -aarch64-ptrauth -aarch64-branch-targets -branch-relaxation -cfi-fixup -lazy-machine-block-freq -machine-opt-remark-emitter -stack-frame-layout -unpack-mi-bundles -lazy-machine-block-freq -machine-opt-remark-emitter -aarch64-asm-printer
+Target Transform Information
+Target Library Information
+Target Pass Configuration
+Machine Module Information
+Create Garbage Collector Module Metadata
+Profile summary info
+Assumption Cache Tracker
+Machine Branch Probability Analysis
+ ModulePass Manager
+ Pre-ISel Intrinsic Lowering
+ FunctionPass Manager
+ Expand large div/rem
+ Expand fp
+ Expand Atomic instructions
+ Lower Garbage Collection Instructions
+ Shadow Stack GC Lowering
+ Lower @llvm.global_dtors via `__cxa_atexit`
+ FunctionPass Manager
+ Remove unreachable blocks from the CFG
+ Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+ Scalarize Masked Memory Intrinsics
+ Expand reduction intrinsics
+ Dominator Tree Construction
+ Natural Loop Information
+ Lazy Branch Probability Analysis
+ Lazy Block Frequency Analysis
+ Optimization Remark Emitter
+ AArch64 Stack Tagging
+ SME ABI Pass
+ Exception handling preparation
+ Prepare callbr
+ Safe Stack instrumentation pass
+ Insert stack protectors
+ Analysis containing CSE Info
+ IRTranslator
+ Analysis for ComputingKnownBits
+ AArch64O0PreLegalizerCombiner
+ Localizer
+ Analysis containing CSE Info
+ Analysis for ComputingKnownBits
+ Legalizer
+ AArch64PostLegalizerLowering
+ RegBankSelect
+ Analysis for ComputingKnownBits
+ InstructionSelect
+ ResetMachineFunction
+ Assignment Tracking Analysis
+ AArch64 Instruction Selection
+ Finalize ISel and expand pseudo-instructions
+ Local Stack Slot Allocation
+ Eliminate PHI nodes for register allocation
+ Two-Address instruction pass
+ Fast Register Allocator
+ Remove Redundant DEBUG_VALUE analysis
+ Fixup Statepoint Caller Saved
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Prologue/Epilogue Insertion & Frame Finalization
+ Post-RA pseudo instruction expansion pass
+ AArch64 pseudo instruction expansion pass
+ Insert KCFI indirect call checks
+ AArch64 speculation hardening pass
+ Analyze Machine Code For Garbage Collection
+ Insert fentry calls
+ Insert XRay ops
+ Implement the 'patchable-function' attribute
+ Workaround A53 erratum 835769 pass
+ Contiguously Lay Out Funclets
+ Remove Loads Into Fake Uses
+ StackMap Liveness Analysis
+ Live DEBUG_VALUE analysis
+ Machine Sanitizer Binary Metadata
+ AArch64 sls hardening pass
+ AArch64 Pointer Authentication
+ AArch64 Branch Targets
+ Branch relaxation pass
+ Insert CFI remember/restore state instructions
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ Stack Frame Layout Analysis
+ Unpack machine instruction bundles
+ Lazy Machine Block Frequency Analysis
+ Machine Optimization Remark Emitter
+ AArch64 Assembly Printer
+ Free MachineFunction
+
diff --git a/test.c b/test.c
new file mode 100644
index 0000000000000..7f23e067e3de8
--- /dev/null
+++ b/test.c
@@ -0,0 +1,21 @@
+int main() {
+ int a = 5;
+ int b = 10;
+ int c = a + b;
+
+ // Dead code that should be eliminated
+ int dead1 = 100;
+ int dead2 = 200;
+ int dead3 = dead1 + dead2; // This is never used
+
+ // Redundant calculations
+ int x = a + b; // Same as c
+ int y = 5 + 10; // Constant folding opportunity
+
+ // Unused loop
+ for (int i = 0; i < 10; i++) {
+ int temp = i * 2; // Dead code in loop
+ }
+
+ return c;
+}
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