[llvm] [WebAssembly] Refactor PerformSETCCCombine (PR #144875)
via llvm-commits
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Thu Jun 19 04:18:27 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-webassembly
Author: Sam Parker (sparker-arm)
<details>
<summary>Changes</summary>
Extract the logic into a templated helper function.
---
Full diff: https://github.com/llvm/llvm-project/pull/144875.diff
1 Files Affected:
- (modified) llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (+57-31)
``````````diff
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 3cd923c0ba058..605efd97938d8 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -3239,50 +3239,76 @@ static SDValue performBitcastCombine(SDNode *N,
return SDValue();
}
-static SDValue performSETCCCombine(SDNode *N,
- TargetLowering::DAGCombinerInfo &DCI) {
- auto &DAG = DCI.DAG;
+template <int MatchRHS, ISD::CondCode MatchCond, bool RequiresNegate,
+ Intrinsic::ID Intrin>
+static SDValue TryMatchTrue(SDNode *N, SelectionDAG &DAG) {
+ EVT VT = N->getValueType(0);
+ if (!VT.isScalarInteger())
+ return SDValue();
SDValue LHS = N->getOperand(0);
- SDValue RHS = N->getOperand(1);
ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
+ if (MatchCond != Cond || LHS->getOpcode() != ISD::BITCAST)
+ return SDValue();
+
+ SDValue RHS = N->getOperand(1);
+ if (auto ConstantRHS = cast<ConstantSDNode>(RHS)) {
+ if (ConstantRHS->getSExtValue() != MatchRHS)
+ return SDValue();
+ } else {
+ return SDValue();
+ }
+
+ EVT FromVT = LHS->getOperand(0).getValueType();
+ if (!FromVT.isFixedLengthVector() || FromVT.getVectorElementType() != MVT::i1)
+ return SDValue();
+
+ unsigned NumElts = FromVT.getVectorNumElements();
+ if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
+ return SDValue();
+
SDLoc DL(N);
- EVT VT = N->getValueType(0);
+ EVT Width = MVT::getIntegerVT(128 / NumElts);
+ SDValue Ret = DAG.getZExtOrTrunc(
+ DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+ {DAG.getConstant(Intrin, DL, MVT::i32),
+ DAG.getSExtOrTrunc(LHS->getOperand(0), DL,
+ FromVT.changeVectorElementType(Width))}),
+ DL, MVT::i1);
+ if (RequiresNegate)
+ Ret = DAG.getNOT(DL, Ret, MVT::i1);
+ return DAG.getZExtOrTrunc(Ret, DL, VT);
+}
+
+static SDValue performSETCCCombine(SDNode *N,
+ TargetLowering::DAGCombinerInfo &DCI) {
+ if (!DCI.isBeforeLegalize())
+ return SDValue();
+ auto &DAG = DCI.DAG;
// setcc (iN (bitcast (vNi1 X))), 0, ne
// ==> any_true (vNi1 X)
+ if (auto Match =
+ TryMatchTrue<0, ISD::SETNE, false, Intrinsic::wasm_anytrue>(N, DAG)) {
+ return Match;
+ }
// setcc (iN (bitcast (vNi1 X))), 0, eq
// ==> xor (any_true (vNi1 X)), -1
+ if (auto Match =
+ TryMatchTrue<0, ISD::SETEQ, true, Intrinsic::wasm_anytrue>(N, DAG)) {
+ return Match;
+ }
// setcc (iN (bitcast (vNi1 X))), -1, eq
// ==> all_true (vNi1 X)
+ if (auto Match = TryMatchTrue<-1, ISD::SETEQ, false, Intrinsic::wasm_alltrue>(
+ N, DAG)) {
+ return Match;
+ }
// setcc (iN (bitcast (vNi1 X))), -1, ne
// ==> xor (all_true (vNi1 X)), -1
- if (DCI.isBeforeLegalize() && VT.isScalarInteger() &&
- (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
- (isNullConstant(RHS) || isAllOnesConstant(RHS)) &&
- LHS->getOpcode() == ISD::BITCAST) {
- EVT FromVT = LHS->getOperand(0).getValueType();
- if (FromVT.isFixedLengthVector() &&
- FromVT.getVectorElementType() == MVT::i1) {
- int Intrin = isNullConstant(RHS) ? Intrinsic::wasm_anytrue
- : Intrinsic::wasm_alltrue;
- unsigned NumElts = FromVT.getVectorNumElements();
- if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
- return SDValue();
- EVT Width = MVT::getIntegerVT(128 / NumElts);
- SDValue Ret = DAG.getZExtOrTrunc(
- DAG.getNode(
- ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
- {DAG.getConstant(Intrin, DL, MVT::i32),
- DAG.getSExtOrTrunc(LHS->getOperand(0), DL,
- FromVT.changeVectorElementType(Width))}),
- DL, MVT::i1);
- if ((isNullConstant(RHS) && (Cond == ISD::SETEQ)) ||
- (isAllOnesConstant(RHS) && (Cond == ISD::SETNE))) {
- Ret = DAG.getNOT(DL, Ret, MVT::i1);
- }
- return DAG.getZExtOrTrunc(Ret, DL, VT);
- }
+ if (auto Match =
+ TryMatchTrue<-1, ISD::SETNE, true, Intrinsic::wasm_alltrue>(N, DAG)) {
+ return Match;
}
return SDValue();
``````````
</details>
https://github.com/llvm/llvm-project/pull/144875
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