[llvm] [X86][GlobalIsel] G_BITCAST support (PR #144473)
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Thu Jun 19 03:58:48 PDT 2025
https://github.com/mahesh-attarde updated https://github.com/llvm/llvm-project/pull/144473
>From 7e9a3d8b4316c0c597958a74a6706bde2d2116f5 Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Tue, 17 Jun 2025 00:50:28 -0700
Subject: [PATCH 1/2] add bitcast
---
.../lib/Target/X86/GISel/X86LegalizerInfo.cpp | 19 +++++++++++++++++++
llvm/lib/Target/X86/GISel/X86LegalizerInfo.h | 2 ++
llvm/test/CodeGen/X86/bitcast.ll | 19 +++++++++++++++++++
3 files changed, 40 insertions(+)
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index 11dd05c584983..85e6c190c7ced 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -669,6 +669,8 @@ bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
return legalizeSITOFP(MI, MRI, Helper);
case TargetOpcode::G_FPTOSI:
return legalizeFPTOSI(MI, MRI, Helper);
+ case TargetOpcode::G_BITCAST:
+ return legalizeBitcast(MI, MRI, Helper);
}
llvm_unreachable("expected switch to return");
}
@@ -835,6 +837,23 @@ bool X86LegalizerInfo::legalizeNarrowingStore(MachineInstr &MI,
return true;
}
+bool X86LegalizerInfo::legalizeBitcast(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ LegalizerHelper &Helper) const {
+ MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+ auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
+ assert(!SrcTy.isVector() && "G_BITCAST does not support vectors yet");
+ bool isCopy =
+ (SrcTy == DstTy) || (SrcTy.getSizeInBits() == DstTy.getSizeInBits());
+ if (isCopy) {
+ MIRBuilder.buildCopy(DstReg, SrcReg);
+ MI.eraseFromParent();
+ return true;
+ }
+ // For Vectors specific bitcasts
+ return Helper.lowerBitcast(MI) == LegalizerHelper::LegalizeResult::Legalized;
+}
+
bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
return true;
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
index 1ba82674ed4c6..eb42126d079fb 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
@@ -54,6 +54,8 @@ class X86LegalizerInfo : public LegalizerInfo {
bool legalizeFPTOSI(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
+ bool legalizeBitcast(MachineInstr &MI, MachineRegisterInfo &MRI,
+ LegalizerHelper &Helper) const;
};
} // namespace llvm
#endif
diff --git a/llvm/test/CodeGen/X86/bitcast.ll b/llvm/test/CodeGen/X86/bitcast.ll
index 0866a0b1b2bd1..c5ee877a57be9 100644
--- a/llvm/test/CodeGen/X86/bitcast.ll
+++ b/llvm/test/CodeGen/X86/bitcast.ll
@@ -1,23 +1,42 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=i686--
; RUN: llc < %s -mtriple=x86_64--
+; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=GISEL
+; XRUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=GISEL
; PR1033
define i64 @test1(double %t) {
+; GISEL-LABEL: test1:
+; GISEL: # %bb.0:
+; GISEL-NEXT: movq %xmm0, %rax
+; GISEL-NEXT: retq
%u = bitcast double %t to i64 ; <i64> [#uses=1]
ret i64 %u
}
define double @test2(i64 %t) {
+; GISEL-LABEL: test2:
+; GISEL: # %bb.0:
+; GISEL-NEXT: movq %rdi, %xmm0
+; GISEL-NEXT: retq
%u = bitcast i64 %t to double ; <double> [#uses=1]
ret double %u
}
define i32 @test3(float %t) {
+; GISEL-LABEL: test3:
+; GISEL: # %bb.0:
+; GISEL-NEXT: movd %xmm0, %eax
+; GISEL-NEXT: retq
%u = bitcast float %t to i32 ; <i32> [#uses=1]
ret i32 %u
}
define float @test4(i32 %t) {
+; GISEL-LABEL: test4:
+; GISEL: # %bb.0:
+; GISEL-NEXT: movd %edi, %xmm0
+; GISEL-NEXT: retq
%u = bitcast i32 %t to float ; <float> [#uses=1]
ret float %u
}
>From 7c9a415272186fc2e05415aaa05df73793ceecb3 Mon Sep 17 00:00:00 2001
From: mattarde <mattarde at intel.com>
Date: Thu, 19 Jun 2025 03:57:39 -0700
Subject: [PATCH 2/2] fix test
---
llvm/test/CodeGen/X86/bitcast.ll | 56 ++++++++++++++++++++------------
1 file changed, 35 insertions(+), 21 deletions(-)
diff --git a/llvm/test/CodeGen/X86/bitcast.ll b/llvm/test/CodeGen/X86/bitcast.ll
index c5ee877a57be9..c9193fed0ed5c 100644
--- a/llvm/test/CodeGen/X86/bitcast.ll
+++ b/llvm/test/CodeGen/X86/bitcast.ll
@@ -1,43 +1,57 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=i686--
-; RUN: llc < %s -mtriple=x86_64--
-; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=GISEL
-; XRUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=GISEL
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s -check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64--| FileCheck %s -check-prefixes=X64
+; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=0 | FileCheck %s -check-prefixes=X86
+; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=X64
; PR1033
define i64 @test1(double %t) {
-; GISEL-LABEL: test1:
-; GISEL: # %bb.0:
-; GISEL-NEXT: movq %xmm0, %rax
-; GISEL-NEXT: retq
+; X64-LABEL: test1:
+; X64: # %bb.0:
+; X64-NEXT: movq %xmm0, %rax
+; X64-NEXT: retq
%u = bitcast double %t to i64 ; <i64> [#uses=1]
ret i64 %u
}
define double @test2(i64 %t) {
-; GISEL-LABEL: test2:
-; GISEL: # %bb.0:
-; GISEL-NEXT: movq %rdi, %xmm0
-; GISEL-NEXT: retq
+; X86-LABEL: test2:
+; X86: # %bb.0:
+; X86-NEXT: fldl {{[0-9]+}}(%esp)
+; X86-NEXT: retl
+;
+; X64-LABEL: test2:
+; X64: # %bb.0:
+; X64-NEXT: movq %rdi, %xmm0
+; X64-NEXT: retq
%u = bitcast i64 %t to double ; <double> [#uses=1]
ret double %u
}
define i32 @test3(float %t) {
-; GISEL-LABEL: test3:
-; GISEL: # %bb.0:
-; GISEL-NEXT: movd %xmm0, %eax
-; GISEL-NEXT: retq
+; X86-LABEL: test3:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: test3:
+; X64: # %bb.0:
+; X64-NEXT: movd %xmm0, %eax
+; X64-NEXT: retq
%u = bitcast float %t to i32 ; <i32> [#uses=1]
ret i32 %u
}
define float @test4(i32 %t) {
-; GISEL-LABEL: test4:
-; GISEL: # %bb.0:
-; GISEL-NEXT: movd %edi, %xmm0
-; GISEL-NEXT: retq
+; X86-LABEL: test4:
+; X86: # %bb.0:
+; X86-NEXT: flds {{[0-9]+}}(%esp)
+; X86-NEXT: retl
+;
+; X64-LABEL: test4:
+; X64: # %bb.0:
+; X64-NEXT: movd %edi, %xmm0
+; X64-NEXT: retq
%u = bitcast i32 %t to float ; <float> [#uses=1]
ret float %u
}
-
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