[llvm] [RISCV] Combine (vp.splice (insert_elt poison, scalar, 0), vec, 0, mask, 1, vl) to vslide1up. (PR #144871)
Ming Yan via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 19 03:52:39 PDT 2025
https://github.com/NexMing created https://github.com/llvm/llvm-project/pull/144871
Fold (vslideup_vl/vslidedown_vl undef, vec, 0, mask, vl, policy)
-> (vec)
Fold (vslideup_vl (insert_ele poison first, 0), vec, 1, mask, vl, policy)
-> (vslide1up_vl/vfslide1up_vl undef, vec, first, mask, vl)
>From 7f6b741f28c46013291cf8fc5c28c5885062f3a4 Mon Sep 17 00:00:00 2001
From: yanming <ming.yan at terapines.com>
Date: Thu, 19 Jun 2025 17:38:31 +0800
Subject: [PATCH 1/2] [SDPatternMatch] Add Matcher m_Poison
---
llvm/include/llvm/CodeGen/SDPatternMatch.h | 2 ++
llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/llvm/include/llvm/CodeGen/SDPatternMatch.h b/llvm/include/llvm/CodeGen/SDPatternMatch.h
index d413227c4d961..9eb6dd45f912f 100644
--- a/llvm/include/llvm/CodeGen/SDPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/SDPatternMatch.h
@@ -142,6 +142,8 @@ inline Opcode_match m_Opc(unsigned Opcode) { return Opcode_match(Opcode); }
inline Opcode_match m_Undef() { return Opcode_match(ISD::UNDEF); }
+inline Opcode_match m_Poison() { return Opcode_match(ISD::POISON); }
+
template <unsigned NumUses, typename Pattern> struct NUses_match {
Pattern P;
diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
index 2162588aadfdb..2b1fa75a1475a 100644
--- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
@@ -493,6 +493,11 @@ TEST_F(SelectionDAGPatternMatchTest, matchConstants) {
SDValue UndefVInt32VT = DAG->getUNDEF(VInt32VT);
EXPECT_TRUE(sd_match(UndefInt32VT, m_Undef()));
EXPECT_TRUE(sd_match(UndefVInt32VT, m_Undef()));
+
+ SDValue PoisonInt32VT = DAG->getPOISON(Int32VT);
+ SDValue PoisonVInt32VT = DAG->getPOISON(VInt32VT);
+ EXPECT_TRUE(sd_match(PoisonInt32VT, m_Poison()));
+ EXPECT_TRUE(sd_match(PoisonVInt32VT, m_Poison()));
}
TEST_F(SelectionDAGPatternMatchTest, patternCombinators) {
>From 4f35098ee0f53062f786c38ed6bcbec4692aab8c Mon Sep 17 00:00:00 2001
From: yanming <ming.yan at terapines.com>
Date: Thu, 19 Jun 2025 17:58:41 +0800
Subject: [PATCH 2/2] [RISCV] Combine (vp.splice (insert_elt poison, scalar,
0), vec, 0, mask, 1, vl) -> (vslideup_vl undef, vec, scalar, mask, vl)
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 33 +++++++++++++++++++++
llvm/test/CodeGen/RISCV/rvv/vp-splice.ll | 24 +++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b8ef221742a26..c17af90c57c93 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -17601,6 +17601,36 @@ static SDValue performFP_TO_INT_SATCombine(SDNode *N,
return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO);
}
+static SDValue performVSLIDEUPOrDOWNCombine(SDNode *N, SelectionDAG &DAG) {
+ assert((N->getOpcode() == RISCVISD::VSLIDEUP_VL ||
+ N->getOpcode() == RISCVISD::VSLIDEDOWN_VL) &&
+ "Unexpected opcode");
+
+ using namespace SDPatternMatch;
+
+ SDLoc DL(N);
+ SDValue Vec;
+ // (vslideup_vl/vslidedown_vl undef, vec, 0, mask, vl, policy) -> (vec)
+ if (sd_match(N, m_Node(N->getOpcode(), m_Undef(), m_Value(Vec), m_Zero(),
+ m_Value(), m_Value(), m_Value())))
+ return Vec;
+
+ SDValue FirstEle, Mask, VL;
+ // (vslideup_vl (insert_ele poison first, 0), vec, 1, mask, vl, policy)
+ // -> (vslide1up_vl/vfslide1up_vl undef, vec, first, mask, vl)
+ if (sd_match(N, m_Node(RISCVISD::VSLIDEUP_VL,
+ m_InsertElt(m_Poison(), m_Value(FirstEle), m_Zero()),
+ m_Value(Vec), m_One(), m_Value(Mask), m_Value(VL),
+ m_Value()))) {
+ EVT VT = Vec.getValueType();
+ return DAG.getNode(VT.isFloatingPoint() ? RISCVISD::VFSLIDE1UP_VL
+ : RISCVISD::VSLIDE1UP_VL,
+ DL, VT, DAG.getUNDEF(VT), Vec, FirstEle, Mask, VL);
+ }
+
+ return SDValue();
+}
+
// Combine (bitreverse (bswap X)) to the BREV8 GREVI encoding if the type is
// smaller than XLenVT.
static SDValue performBITREVERSECombine(SDNode *N, SelectionDAG &DAG,
@@ -19881,6 +19911,9 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue();
}
+ case RISCVISD::VSLIDEUP_VL:
+ case RISCVISD::VSLIDEDOWN_VL:
+ return performVSLIDEUPOrDOWNCombine(N, DAG);
case ISD::BITREVERSE:
return performBITREVERSECombine(N, DAG, Subtarget);
case ISD::FP_TO_SINT:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
index a4f91c3e7c99e..f0ff6d622cef5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll
@@ -286,3 +286,27 @@ define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float>
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
ret <vscale x 2 x float> %v
}
+
+define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
+; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
+; CHECK-NEXT: vslide1up.vx v9, v8, a0, v0.t
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
+ %va = insertelement <vscale x 2 x i32> poison, i32 %first, i32 0
+ %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
+ ret <vscale x 2 x i32> %v
+}
+
+define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
+; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT: vfslide1up.vf v9, v8, fa0, v0.t
+; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: ret
+ %va = insertelement <vscale x 2 x float> poison, float %first, i32 0
+ %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
+ ret <vscale x 2 x float> %v
+}
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