[llvm] db8e6fc - [AMDGPU] New RegBanKSelect: Add S128 types (#142601)

[via llvm-commits]

Author: Pierre van Houtryve
Date: 2025-06-19T09:58:57+02:00
New Revision: db8e6fc64534e986f5bf96cceaa76cc5007ac1c7

URL: https://github.com/llvm/llvm-project/commit/db8e6fc64534e986f5bf96cceaa76cc5007ac1c7
DIFF: https://github.com/llvm/llvm-project/commit/db8e6fc64534e986f5bf96cceaa76cc5007ac1c7.diff

LOG: [AMDGPU] New RegBanKSelect: Add S128 types (#142601)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 7ff822c6f6580..89af982636590 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -556,6 +556,9 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr64:
   case Vgpr64:
     return LLT::scalar(64);
+  case Sgpr128:
+  case Vgpr128:
+    return LLT::scalar(128);
   case VgprP0:
     return LLT::pointer(0, 64);
   case SgprP1:
@@ -646,6 +649,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr16:
   case Sgpr32:
   case Sgpr64:
+  case Sgpr128:
   case SgprP1:
   case SgprP3:
   case SgprP4:
@@ -678,6 +682,7 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr16:
   case Vgpr32:
   case Vgpr64:
+  case Vgpr128:
   case VgprP0:
   case VgprP1:
   case VgprP3:
@@ -718,6 +723,7 @@ void RegBankLegalizeHelper::applyMappingDst(
     case Sgpr16:
     case Sgpr32:
     case Sgpr64:
+    case Sgpr128:
     case SgprP1:
     case SgprP3:
     case SgprP4:
@@ -728,6 +734,7 @@ void RegBankLegalizeHelper::applyMappingDst(
     case Vgpr16:
     case Vgpr32:
     case Vgpr64:
+    case Vgpr128:
     case VgprP0:
     case VgprP1:
     case VgprP3:
@@ -839,6 +846,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
     case Sgpr16:
     case Sgpr32:
     case Sgpr64:
+    case Sgpr128:
     case SgprP1:
     case SgprP3:
     case SgprP4:
@@ -865,6 +873,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
     case Vgpr16:
     case Vgpr32:
     case Vgpr64:
+    case Vgpr128:
     case VgprP0:
     case VgprP1:
     case VgprP3:

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 5e21f44f7d545..672fc5b79abc2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -50,6 +50,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::scalar(32);
   case S64:
     return MRI.getType(Reg) == LLT::scalar(64);
+  case S128:
+    return MRI.getType(Reg) == LLT::scalar(128);
   case P0:
     return MRI.getType(Reg) == LLT::pointer(0, 64);
   case P1:
@@ -84,6 +86,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
   case UniS64:
     return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+  case UniS128:
+    return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
   case UniP0:
     return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
   case UniP1:
@@ -116,6 +120,8 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
     return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
   case DivS64:
     return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+  case DivS128:
+    return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
   case DivP0:
     return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
   case DivP1:

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index bddfb8dd1913f..30b900d871f3c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -39,16 +39,19 @@ enum UniformityLLTOpPredicateID {
   S16,
   S32,
   S64,
+  S128,
 
   UniS1,
   UniS16,
   UniS32,
   UniS64,
+  UniS128,
 
   DivS1,
   DivS16,
   DivS32,
   DivS64,
+  DivS128,
 
   // pointers
   P0,
@@ -117,6 +120,7 @@ enum RegBankLLTMappingApplyID {
   Sgpr16,
   Sgpr32,
   Sgpr64,
+  Sgpr128,
   SgprP1,
   SgprP3,
   SgprP4,
@@ -135,6 +139,7 @@ enum RegBankLLTMappingApplyID {
   Vgpr16,
   Vgpr32,
   Vgpr64,
+  Vgpr128,
   VgprP0,
   VgprP1,
   VgprP3,