[llvm] Handle VECREDUCE intrinsics in NVPTX backend (PR #136253)

[via llvm-commits]

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<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp llvm/lib/Target/NVPTX/NVPTXISelLowering.h llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
index 348a8b7ff..f78d77add 100644
--- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h
@@ -87,7 +87,9 @@ public:
   }
   unsigned getMinVectorRegisterBitWidth() const override { return 32; }
 
-  bool shouldExpandReduction(const IntrinsicInst *II) const override { return false; }
+  bool shouldExpandReduction(const IntrinsicInst *II) const override {
+    return false;
+  }
 
   // We don't want to prevent inlining because of target-cpu and -features
   // attributes that were added to newer versions of LLVM/Clang: There are

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https://github.com/llvm/llvm-project/pull/136253