[llvm] [AMDGPU][True16][CodeGen] sext i16 inreg in true16 mode (PR #144024)

[Matt Arsenault via llvm-commits]

================
@@ -2583,6 +2585,23 @@ def : GCNPat <
   (i16 (DivergentSextInreg<i8> i16:$src)),
   (V_BFE_I32_e64 $src, (i32 0), (i32 8))
 >;
+}
+
+let True16Predicate = UseRealTrue16Insts in {
+def : GCNPat <
+  (i16 (DivergentSextInreg<i1> i16:$src)),
+  (V_BFE_I32_e64
+   (REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16),
+   (i32 0), (i32 1))
+>;
----------------
arsenm wrote:

You can separately legalize the 64-bit SEXT_INREG operation to split it into a 32-bit sext_inreg + a sext. The main problem would be how much code bothers checking if SEXT_INREG is legal before introducing it in post-legalize combines

https://github.com/llvm/llvm-project/pull/144024