[llvm] [WebAssembly] Fix missed optimization in 50142 (PR #144741)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 18 16:42:31 PDT 2025
https://github.com/badumbatish updated https://github.com/llvm/llvm-project/pull/144741
>From 08246643be0239b88e62be8e38ad4c20bc113627 Mon Sep 17 00:00:00 2001
From: badumbatish <tanghocle456 at gmail.com>
Date: Wed, 18 Jun 2025 16:38:11 -0700
Subject: [PATCH 1/2] Precommit missed optimization test for #50142
---
.../WebAssembly/simd-setcc-reductions.ll | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
new file mode 100644
index 0000000000000..3424e92fba3bc
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
@@ -0,0 +1,104 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
+
+target triple = "wasm64"
+
+define i32 @all_true_16_i8(<16 x i8> %v) {
+; CHECK-LABEL: all_true_16_i8:
+; CHECK: .functype all_true_16_i8 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i8x16.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <16 x i8> %v, zeroinitializer
+ %2 = bitcast <16 x i1> %1 to i16
+ %3 = icmp eq i16 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_4_i32(<4 x i32> %v) {
+; CHECK-LABEL: all_true_4_i32:
+; CHECK: .functype all_true_4_i32 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0
+; CHECK-NEXT: i32x4.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <4 x i32> %v, zeroinitializer
+ %2 = bitcast <4 x i1> %1 to i4
+ %3 = icmp eq i4 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_8_i16(<8 x i16> %v) {
+; CHECK-LABEL: all_true_8_i16:
+; CHECK: .functype all_true_8_i16 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i16x8.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <8 x i16> %v, zeroinitializer
+ %2 = bitcast <8 x i1> %1 to i8
+ %3 = icmp eq i8 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_4_i16(<4 x i16> %v) {
+; CHECK-LABEL: all_true_4_i16:
+; CHECK: .functype all_true_4_i16 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i16x8.eq $push1=, $0, $pop0
+; CHECK-NEXT: i32x4.extend_low_i16x8_s $push2=, $pop1
+; CHECK-NEXT: v128.any_true $push3=, $pop2
+; CHECK-NEXT: i32.const $push4=, -1
+; CHECK-NEXT: i32.xor $push5=, $pop3, $pop4
+; CHECK-NEXT: i32.const $push6=, 1
+; CHECK-NEXT: i32.and $push7=, $pop5, $pop6
+; CHECK-NEXT: return $pop7
+ %1 = icmp eq <4 x i16> %v, zeroinitializer
+ %2 = bitcast <4 x i1> %1 to i4
+ %3 = icmp eq i4 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
+
+
+define i32 @all_true_2_i64(<2 x i64> %v) {
+; CHECK-LABEL: all_true_2_i64:
+; CHECK: .functype all_true_2_i64 (v128) -> (i32)
+; CHECK-NEXT: # %bb.0:
+; CHECK-NEXT: v128.const $push0=, 0, 0
+; CHECK-NEXT: i64x2.eq $push1=, $0, $pop0
+; CHECK-NEXT: v128.any_true $push2=, $pop1
+; CHECK-NEXT: i32.const $push3=, -1
+; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
+; CHECK-NEXT: i32.const $push5=, 1
+; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
+; CHECK-NEXT: return $pop6
+ %1 = icmp eq <2 x i64> %v, zeroinitializer
+ %2 = bitcast <2 x i1> %1 to i2
+ %3 = icmp eq i2 %2, 0
+ %conv3 = zext i1 %3 to i32
+ ret i32 %conv3
+}
>From 9d38a5402669ea30dcc28b979e9e47d3e03edfe5 Mon Sep 17 00:00:00 2001
From: badumbatish <tanghocle456 at gmail.com>
Date: Wed, 18 Jun 2025 09:01:16 -0700
Subject: [PATCH 2/2] Fix 50142
Fix a miss of further vectorization introduced in 50142, where we can
only achieve zext (xor (any_true), -1). Now in test case
simd-setcc-reductions.ll, it's converted to all_true.
---
.../WebAssembly/WebAssemblyISelLowering.cpp | 31 +++++++++++
.../WebAssembly/simd-setcc-reductions.ll | 52 ++++---------------
2 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 3cd923c0ba058..47f48e0af55f0 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -3248,6 +3248,37 @@ static SDValue performSETCCCombine(SDNode *N,
ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
SDLoc DL(N);
EVT VT = N->getValueType(0);
+ // N LHS LhsL LhsLL LhsLR InnerCond RHS Cond
+ // setcc (iN (bitcast (setcc vNi1 (vNiY X), <vNiY 0>, eq)), 0, eq
+ // => all_true (vNi1 X)
+ if (DCI.isBeforeLegalize() && VT.isScalarInteger() && (Cond == ISD::SETEQ) &&
+ (isNullConstant(RHS)) && LHS->getOpcode() == ISD::BITCAST) {
+ SDValue LhsL = LHS.getOperand(0);
+ EVT LhsLType = LhsL.getValueType();
+ if (LhsL.getOpcode() == ISD::SETCC) {
+ ISD::CondCode InnerCond =
+ cast<CondCodeSDNode>(LhsL->getOperand(2))->get();
+ if (InnerCond == ISD::SETEQ) {
+ SDValue LhsLL = LhsL.getOperand(0); // vNiY X
+ SDValue LhsLR = LhsL.getOperand(1); // <0>
+ unsigned NumElts = LhsLType.getVectorNumElements();
+ bool Vectorizable =
+ NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16;
+ EVT Width = MVT::getIntegerVT(128 / NumElts);
+
+ if (Vectorizable && LhsLR.getOpcode() == ISD::BUILD_VECTOR &&
+ LhsLType.isFixedLengthVector()) {
+ return DAG.getZExtOrTrunc(
+ DAG.getNode(
+ ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
+ {DAG.getConstant(Intrinsic::wasm_alltrue, DL, MVT::i32),
+ DAG.getSExtOrTrunc(
+ LhsLL, DL, LhsLType.changeVectorElementType(Width))}),
+ DL, MVT::i1);
+ }
+ }
+ }
+ }
// setcc (iN (bitcast (vNi1 X))), 0, ne
// ==> any_true (vNi1 X)
diff --git a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
index 3424e92fba3bc..36d64446e40ec 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-setcc-reductions.ll
@@ -7,14 +7,8 @@ define i32 @all_true_16_i8(<16 x i8> %v) {
; CHECK-LABEL: all_true_16_i8:
; CHECK: .functype all_true_16_i8 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: i8x16.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i8x16.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <16 x i8> %v, zeroinitializer
%2 = bitcast <16 x i1> %1 to i16
%3 = icmp eq i16 %2, 0
@@ -27,14 +21,8 @@ define i32 @all_true_4_i32(<4 x i32> %v) {
; CHECK-LABEL: all_true_4_i32:
; CHECK: .functype all_true_4_i32 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0
-; CHECK-NEXT: i32x4.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i32x4.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <4 x i32> %v, zeroinitializer
%2 = bitcast <4 x i1> %1 to i4
%3 = icmp eq i4 %2, 0
@@ -47,14 +35,8 @@ define i32 @all_true_8_i16(<8 x i16> %v) {
; CHECK-LABEL: all_true_8_i16:
; CHECK: .functype all_true_8_i16 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: i16x8.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i16x8.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <8 x i16> %v, zeroinitializer
%2 = bitcast <8 x i1> %1 to i8
%3 = icmp eq i8 %2, 0
@@ -67,15 +49,9 @@ define i32 @all_true_4_i16(<4 x i16> %v) {
; CHECK-LABEL: all_true_4_i16:
; CHECK: .functype all_true_4_i16 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0, 0, 0, 0, 0, 0, 0
-; CHECK-NEXT: i16x8.eq $push1=, $0, $pop0
-; CHECK-NEXT: i32x4.extend_low_i16x8_s $push2=, $pop1
-; CHECK-NEXT: v128.any_true $push3=, $pop2
-; CHECK-NEXT: i32.const $push4=, -1
-; CHECK-NEXT: i32.xor $push5=, $pop3, $pop4
-; CHECK-NEXT: i32.const $push6=, 1
-; CHECK-NEXT: i32.and $push7=, $pop5, $pop6
-; CHECK-NEXT: return $pop7
+; CHECK-NEXT: i32x4.extend_low_i16x8_s $push0=, $0
+; CHECK-NEXT: i32x4.all_true $push1=, $pop0
+; CHECK-NEXT: return $pop1
%1 = icmp eq <4 x i16> %v, zeroinitializer
%2 = bitcast <4 x i1> %1 to i4
%3 = icmp eq i4 %2, 0
@@ -88,14 +64,8 @@ define i32 @all_true_2_i64(<2 x i64> %v) {
; CHECK-LABEL: all_true_2_i64:
; CHECK: .functype all_true_2_i64 (v128) -> (i32)
; CHECK-NEXT: # %bb.0:
-; CHECK-NEXT: v128.const $push0=, 0, 0
-; CHECK-NEXT: i64x2.eq $push1=, $0, $pop0
-; CHECK-NEXT: v128.any_true $push2=, $pop1
-; CHECK-NEXT: i32.const $push3=, -1
-; CHECK-NEXT: i32.xor $push4=, $pop2, $pop3
-; CHECK-NEXT: i32.const $push5=, 1
-; CHECK-NEXT: i32.and $push6=, $pop4, $pop5
-; CHECK-NEXT: return $pop6
+; CHECK-NEXT: i64x2.all_true $push0=, $0
+; CHECK-NEXT: return $pop0
%1 = icmp eq <2 x i64> %v, zeroinitializer
%2 = bitcast <2 x i1> %1 to i2
%3 = icmp eq i2 %2, 0
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