[llvm] [RISCV] Update SpacemiT X60 scheduling latencies based on hardware measurements (PR #144730)
Mikhail R. Gadelha via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 18 14:31:49 PDT 2025
https://github.com/mikhailramalho updated https://github.com/llvm/llvm-project/pull/144730
>From 715b4a4859dcba615315fb4a7a321a221105388e Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Mon, 16 Jun 2025 11:48:50 -0300
Subject: [PATCH 1/3] Update latency for load and store instructions
Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
---
llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 8948694c420a0..92835f12007d7 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -16,7 +16,7 @@
def SpacemitX60Model : SchedMachineModel {
let IssueWidth = 2; // dual-issue
let MicroOpBufferSize = 0; // in-order
- let LoadLatency = 5; // worse case: >= 3
+ let LoadLatency = 3; // worse case: >= 3
let MispredictPenalty = 9; // nine-stage
let CompleteModel = 0;
@@ -114,7 +114,7 @@ def : WriteRes<WriteBEXT, [SMX60_IEU]>;
def : WriteRes<WriteBEXTI, [SMX60_IEU]>;
// Memory/Atomic memory
-let Latency = 3 in {
+let Latency = 4 in {
def : WriteRes<WriteSTB, [SMX60_LS]>;
def : WriteRes<WriteSTH, [SMX60_LS]>;
def : WriteRes<WriteSTW, [SMX60_LS]>;
@@ -122,11 +122,7 @@ let Latency = 3 in {
def : WriteRes<WriteFST16, [SMX60_LS]>;
def : WriteRes<WriteFST32, [SMX60_LS]>;
def : WriteRes<WriteFST64, [SMX60_LS]>;
- def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
- def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
-}
-let Latency = 5 in {
def : WriteRes<WriteLDB, [SMX60_LS]>;
def : WriteRes<WriteLDH, [SMX60_LS]>;
def : WriteRes<WriteLDW, [SMX60_LS]>;
@@ -137,9 +133,14 @@ let Latency = 5 in {
}
// Atomics
-let Latency = 5 in {
+let Latency = 9 in {
+ def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
+ def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
def : WriteRes<WriteAtomicLDW, [SMX60_LS]>;
def : WriteRes<WriteAtomicLDD, [SMX60_LS]>;
+}
+
+let Latency = 13 in {
def : WriteRes<WriteAtomicW, [SMX60_LS]>;
def : WriteRes<WriteAtomicD, [SMX60_LS]>;
}
>From 9ac6f7b42b222a53e2e9c5fa30439242b0e41507 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Tue, 17 Jun 2025 10:50:42 -0300
Subject: [PATCH 2/3] Reduce it slightly
Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
---
llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 92835f12007d7..9059d5a4e497b 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -133,14 +133,14 @@ let Latency = 4 in {
}
// Atomics
-let Latency = 9 in {
+let Latency = 8 in {
def : WriteRes<WriteAtomicSTW, [SMX60_LS]>;
def : WriteRes<WriteAtomicSTD, [SMX60_LS]>;
def : WriteRes<WriteAtomicLDW, [SMX60_LS]>;
def : WriteRes<WriteAtomicLDD, [SMX60_LS]>;
}
-let Latency = 13 in {
+let Latency = 12 in {
def : WriteRes<WriteAtomicW, [SMX60_LS]>;
def : WriteRes<WriteAtomicD, [SMX60_LS]>;
}
>From 6f34ca08660e1823969dcdf92208cfc85432b33d Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail at igalia.com>
Date: Wed, 18 Jun 2025 18:31:35 -0300
Subject: [PATCH 3/3] Updated test cases
Signed-off-by: Mikhail R. Gadelha <mikhail at igalia.com>
---
.../tools/llvm-mca/RISCV/SpacemitX60/atomic.s | 176 +++++++++---------
.../RISCV/SpacemitX60/floating-point.s | 12 +-
.../llvm-mca/RISCV/SpacemitX60/integer.s | 22 +--
3 files changed, 105 insertions(+), 105 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
index ceab015e27203..bc9229471b20e 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/atomic.s
@@ -120,94 +120,94 @@ amomaxu.d.aqrl s5, s4, (s3)
# CHECK-NEXT: [9]: LLVM Opcode Name
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W lr.w t0, (t1)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W_AQ lr.w.aq t1, (t2)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W_RL lr.w.rl t2, (t3)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_W_AQ_RL lr.w.aqrl t3, (t4)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W sc.w t6, t5, (t4)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W_AQ sc.w.aq t5, t4, (t3)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W_RL sc.w.rl t4, t3, (t2)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_W_AQ_RL sc.w.aqrl t3, t2, (t1)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D lr.d t0, (t1)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D_AQ lr.d.aq t1, (t2)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D_RL lr.d.rl t2, (t3)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LR_D_AQ_RL lr.d.aqrl t3, (t4)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D sc.d t6, t5, (t4)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D_AQ sc.d.aq t5, t4, (t3)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D_RL sc.d.rl t4, t3, (t2)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SC_D_AQ_RL sc.d.aqrl t3, t2, (t1)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W amoswap.w a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W amoadd.w a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W amoxor.w a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W amoand.w a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W amoor.w a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W amomin.w a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W amomax.w s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W amominu.w s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W amomaxu.w s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W_AQ amoswap.w.aq a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W_AQ amoadd.w.aq a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W_AQ amoxor.w.aq a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W_AQ amoand.w.aq a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W_AQ amoor.w.aq a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W_AQ amomin.w.aq a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W_AQ amomax.w.aq s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W_AQ amominu.w.aq s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W_AQ amomaxu.w.aq s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W_RL amoswap.w.rl a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W_RL amoadd.w.rl a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W_RL amoxor.w.rl a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W_RL amoand.w.rl a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W_RL amoor.w.rl a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W_RL amomin.w.rl a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_W_AQ_RL amoswap.w.aqrl a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_W_AQ_RL amoadd.w.aqrl a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_W_AQ_RL amoxor.w.aqrl a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_W_AQ_RL amoand.w.aqrl a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_W_AQ_RL amoor.w.aqrl a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_W_AQ_RL amomin.w.aqrl a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_W_AQ_RL amomax.w.aqrl s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_W_AQ_RL amominu.w.aqrl s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_W_AQ_RL amomaxu.w.aqrl s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D amoswap.d a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D amoadd.d a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D amoxor.d a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D amoand.d a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D amoor.d a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D amomin.d a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D amomax.d s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D amominu.d s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D amomaxu.d s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D_AQ amoswap.d.aq a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D_AQ amoadd.d.aq a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D_AQ amoxor.d.aq a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D_AQ amoand.d.aq a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D_AQ amoor.d.aq a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D_AQ amomin.d.aq a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D_AQ amomax.d.aq s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D_AQ amominu.d.aq s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D_AQ amomaxu.d.aq s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D_RL amoswap.d.rl a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D_RL amoadd.d.rl a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D_RL amoxor.d.rl a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D_RL amoand.d.rl a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D_RL amoor.d.rl a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D_RL amomin.d.rl a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOSWAP_D_AQ_RL amoswap.d.aqrl a4, ra, (s0)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOADD_D_AQ_RL amoadd.d.aqrl a1, a2, (a3)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOXOR_D_AQ_RL amoxor.d.aqrl a2, a3, (a4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOAND_D_AQ_RL amoand.d.aqrl a3, a4, (a5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOOR_D_AQ_RL amoor.d.aqrl a4, a5, (a6)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMIN_D_AQ_RL amomin.d.aqrl a5, a6, (a7)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAX_D_AQ_RL amomax.d.aqrl s7, s6, (s5)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMINU_D_AQ_RL amominu.d.aqrl s6, s5, (s4)
-# CHECK-NEXT: 1 5 0.50 * * 5 SMX60_LS AMOMAXU_D_AQ_RL amomaxu.d.aqrl s5, s4, (s3)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W lr.w t0, (t1)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ lr.w.aq t1, (t2)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_RL lr.w.rl t2, (t3)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_W_AQ_RL lr.w.aqrl t3, (t4)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W sc.w t6, t5, (t4)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_RL sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_W_AQ_RL sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D lr.d t0, (t1)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ lr.d.aq t1, (t2)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_RL lr.d.rl t2, (t3)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS LR_D_AQ_RL lr.d.aqrl t3, (t4)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D sc.d t6, t5, (t4)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_RL sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: 1 8 0.50 * 8 SMX60_LS SC_D_AQ_RL sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W amoswap.w a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W amoadd.w a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W amoxor.w a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W amoand.w a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W amoor.w a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W amomin.w a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W amomax.w s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W amominu.w s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQ amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQ amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQ amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQ amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQ amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQ amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQ amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQ amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQ amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_RL amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_RL amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_RL amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_RL amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_RL amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_RL amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_W_AQ_RL amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_W_AQ_RL amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_W_AQ_RL amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_W_AQ_RL amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_W_AQ_RL amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_W_AQ_RL amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_W_AQ_RL amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_W_AQ_RL amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_W_AQ_RL amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D amoswap.d a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D amoadd.d a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D amoxor.d a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D amoand.d a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D amoor.d a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D amomin.d a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D amomax.d s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D amominu.d s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQ amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQ amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQ amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQ amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQ amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQ amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQ amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQ amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQ amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_RL amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_RL amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_RL amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_RL amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_RL amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_RL amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOSWAP_D_AQ_RL amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOADD_D_AQ_RL amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOXOR_D_AQ_RL amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOAND_D_AQ_RL amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOOR_D_AQ_RL amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMIN_D_AQ_RL amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAX_D_AQ_RL amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMINU_D_AQ_RL amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 12 0.50 * * 12 SMX60_LS AMOMAXU_D_AQ_RL amomaxu.d.aqrl s5, s4, (s3)
# CHECK: Resources:
# CHECK-NEXT: [0] - SMX60_FP
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
index bd3666ef7bb9f..b86fcbccbeabb 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/floating-point.s
@@ -148,12 +148,12 @@ fclass.d a3, ft10
# CHECK-NEXT: [9]: LLVM Opcode Name
# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS FLH flh ft0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS FSH fsh ft0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS FLW flw ft0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS FSW fsw ft0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS FLD fld ft0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS FSD fsd ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSH fsh ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLW flw ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSW fsw ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FLD fld ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS FSD fsd ft0, 0(a0)
# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FADD_H fadd.h fs10, fs11, ft8
# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FSUB_H fsub.h ft9, ft10, ft11
# CHECK-NEXT: 1 4 1.00 4 SMX60_FP FMUL_H fmul.h ft0, ft1, ft2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
index 8b43874499f2b..b72540f29f487 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX60/integer.s
@@ -222,17 +222,17 @@ bseti a0, a1, 1
# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGE bge a0, a0, .Ltmp5
# CHECK-NEXT: 1 1 1.00 1 SMX60_IEU,SMX60_IEUA BGEU bgeu a0, a0, .Ltmp6
# CHECK-NEXT: 1 1 0.50 1 SMX60_IEU C_ADD add a0, a0, a0
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LB lb t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LBU lbu t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LH lh t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LHU lhu t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LW lw t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LWU lwu t0, 0(a0)
-# CHECK-NEXT: 1 5 0.50 * 5 SMX60_LS LD ld t0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SB sb t0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SH sh t0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SW sw t0, 0(a0)
-# CHECK-NEXT: 1 3 0.50 * 3 SMX60_LS SD sd t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LB lb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LBU lbu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LH lh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LHU lhu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LW lw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LWU lwu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS LD ld t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SB sb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SH sh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SW sw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 SMX60_LS SD sd t0, 0(a0)
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MUL mul a0, a0, a0
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULH mulh a0, a0, a0
# CHECK-NEXT: 1 6 0.50 6 SMX60_IEU MULHU mulhu a0, a0, a0
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