[llvm] [AMDGPU][SDAG] Legalise v2i32 or/xor/and instructions to make use of 64-bit wide instructions (PR #140694)

[via llvm-commits]

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@@ -4056,6 +4056,58 @@ SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
   SDLoc SL(N);
   SelectionDAG &DAG = DCI.DAG;
 
+  // When the shl64_reduce optimisation code is passed through vector
+  // legalization //some scalarising occurs. After ISD::AND was legalised, this
+  // resulted in the AND instructions no longer being elided, as mentioned
+  // below. The following code should make sure this takes place.
+  // ConstantSDNode *CVANDRHS = dyn_cast<ConstantSDNode>(RHS->getOperand(1));
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LU-JOHN wrote:

Does a similar problem for eliding AND also occur in performSrlCombine?  This should be tested in srl64_reduce.ll.

Also PR https://github.com/llvm/llvm-project/pull/144421 will add a similar 64-bit to 32-bit reduction for performSraCombine.

https://github.com/llvm/llvm-project/pull/140694