[llvm] keep src mod and clamp for v_s_xxx_f16 lowering (PR #144781)

via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 18 11:53:04 PDT 2025


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
``````````

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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d9c10bce7..2b4d6a35d 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7746,8 +7746,8 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist,
     auto NewInstr = BuildMI(*MBB, Inst, DL, get(NewOpcode), NewDst)
                         .add(Inst.getOperand(1)) // src0_modifiers
                         .add(Inst.getOperand(2))
-                        .add(Inst.getOperand(3)) // clamp
-                        .add(Inst.getOperand(4));// omod
+                        .add(Inst.getOperand(3))  // clamp
+                        .add(Inst.getOperand(4)); // omod
     if (AMDGPU::hasNamedOperand(NewOpcode, AMDGPU::OpName::op_sel))
       NewInstr.addImm(0); // opsel0
     MRI.replaceRegWith(Inst.getOperand(0).getReg(), NewDst);

``````````

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https://github.com/llvm/llvm-project/pull/144781


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