[llvm] [TTI] Remove PPC hasActiveVectorLength impl, simplify interface (NFC). (PR #142310)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 18 11:02:00 PDT 2025
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/142310
>From 778875c12e268b4a7c9c3d5bc7dcf4e718dfc76c Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Sun, 1 Jun 2025 15:29:27 +0100
Subject: [PATCH 1/3] [TTI] Remove PPC hasActiveVectorLength impl, simplify
interface (NFC).
PPCTTIImpl defines hasActiveVectorLength and also getVPMemoryOpCost, but
they appear unused (i.e. no changes to tests).
Remove them, as they complicate the interface for hasActiveVectorLength.
This simplifies the only use in LV as now no placeholder values need to be
passed.
---
.../llvm/Analysis/TargetTransformInfo.h | 3 +-
.../llvm/Analysis/TargetTransformInfoImpl.h | 5 +-
llvm/lib/Analysis/TargetTransformInfo.cpp | 5 +-
.../Target/PowerPC/PPCTargetTransformInfo.cpp | 82 -------------------
.../Target/PowerPC/PPCTargetTransformInfo.h | 6 --
.../Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +-
.../Target/RISCV/RISCVTargetTransformInfo.h | 9 +-
.../Transforms/Vectorize/LoopVectorize.cpp | 4 +-
8 files changed, 7 insertions(+), 109 deletions(-)
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 8f4ce80ada5ed..ce4f8e4f9ceb9 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1853,8 +1853,7 @@ class TargetTransformInfo {
/// in hardware, for the given opcode and type/alignment. (see LLVM Language
/// Reference - "Vector Predication Intrinsics").
/// Use of %evl is discouraged when that is not the case.
- LLVM_ABI bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
- Align Alignment) const;
+ LLVM_ABI bool hasActiveVectorLength() const;
/// Return true if sinking I's operands to the same basic block as I is
/// profitable, e.g. because the operands can be folded into a target
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index a80b4c5179bad..d933752183949 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -1108,10 +1108,7 @@ class TargetTransformInfoImplBase {
virtual bool enableScalableVectorization() const { return false; }
- virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
- Align Alignment) const {
- return false;
- }
+ virtual bool hasActiveVectorLength() const { return false; }
virtual bool isProfitableToSinkOperands(Instruction *I,
SmallVectorImpl<Use *> &Ops) const {
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index 2d053e55bdfa9..d9cb11de9c097 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -1454,9 +1454,8 @@ bool TargetTransformInfo::enableScalableVectorization() const {
return TTIImpl->enableScalableVectorization();
}
-bool TargetTransformInfo::hasActiveVectorLength(unsigned Opcode, Type *DataType,
- Align Alignment) const {
- return TTIImpl->hasActiveVectorLength(Opcode, DataType, Alignment);
+bool TargetTransformInfo::hasActiveVectorLength() const {
+ return TTIImpl->hasActiveVectorLength();
}
bool TargetTransformInfo::isProfitableToSinkOperands(
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index f9e77f2abdca2..cd9b226ca82dc 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1027,88 +1027,6 @@ bool PPCTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
return false;
}
-bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType,
- Align Alignment) const {
- // Only load and stores instructions can have variable vector length on Power.
- if (Opcode != Instruction::Load && Opcode != Instruction::Store)
- return false;
- // Loads/stores with length instructions use bits 0-7 of the GPR operand and
- // therefore cannot be used in 32-bit mode.
- if ((!ST->hasP9Vector() && !ST->hasP10Vector()) || !ST->isPPC64())
- return false;
- if (isa<FixedVectorType>(DataType)) {
- unsigned VecWidth = DataType->getPrimitiveSizeInBits();
- return VecWidth == 128;
- }
- Type *ScalarTy = DataType->getScalarType();
-
- if (ScalarTy->isPointerTy())
- return true;
-
- if (ScalarTy->isFloatTy() || ScalarTy->isDoubleTy())
- return true;
-
- if (!ScalarTy->isIntegerTy())
- return false;
-
- unsigned IntWidth = ScalarTy->getIntegerBitWidth();
- return IntWidth == 8 || IntWidth == 16 || IntWidth == 32 || IntWidth == 64;
-}
-
-InstructionCost PPCTTIImpl::getVPMemoryOpCost(unsigned Opcode, Type *Src,
- Align Alignment,
- unsigned AddressSpace,
- TTI::TargetCostKind CostKind,
- const Instruction *I) const {
- InstructionCost Cost = BaseT::getVPMemoryOpCost(Opcode, Src, Alignment,
- AddressSpace, CostKind, I);
- if (TLI->getValueType(DL, Src, true) == MVT::Other)
- return Cost;
- // TODO: Handle other cost kinds.
- if (CostKind != TTI::TCK_RecipThroughput)
- return Cost;
-
- assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
- "Invalid Opcode");
-
- auto *SrcVTy = dyn_cast<FixedVectorType>(Src);
- assert(SrcVTy && "Expected a vector type for VP memory operations");
-
- if (hasActiveVectorLength(Opcode, Src, Alignment)) {
- std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(SrcVTy);
-
- InstructionCost CostFactor =
- vectorCostAdjustmentFactor(Opcode, Src, nullptr);
- if (!CostFactor.isValid())
- return InstructionCost::getMax();
-
- InstructionCost Cost = LT.first * CostFactor;
- assert(Cost.isValid() && "Expected valid cost");
-
- // On P9 but not on P10, if the op is misaligned then it will cause a
- // pipeline flush. Otherwise the VSX masked memops cost the same as unmasked
- // ones.
- const Align DesiredAlignment(16);
- if (Alignment >= DesiredAlignment || ST->getCPUDirective() != PPC::DIR_PWR9)
- return Cost;
-
- // Since alignment may be under estimated, we try to compute the probability
- // that the actual address is aligned to the desired boundary. For example
- // an 8-byte aligned load is assumed to be actually 16-byte aligned half the
- // time, while a 4-byte aligned load has a 25% chance of being 16-byte
- // aligned.
- float AlignmentProb = ((float)Alignment.value()) / DesiredAlignment.value();
- float MisalignmentProb = 1.0 - AlignmentProb;
- return (MisalignmentProb * P9PipelineFlushEstimate) +
- (AlignmentProb * Cost.getValue());
- }
-
- // Usually we should not get to this point, but the following is an attempt to
- // model the cost of legalization. Currently we can only lower intrinsics with
- // evl but no mask, on Power 9/10. Otherwise, we must scalarize.
- return getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
-}
-
bool PPCTTIImpl::supportsTailCallFor(const CallBase *CB) const {
return TLI->supportsTailCallFor(CB);
}
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 8618f3064c188..bc5f7a4d06de1 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -148,12 +148,6 @@ class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> {
const Function *Callee) const override;
bool areTypesABICompatible(const Function *Caller, const Function *Callee,
const ArrayRef<Type *> &Types) const override;
- bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
- Align Alignment) const override;
- InstructionCost
- getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
- unsigned AddressSpace, TTI::TargetCostKind CostKind,
- const Instruction *I = nullptr) const override;
bool supportsTailCallFor(const CallBase *CB) const override;
private:
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 46e30ce4c18a9..63c5f17a84872 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -282,7 +282,7 @@ RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
return TTI::TCC_Free;
}
-bool RISCVTTIImpl::hasActiveVectorLength(unsigned, Type *DataTy, Align) const {
+bool RISCVTTIImpl::hasActiveVectorLength() const {
return ST->hasVInstructions();
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index dd7e9f7709f8e..fdcced152bd9b 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -95,14 +95,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
/// https://llvm.org/docs/LangRef.html#vector-predication-intrinsics and
/// "IR-level VP intrinsics",
/// https://llvm.org/docs/Proposals/VectorPredication.html#ir-level-vp-intrinsics).
- /// \param Opcode the opcode of the instruction checked for predicated version
- /// support.
- /// \param DataType the type of the instruction with the \p Opcode checked for
- /// prediction support.
- /// \param Alignment the alignment for memory access operation checked for
- /// predicated version support.
- bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
- Align Alignment) const override;
+ bool hasActiveVectorLength() const override;
TargetTransformInfo::PopcntSupportKind
getPopcntSupport(unsigned TyWidth) const override;
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 2f4416d2782e8..3b16248f962bc 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -1377,11 +1377,9 @@ class LoopVectorizationCostModel {
if (ForceTailFoldingStyle != TailFoldingStyle::DataWithEVL)
return;
// Override forced styles if needed.
- // FIXME: use actual opcode/data type for analysis here.
// FIXME: Investigate opportunity for fixed vector factor.
bool EVLIsLegal = UserIC <= 1 && IsScalableVF &&
- TTI.hasActiveVectorLength(0, nullptr, Align()) &&
- !EnableVPlanNativePath;
+ TTI.hasActiveVectorLength() && !EnableVPlanNativePath;
if (!EVLIsLegal) {
// If for some reason EVL mode is unsupported, fallback to
// DataWithoutLaneMask to try to vectorize the loop with folded tail
>From fe57f55fc77fdfee0e6ae65d5942875d24e782a1 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Wed, 18 Jun 2025 14:12:35 +0100
Subject: [PATCH 2/3] !fixup adjust comments
---
llvm/include/llvm/Analysis/TargetTransformInfo.h | 5 ++---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 ++--
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index ce4f8e4f9ceb9..9dc4eca82492e 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -1850,9 +1850,8 @@ class TargetTransformInfo {
/// \name Vector Predication Information
/// @{
/// Whether the target supports the %evl parameter of VP intrinsic efficiently
- /// in hardware, for the given opcode and type/alignment. (see LLVM Language
- /// Reference - "Vector Predication Intrinsics").
- /// Use of %evl is discouraged when that is not the case.
+ /// in hardware. (see LLVM Language Reference - "Vector Predication
+ /// Intrinsics"). Use of %evl is discouraged when that is not the case.
LLVM_ABI bool hasActiveVectorLength() const;
/// Return true if sinking I's operands to the same basic block as I is
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index fdcced152bd9b..aedf152966b35 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -90,8 +90,8 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
/// \name EVL Support for predicated vectorization.
/// Whether the target supports the %evl parameter of VP intrinsic efficiently
- /// in hardware, for the given opcode and type/alignment. (see LLVM Language
- /// Reference - "Vector Predication Intrinsics",
+ /// in hardware (see LLVM Language Reference - "Vector Predication
+ /// Intrinsics",
/// https://llvm.org/docs/LangRef.html#vector-predication-intrinsics and
/// "IR-level VP intrinsics",
/// https://llvm.org/docs/Proposals/VectorPredication.html#ir-level-vp-intrinsics).
>From d4d3872e604c6155320ebca8d9ec27732a2a28bf Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Wed, 18 Jun 2025 19:01:29 +0100
Subject: [PATCH 3/3] !fixup add back period.
---
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index aedf152966b35..75d377abb0e7d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -90,7 +90,7 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
/// \name EVL Support for predicated vectorization.
/// Whether the target supports the %evl parameter of VP intrinsic efficiently
- /// in hardware (see LLVM Language Reference - "Vector Predication
+ /// in hardware. (see LLVM Language Reference - "Vector Predication
/// Intrinsics",
/// https://llvm.org/docs/LangRef.html#vector-predication-intrinsics and
/// "IR-level VP intrinsics",
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